[U-Boot] [PATCH v2 0/2] SiFive UART support

[Anup Patel]

On Tue, Dec 11, 2018 at 9:45 PM Bin Meng <bmeng.cn at gmail.com> wrote:
>
> Hi Anup,
>
> On Wed, Dec 12, 2018 at 12:07 AM Anup Patel <anup at brainfault.org> wrote:
> >
> > On Tue, Dec 11, 2018 at 9:03 PM Bin Meng <bmeng.cn at gmail.com> wrote:
> > >
> > > Hi Anup,
> > >
> > > On Tue, Dec 11, 2018 at 11:02 PM Anup Patel <anup at brainfault.org> wrote:
> > > >
> > > > This patchset adds SiFive UART driver for SiFive UART
> > > > found on SiFive boards.
> > > >
> > > > The driver is tested on QEMU sifive_u machine. In fact,
> > > > with this patchset same U-Boot binary boots on QEMU virt
> > > > machine and QEMU sifive_u machine in both M-mode and
> > > > S-mode.
> > > >
> > >
> > > Could you please specify how to test this? I tried your v1 patch but
> > > U-Boot did not boot. I must have missed something ...
> >
> > To try this patches in M-mode do the following (in u-boot source directory):
> > # ARCH=riscv
> > # CROSS_COMPILE=riscv64-unknown-linux-gnu-
> > # make qemu-riscv64_defconfig
> > # make
> > # qemu-system-riscv64 -M sifive_u -m 256M -display none -serial stdio
> > -kernel ./u-boot
>
> I tried exactly the same, but no console output.
>

Ahh, understood your problem.

There is a bug in QEMU FDT generation for sifive_u.

Here's the QEMU fix (which I have send to QEMU mailing list):

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From: Anup Patel <anup at brainfault.org>
To: qemu-riscv at nongnu.org
Cc: Anup Patel <anup at brainfault.org>
Subject: [PATCH 2/2] hw/riscv/sifive_u: Set 'clock-frequency' DT
property for SiFive UART
Date: Wed,
  5 Dec 2018 13:57:03 +0530
Message-Id: <20181205082703.13945-2-anup at brainfault.org>
X-Mailer: git-send-email 2.17.1
In-Reply-To: <20181205082703.13945-1-anup at brainfault.org>
References: <20181205082703.13945-1-anup at brainfault.org>

The 'clock-frequency' DT property is required by U-Boot to compute
divider value. This patch sets 'clock-frequency' DT property of
SiFive UART DT node (similar to virt machine).

Signed-off-by: Anup Patel <anup at brainfault.org>
---
 hw/riscv/sifive_u.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b3a4352986..5fa666fefc 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -238,6 +238,8 @@ static void create_fdt(SiFiveUState *s, const
struct MemmapEntry *memmap,
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
         0x0, memmap[SIFIVE_U_UART0].base,
         0x0, memmap[SIFIVE_U_UART0].size);
+    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+        SIFIVE_U_CLOCK_FREQ / 2);
     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);

-- 
2.17.1


Regards,
Anup