[U-Boot] [PATCH v5 00/25] riscv: Adding RISC-V CPU and timer driver

[Bin Meng]

This adds DM drivers to support RISC-V CPU and timer, plus some bug fixes.

This series is available at u-boot-x86/riscv-working for testing.

Changes in v5:
- Introduced another Kconfig option for the cache ops on AX25 CPU,
  so that it remains selectable in Kconfig menu, but only visible
  to AX25 platform.
- check if dev is valid, otherwise print a warning

Changes in v4:
- print warnings for S-mode without CONFIG_CPU

Changes in v3:
- remove 'select RISCV_CLINT' in Kconfig
- do not mention the spec version number v1.10
- adjust riscv_get_time() API signature to have a return value
- check return value of syscon_get_first_range()
- probe cpus in the pre-relocation stage too
- new patch to remove non-DM version of print_cpuinfo()
- add sedeleg (0x102) and sideleg (0x103) CSRs
- new patch to update supports_extension() to use desc from cpu driver
- only initialize mcounteren CSR for S-mode
- only touch satp in M-mode U-Boot
- move the implementation to arch_cpu_init_dm()
- new patch to save boot hart id to the global data
- new patch to change to use boot_hart from global data
- new patch to remove ae350.dts

Changes in v2:
- Use 'Hz' instead of 'HZ'
- add DM_FLAG_PRE_RELOC flag to the simple-bus driver
- pass NULL as the timer device to device_bind_with_driver_data()
- remove the probe to syscon driver in the timer probe, to make the
  driver generic, and rely on platform codes to provide the API
  riscv_get_time().
- incorporated and reworked Anup's S-mode timer patch
  @ http://patchwork.ozlabs.org/patch/1006663/
- rename the driver name to sifive_clint
- save the clint base address to arch specific global data to support
  pre-relocation stage
- remove the probe routine
- add riscv_clear_ipi() API
- incorporated and reworked Anup's S-mode timer patch
  @ http://patchwork.ozlabs.org/patch/1006663/
- add CMD_CPU as well
- move to arch/riscv/cpu/cpu.c
- new patch to add indirect stringification to csr_xxx ops
- use csr_set() to set MSTATUS_FS
- only enabling the cycle, time, and instret counters
- change to use satp
- rebase on u-boot/master
- drop the patch "riscv: Pass correct exception code to _exit_trap()"
- drop the patch "riscv: Refactor handle_trap() a little for future extension"
- drop the patch "riscv: Allow U-Boot to run on hart 0 only", and
  leave the SMP support to Lukas's future patch series

Anup Patel (2):
  riscv: Introduce a Kconfig option for machine mode
  riscv: Implement riscv_get_time() API using rdtime instruction

Bin Meng (22):
  dm: cpu: Add timebase frequency to the platdata
  riscv: qemu: Create a simple-bus driver for the soc node
  cpu: Add a RISC-V CPU driver
  timer: Add generic driver for RISC-V privileged architecture defined
    timer
  riscv: ax25: Hide the ax25-specific Kconfig option
  riscv: Add a SYSCON driver for SiFive's Core Local Interruptor
  riscv: qemu: Add platform-specific Kconfig options
  riscv: Enlarge the default SYS_MALLOC_F_LEN
  riscv: Probe cpus during boot
  riscv: Remove non-DM version of print_cpuinfo()
  riscv: Add CSR numbers
  riscv: Add exception codes for xcause register
  riscv: Update supports_extension() to use desc from cpu driver
  riscv: Add indirect stringification to csr_xxx ops
  riscv: Do some basic architecture level cpu initialization
  riscv: Move trap handler codes to mtrap.S
  riscv: Fix context restore before returning from trap handler
  riscv: Return to previous privilege level after trap handling
  riscv: Adjust the _exit_trap() position to come before handle_trap()
  riscv: Save boot hart id to the global data
  riscv: bootm: Change to use boot_hart from global data
  riscv: Remove ae350.dts

Lukas Auer (1):
  riscv: add Kconfig entries for the code model

 arch/riscv/Kconfig                   |  60 ++++++++-
 arch/riscv/Makefile                  |   9 +-
 arch/riscv/cpu/Makefile              |   2 +-
 arch/riscv/cpu/ax25/Kconfig          |  17 ++-
 arch/riscv/cpu/ax25/cache.c          |  12 +-
 arch/riscv/cpu/cpu.c                 |  98 ++++++++++-----
 arch/riscv/cpu/mtrap.S               | 103 +++++++++++++++
 arch/riscv/cpu/qemu/Kconfig          |  12 ++
 arch/riscv/cpu/qemu/cpu.c            |  14 +++
 arch/riscv/cpu/start.S               |  93 +-------------
 arch/riscv/dts/ae350.dts             | 229 ---------------------------------
 arch/riscv/include/asm/csr.h         |  16 +--
 arch/riscv/include/asm/encoding.h    | 236 +++++++++++++++++++++++++++++++++++
 arch/riscv/include/asm/global_data.h |   4 +
 arch/riscv/include/asm/syscon.h      |  19 +++
 arch/riscv/lib/Makefile              |   2 +
 arch/riscv/lib/asm-offsets.c         |  19 +++
 arch/riscv/lib/bootm.c               |   2 +-
 arch/riscv/lib/interrupts.c          |  62 +++++----
 arch/riscv/lib/rdtime.c              |  38 ++++++
 arch/riscv/lib/sifive_clint.c        |  84 +++++++++++++
 board/AndesTech/ax25-ae350/Kconfig   |   4 +
 board/emulation/qemu-riscv/Kconfig   |   1 +
 drivers/cpu/Kconfig                  |   6 +
 drivers/cpu/Makefile                 |   1 +
 drivers/cpu/riscv_cpu.c              | 116 +++++++++++++++++
 drivers/timer/Kconfig                |   7 ++
 drivers/timer/Makefile               |   1 +
 drivers/timer/riscv_timer.c          |  56 +++++++++
 include/cpu.h                        |   3 +
 30 files changed, 921 insertions(+), 405 deletions(-)
 create mode 100644 arch/riscv/cpu/mtrap.S
 create mode 100644 arch/riscv/cpu/qemu/Kconfig
 delete mode 100644 arch/riscv/dts/ae350.dts
 create mode 100644 arch/riscv/include/asm/syscon.h
 create mode 100644 arch/riscv/lib/asm-offsets.c
 create mode 100644 arch/riscv/lib/rdtime.c
 create mode 100644 arch/riscv/lib/sifive_clint.c
 create mode 100644 drivers/cpu/riscv_cpu.c
 create mode 100644 drivers/timer/riscv_timer.c

-- 
2.7.4