[U-Boot] [PATCH v5 06/25] riscv: ax25: Hide the ax25-specific Kconfig option

[Bin Meng]

There is no need to expose RISCV_NDS to the Kconfig menu as it is
an ax25-specific option. Introduce a dedicated Kconfig option for
the cache ops of ax25 platform and use that to guard the cache ops.

Signed-off-by: Bin Meng <bmeng.cn at gmail.com>

---

Changes in v5:
- Introduced another Kconfig option for the cache ops on AX25 CPU,
  so that it remains selectable in Kconfig menu, but only visible
  to AX25 platform.

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/riscv/cpu/ax25/Kconfig        | 17 ++++++++++++-----
 arch/riscv/cpu/ax25/cache.c        | 12 ++++++------
 board/AndesTech/ax25-ae350/Kconfig |  4 ++++
 3 files changed, 22 insertions(+), 11 deletions(-)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6c7022f..e9dbca2 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -1,7 +1,14 @@
 config RISCV_NDS
-	bool "AndeStar V5 ISA support"
-	default n
+	bool
 	help
-		Say Y here if you plan to run U-Boot on AndeStar v5
-		platforms and use some specific features which are
-		provided by Andes Technology AndeStar V5 Families.
+	  Run U-Boot on AndeStar V5 platforms and use some specific features
+	  which are provided by Andes Technology AndeStar V5 families.
+
+if RISCV_NDS
+
+config RISCV_NDS_CACHE
+	bool "AndeStar V5 families specific cache support"
+	help
+	  Provide Andes Technology AndeStar V5 families specific cache support.
+
+endif
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 6600ac2..8d6ae17 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -9,7 +9,7 @@
 void icache_enable(void)
 {
 #ifndef CONFIG_SYS_ICACHE_OFF
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
 	asm volatile (
 		"csrr t1, mcache_ctl\n\t"
 		"ori t0, t1, 0x1\n\t"
@@ -22,7 +22,7 @@ void icache_enable(void)
 void icache_disable(void)
 {
 #ifndef CONFIG_SYS_ICACHE_OFF
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
 	asm volatile (
 		"fence.i\n\t"
 		"csrr t1, mcache_ctl\n\t"
@@ -36,7 +36,7 @@ void icache_disable(void)
 void dcache_enable(void)
 {
 #ifndef CONFIG_SYS_DCACHE_OFF
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
 	asm volatile (
 		"csrr t1, mcache_ctl\n\t"
 		"ori t0, t1, 0x2\n\t"
@@ -49,7 +49,7 @@ void dcache_enable(void)
 void dcache_disable(void)
 {
 #ifndef CONFIG_SYS_DCACHE_OFF
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
 	asm volatile (
 		"fence\n\t"
 		"csrr t1, mcache_ctl\n\t"
@@ -64,7 +64,7 @@ int icache_status(void)
 {
 	int ret = 0;
 
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
 	asm volatile (
 		"csrr t1, mcache_ctl\n\t"
 		"andi	%0, t1, 0x01\n\t"
@@ -81,7 +81,7 @@ int dcache_status(void)
 {
 	int ret = 0;
 
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
 	asm volatile (
 		"csrr t1, mcache_ctl\n\t"
 		"andi	%0, t1, 0x02\n\t"
diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
index bb69ea3..44cb302 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -21,4 +21,8 @@ config ENV_SIZE
 config ENV_OFFSET
 	default 0x140000 if ENV_IS_IN_SPI_FLASH
 
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select RISCV_NDS
+
 endif
-- 
2.7.4