[U-Boot] Uboot send pull request

[uboot at andestech.com]

Hi Tom,

Please pull some riscv update:
1. Add DM drivers to support RISC-V CPU and timer, plus some bug fixes.
2. Support SiFive UART
3. Rename ax25-ae350 defconfig

https://travis-ci.org/rickchen36/u-boot-riscv/builds/469364551

Thanks

Rick


The following changes since commit 1f2e948d6d53f77a2ddb2dde3531b0d5bc2815ad:

  Prepare v2019.01-rc2 (2018-12-17 20:25:24 -0500)

are available in the Git repository at:

  git://git.denx.de/u-boot-riscv.git

for you to fetch changes up to 368ff57805b03bebf99e97e703ce07aec721bc71:

  doc: README.ae350: Sync for ax25-ae350 rename (2018-12-18 13:26:02 +0800)

----------------------------------------------------------------
Anup Patel (4):
      riscv: Introduce a Kconfig option for machine mode
      riscv: Implement riscv_get_time() API using rdtime instruction
      drivers: serial: Add SiFive UART driver
      riscv: qemu: Imply SIFIVE_SERIAL for emulation

Bin Meng (22):
      dm: cpu: Add timebase frequency to the platdata
      riscv: qemu: Create a simple-bus driver for the soc node
      cpu: Add a RISC-V CPU driver
      timer: Add generic driver for RISC-V privileged architecture defined timer
      riscv: ax25: Hide the ax25-specific Kconfig option
      riscv: Add a SYSCON driver for SiFive's Core Local Interruptor
      riscv: qemu: Add platform-specific Kconfig options
      riscv: Enlarge the default SYS_MALLOC_F_LEN
      riscv: Probe cpus during boot
      riscv: Remove non-DM version of print_cpuinfo()
      riscv: Add CSR numbers
      riscv: Add exception codes for xcause register
      riscv: Update supports_extension() to use desc from cpu driver
      riscv: Add indirect stringification to csr_xxx ops
      riscv: Do some basic architecture level cpu initialization
      riscv: Move trap handler codes to mtrap.S
      riscv: Fix context restore before returning from trap handler
      riscv: Return to previous privilege level after trap handling
      riscv: Adjust the _exit_trap() position to come before handle_trap()
      riscv: Save boot hart id to the global data
      riscv: bootm: Change to use boot_hart from global data
      riscv: Remove ae350.dts

Lukas Auer (1):
      riscv: add Kconfig entries for the code model

Rick Chen (2):
      riscv: configs: Rename ax25-ae350 defconfig
      doc: README.ae350: Sync for ax25-ae350 rename

 arch/riscv/Kconfig                                        |  60 +++++++++++++++++++++--
 arch/riscv/Makefile                                       |   9 +++-
 arch/riscv/cpu/Makefile                                   |   2 +-
 arch/riscv/cpu/ax25/Kconfig                               |  17 +++++--
 arch/riscv/cpu/ax25/cache.c                               |  12 ++---
 arch/riscv/cpu/cpu.c                                      |  98 ++++++++++++++++++++++++++------------
 arch/riscv/cpu/mtrap.S                                    | 103 ++++++++++++++++++++++++++++++++++++++++
 arch/riscv/cpu/qemu/Kconfig                               |  12 +++++
 arch/riscv/cpu/qemu/cpu.c                                 |  14 ++++++
 arch/riscv/cpu/start.S                                    |  93 ++----------------------------------
 arch/riscv/dts/ae350.dts                                  | 229 ----------------------------------------------------------------------------------------
 arch/riscv/include/asm/csr.h                              |  16 ++++---
 arch/riscv/include/asm/encoding.h                         | 236 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/riscv/include/asm/global_data.h                      |   4 ++
 arch/riscv/include/asm/syscon.h                           |  19 ++++++++
 arch/riscv/lib/Makefile                                   |   2 +
 arch/riscv/lib/asm-offsets.c                              |  19 ++++++++
 arch/riscv/lib/bootm.c                                    |   2 +-
 arch/riscv/lib/interrupts.c                               |  62 ++++++++++++------------
 arch/riscv/lib/rdtime.c                                   |  38 +++++++++++++++
 arch/riscv/lib/sifive_clint.c                             |  84 +++++++++++++++++++++++++++++++++
 board/AndesTech/ax25-ae350/Kconfig                        |   4 ++
 board/AndesTech/ax25-ae350/MAINTAINERS                    |   5 +-
 board/emulation/qemu-riscv/Kconfig                        |   2 +
 configs/{a25-ae350_32_defconfig => ae350_rv32_defconfig}  |   0
 configs/{ax25-ae350_64_defconfig => ae350_rv64_defconfig} |   0
 doc/README.ae350                                          |   2 +-
 drivers/cpu/Kconfig                                       |   6 +++
 drivers/cpu/Makefile                                      |   1 +
 drivers/cpu/riscv_cpu.c                                   | 116 +++++++++++++++++++++++++++++++++++++++++++++
 drivers/serial/Kconfig                                    |  13 +++++
 drivers/serial/Makefile                                   |   1 +
 drivers/serial/serial_sifive.c                            | 215 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/timer/Kconfig                                     |   7 +++
 drivers/timer/Makefile                                    |   1 +
 drivers/timer/riscv_timer.c                               |  56 ++++++++++++++++++++++
 include/cpu.h                                             |   3 ++
 37 files changed, 1154 insertions(+), 409 deletions(-)
 create mode 100644 arch/riscv/cpu/mtrap.S
 create mode 100644 arch/riscv/cpu/qemu/Kconfig
 delete mode 100644 arch/riscv/dts/ae350.dts
 create mode 100644 arch/riscv/include/asm/syscon.h
 create mode 100644 arch/riscv/lib/asm-offsets.c
 create mode 100644 arch/riscv/lib/rdtime.c
 create mode 100644 arch/riscv/lib/sifive_clint.c
 rename configs/{a25-ae350_32_defconfig => ae350_rv32_defconfig} (100%)
 rename configs/{ax25-ae350_64_defconfig => ae350_rv64_defconfig} (100%)
 create mode 100644 drivers/cpu/riscv_cpu.c
 create mode 100644 drivers/serial/serial_sifive.c
 create mode 100644 drivers/timer/riscv_timer.c