[U-Boot] [PATCH v2 2/4] mips: mscc: Add generic GPIO control utility function

[Lars Povlsen]

The GPIO control function can be used for controlling alternate
functions associated with a GPIO.

Signed-off-by: Lars Povlsen <lars.povlsen at microchip.com>
---
 arch/mips/mach-mscc/Makefile                  |  2 +-
 arch/mips/mach-mscc/gpio.c                    | 33 +++++++++++++++++++
 arch/mips/mach-mscc/include/mach/common.h     |  2 ++
 .../include/mach/luton/luton_devcpu_gcb.h     |  2 ++
 .../include/mach/ocelot/ocelot_devcpu_gcb.h   |  2 ++
 5 files changed, 40 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/mach-mscc/gpio.c

diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
index 300c88b5cd..44538b7118 100644
--- a/arch/mips/mach-mscc/Makefile
+++ b/arch/mips/mach-mscc/Makefile
@@ -2,5 +2,5 @@
 
 CFLAGS_cpu.o += -finline-limit=64000
 
-obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
+obj-y += cpu.o dram.o reset.o phy.o gpio.o lowlevel_init.o
 obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o
diff --git a/arch/mips/mach-mscc/gpio.c b/arch/mips/mach-mscc/gpio.c
new file mode 100644
index 0000000000..5e3a53372d
--- /dev/null
+++ b/arch/mips/mach-mscc/gpio.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+void mscc_gpio_set_alternate(int gpio, int mode)
+{
+	u32 mask = BIT(gpio);
+	u32 val0, val1;
+
+	val0 = readl(BASE_DEVCPU_GCB + GPIO_ALT(0));
+	val1 = readl(BASE_DEVCPU_GCB + GPIO_ALT(1));
+
+	if (mode == 1) {
+		val0 |= mask;
+		val1 &= ~mask;
+	} else if (mode == 2) {
+		val0 &= ~mask;
+		val1 |= mask;
+	} else if (mode == 3) {
+		val0 |= mask;
+		val1 |= mask;
+	} else {
+		val0 &= ~mask;
+		val1 &= ~mask;
+	}
+
+	writel(val0, BASE_DEVCPU_GCB + GPIO_ALT(0));
+	writel(val1, BASE_DEVCPU_GCB + GPIO_ALT(1));
+}
diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h
index 92a055561e..d18ae78bfd 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -45,4 +45,6 @@ int mscc_phy_wr(u32 miim_controller,
 		u8 addr,
 		u16 value);
 
+void mscc_gpio_set_alternate(int gpio, int mode);
+
 #endif				/* __ASM_MACH_COMMON_H */
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
index 8c0b612325..a06cf819b0 100644
--- a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
+++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
@@ -11,4 +11,6 @@
 #define PERF_SOFT_RST_SOFT_SWC_RST                        BIT(1)
 #define PERF_SOFT_RST_SOFT_CHIP_RST                       BIT(0)
 
+#define GPIO_ALT(x)				(0x88 + 4 * (x))
+
 #endif
diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
index f8aa97ba26..d3a76412e2 100644
--- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
+++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
@@ -18,4 +18,6 @@
 
 #define PERF_GPIO_OE                                      0x44
 
+#define GPIO_ALT(x)				(0x54 + 4 * (x))
+
 #endif
-- 
2.19.2