[U-Boot] [RFC PATCH] ARM: mvebu: add support for Allied Telesis x530
Stefan Roese
sr at denx.de
Fri Dec 21 07:57:18 UTC 2018
On 20.12.18 04:13, Chris Packham wrote:
> From: Chris Packham <chris.packham at alliedtelesis.co.nz>
>
> This is a range of stackable network switches. The SoC is Armada-385 and
> there are a number of variants with differing network port
> configurations. The DP variants are intended for a harsher operating
> environment so they use a different i2c mux and fit industrial-temp
> parts.
>
> Signed-off-by: Chris Packham <judge.packham at gmail.com>
> ---
> This needs http://patchwork.ozlabs.org/patch/1010285/
>
> I imagine that the dts names may want some extra qualifiers. The boards
> aren't in upstream Linux (the source for our fork is published for GPL
> compliance) so there is some flexibility to change the name.
>
> arch/arm/dts/Makefile | 4 +-
> arch/arm/dts/x530.dts | 48 +++++
> arch/arm/dts/x530.dtsi | 269 ++++++++++++++++++++++++++
> arch/arm/dts/x530DP.dts | 50 +++++
> arch/arm/dts/x530DP.dtsi | 149 ++++++++++++++
Yes, please change the dts/dtsi file names to be a bit more specific
about the platform / SoC. Perhaps something like:
armada-385-x530*
> arch/arm/mach-mvebu/Kconfig | 7 +
> board/alliedtelesis/common/gpio_hog.c | 36 ++++
> board/alliedtelesis/common/gpio_hog.h | 13 ++
> board/alliedtelesis/x530/MAINTAINERS | 12 ++
> board/alliedtelesis/x530/Makefile | 9 +
> board/alliedtelesis/x530/kwbimage.cfg | 12 ++
> board/alliedtelesis/x530/x530.c | 161 +++++++++++++++
> configs/x530_defconfig | 71 +++++++
> include/configs/x530.h | 134 +++++++++++++
> 14 files changed, 974 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/x530.dts
> create mode 100644 arch/arm/dts/x530.dtsi
> create mode 100644 arch/arm/dts/x530DP.dts
> create mode 100644 arch/arm/dts/x530DP.dtsi
> create mode 100644 board/alliedtelesis/common/gpio_hog.c
> create mode 100644 board/alliedtelesis/common/gpio_hog.h
> create mode 100644 board/alliedtelesis/x530/MAINTAINERS
> create mode 100644 board/alliedtelesis/x530/Makefile
> create mode 100644 board/alliedtelesis/x530/kwbimage.cfg
> create mode 100644 board/alliedtelesis/x530/x530.c
> create mode 100644 configs/x530_defconfig
> create mode 100644 include/configs/x530.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index dc6f6b233a6a..72d78d011c14 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -109,7 +109,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
> armada-xp-maxbcm.dtb \
> armada-xp-synology-ds414.dtb \
> armada-xp-theadorable.dtb \
> - armada-38x-controlcenterdc.dtb
> + armada-38x-controlcenterdc.dtb \
> + x530.dtb \
> + x530DP.dtb
>
> dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
> uniphier-ld11-global.dtb \
> diff --git a/arch/arm/dts/x530.dts b/arch/arm/dts/x530.dts
> new file mode 100644
> index 000000000000..22f1c4268b7d
> --- /dev/null
> +++ b/arch/arm/dts/x530.dts
> @@ -0,0 +1,48 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/dts-v1/;
> +#include "x530.dtsi"
> +
> +/ {
> + model = "Allied Telesis x530";
> + compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
> +
> + nand-protect {
> + compatible = "atl,nand-protect";
> + protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
> + };
> +
> + usb-enable {
> + compatible = "atl,usb-enable";
> + enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
> + };
> +
> + boot-board {
> + compatible = "atl,boot-board";
> + present-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
> + override-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
> + };
> +
> + phy-reset {
> + compatible = "atl,phy-reset";
> + reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
> + <&gpio1 21 GPIO_ACTIVE_HIGH>;
> + };
> +
> + led-enable {
> + compatible = "atl,led-enable";
> + enable-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
> + };
> +
> + led_7seg {
> + compatible = "atl,of-led-7seg";
> + segment-gpios = <
> + &led_7seg_gpio 0 0
> + &led_7seg_gpio 1 0
> + &led_7seg_gpio 2 0
> + &led_7seg_gpio 3 0
> + &led_7seg_gpio 4 0
> + &led_7seg_gpio 5 0
> + &led_7seg_gpio 6 0
> + &led_7seg_gpio 7 0>;
> + };
> +};
> diff --git a/arch/arm/dts/x530.dtsi b/arch/arm/dts/x530.dtsi
> new file mode 100644
> index 000000000000..664fc6a8fe31
> --- /dev/null
> +++ b/arch/arm/dts/x530.dtsi
> @@ -0,0 +1,269 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include "armada-385.dtsi"
> +
> +/ {
> + model = "Allied Telesis x530";
> + compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + bootargs = "console=ttyS0,115200 earlyprintk";
> + };
> +
> + aliases {
> + spi1 = &spi1;
> + i2c0 = &i2c0;
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
> + };
> +
> + soc {
> + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
> + MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000
> + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
> +
> + pcie-mem-aperture = <0xa0000000 0x40000000>;
> + };
> +
> + eco-button-interrupt {
> + compatible = "atl,eco-button-interrupt";
> + eco-button-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
> + };
> +
> + board-reset {
> + compatible = "atl,phy_reset";
> + /* Physical board layout of reset pin is active-low but for the
> + * current driver we have to set it to active-high here.
> + */
> + phy-reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
> + <&gpio1 21 GPIO_ACTIVE_HIGH>;
> + };
> +
> + phy-int {
> + compatible = "linux,uio-pdrv-genirq";
> + interrupt-parent = <&gpio0>;
> + interrupts = <6 IRQ_TYPE_EDGE_BOTH>;
> + };
> +
> + led-enable {
> + compatible = "atl,led-enable";
> + led-enable-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
> + };
> +
> + led_7seg {
> + compatible = "atl,of-led-7seg";
> + segment-gpios = <
> + &led_7seg_gpio 0 0
> + &led_7seg_gpio 1 0
> + &led_7seg_gpio 2 0
> + &led_7seg_gpio 3 0
> + &led_7seg_gpio 4 0
> + &led_7seg_gpio 5 0
> + &led_7seg_gpio 6 0
> + &led_7seg_gpio 7 0>;
> + };
> +
> + poe {
> + compatible = "atl,periph-poe";
> + poe-reset-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <20 IRQ_TYPE_EDGE_BOTH>;
> + };
> +};
> +
> +&pciec {
> + status = "okay";
> +};
> +
> +&pcie1 {
> + status = "okay";
> +};
> +
> +&devbus_cs1 {
> + compatible = "marvell,mvebu-devbus";
> + status = "okay";
> +
> + devbus,bus-width = <8>;
> + devbus,turn-off-ps = <60000>;
> + devbus,badr-skew-ps = <0>;
> + devbus,acc-first-ps = <124000>;
> + devbus,acc-next-ps = <248000>;
> + devbus,rd-setup-ps = <0>;
> + devbus,rd-hold-ps = <0>;
> +
> + /* Write parameters */
> + devbus,sync-enable = <0>;
> + devbus,wr-high-ps = <60000>;
> + devbus,wr-low-ps = <60000>;
> + devbus,ale-wr-ps = <60000>;
> +
> + nvs at 0 {
> + status = "okay";
> +
> + compatible = "mtd-ram";
> + reg = <0 0x00080000>;
> + bank-width = <1>;
> + label = "nvs";
> + };
> +};
> +
> +&gpio0 {
> + poe-disable {
> + gpio-hog;
> + gpios = <16 GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "poe-disable";
> + };
> +};
> +
> +&gpio1 {
> + poe-mezz-reset {
> + gpio-hog;
> + gpios = <15 GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "poe-mezz-reset";
> + };
> +};
> +
> +&i2c0 {
> + clock-frequency = <100000>;
> + status = "okay";
> +
> + mux at 71 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "nxp,pca9544";
> + reg = <0x71>;
> + i2c-mux-idle-disconnect;
> +
> + i2c at 0 { /* POE devices MUX */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + };
> +
> + i2c at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + rng at 3b {
> + compatible = "maxim,ds2476";
> + reg = <0x3b>;
> + };
> +
> + hwmon at 2e {
> + compatible = "adi,adt7476";
> + reg = <0x2e>;
> + };
> +
> + hwmon at 2d {
> + compatible = "adi,adt7476";
> + reg = <0x2d>;
> + };
> +
> + };
> +
> + i2c at 2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> +
> + rtc at 68 {
> + compatible = "dallas,ds1340";
> + reg = <0x68>;
> + };
> + };
> +
> + i2c at 3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> +
> + led_7seg_gpio: gpio at 20 {
> + compatible = "nxp,pca9554";
> + gpio-controller;
> + #gpio-cells = <2>;
> + reg = <0x20>;
> + };
> +
> + sfpgpio: gpio at 27 { /* I2C to GPIO */
> + compatible = "nxp,pca9555";
> + gpio-controller;
> + #gpio-cells = <2>;
> + reg = <0x27>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + sfpmux: mux at 77 { /* SFP I2C MUX */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "nxp,pca9544";
> + reg = <0x77>;
> + i2c-mux-idle-disconnect;
> + };
> + };
> + };
> +};
> +
> +&spi1 {
> + status = "okay";
> + u-boot,dm-pre-reloc;
I know that these boards are not supported in Linux (yet), but it could
make sense to move these U-Boot specific DT properties into the
*u-boot.dts file.
> +
> + spi-flash at 0 {
> + u-boot,dm-pre-reloc;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "jedec,spi-nor";
> + reg = <0>; /* Chip select 0 */
> + spi-max-frequency = <50000000>;
> + m25p,fast-read;
> +
> + partition at u-boot {
> + reg = <0x00000000 0x00100000>;
> + label = "u-boot";
> + };
> + partition at u-boot-env {
> + reg = <0x00100000 0x00040000>;
> + label = "u-boot-env";
> + };
> + partition at unused {
> + reg = <0x00140000 0x00e80000>;
> + label = "unused";
> + };
> + partition at idprom {
> + reg = <0x00fc0000 0x00040000>;
> + label = "idprom";
> + };
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> + status = "okay";
> + u-boot,dm-pre-reloc;
> +};
> +
> +&usb0 {
> + status = "okay";
> +};
> +
> +&refclk {
> + clock-frequency = <25000000>;
> +};
> +
> +&nand_controller { /* 256 MB */
> + status = "okay";
> + num-cs = <1>;
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> + marvell,nand-enable-arbiter;
> + nand-on-flash-bbt;
> +};
> diff --git a/arch/arm/dts/x530DP.dts b/arch/arm/dts/x530DP.dts
> new file mode 100644
> index 000000000000..86cbdde4bf39
> --- /dev/null
> +++ b/arch/arm/dts/x530DP.dts
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/dts-v1/;
> +
> +#include "x530.dtsi"
> +#include "x530DP.dtsi"
> +
> +/ {
> + model = "Allied Telesis x530";
> + compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
> +
> + nand-protect {
> + compatible = "atl,nand-protect";
> + protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
> + };
> +
> + usb-enable {
> + compatible = "atl,usb-enable";
> + enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
> + };
> +
> + boot-board {
> + compatible = "atl,boot-board";
> + present-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
> + override-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
> + };
> +
> + phy-reset {
> + compatible = "atl,phy-reset";
> + reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
> + <&gpio1 21 GPIO_ACTIVE_HIGH>;
> + };
> +
> + led-enable {
> + compatible = "atl,led-enable";
> + enable-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
> + };
> +
> + led_7seg {
> + compatible = "atl,of-led-7seg";
> + segment-gpios = <
> + &led_7seg_gpio 0 0
> + &led_7seg_gpio 1 0
> + &led_7seg_gpio 2 0
> + &led_7seg_gpio 3 0
> + &led_7seg_gpio 4 0
> + &led_7seg_gpio 5 0
> + &led_7seg_gpio 6 0
> + &led_7seg_gpio 7 0>;
> + };
> +};
> diff --git a/arch/arm/dts/x530DP.dtsi b/arch/arm/dts/x530DP.dtsi
> new file mode 100644
> index 000000000000..977eb4ee54fe
> --- /dev/null
> +++ b/arch/arm/dts/x530DP.dtsi
> @@ -0,0 +1,149 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +&i2c0 {
> + mux at 71 {
> + compatible = "nxp,pca9548";
> +
> + i2c at 1 {
> + hwmon at 2c {
> + compatible = "ti,lm87";
> + reg = <0x2c>;
> + };
> +
> + hwmon at 2d {
> + compatible = "ti,lm87";
> + reg = <0x2d>;
> + };
> +
> + hwmon at 2e {
> + pwm-polarity = <1>;
> + };
> + };
> +
> + psu_a_adapter: i2c at 4 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <4>;
> + };
> +
> + psu_b_adapter: i2c at 5 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <5>;
> + };
> +
> + i2c at 6 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <6>;
> +
> + misc_gpio: gpio at 26 {
> + compatible = "nxp,pca9555";
> + gpio-controller;
> + #gpio-cells = <2>;
> + reg = <0x26>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
> + status = "okay";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + psu_bank2 {
> + gpio-hog;
> + gpios = <0 GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "psu-bank2";
> + };
> + };
> + };
> + };
> +};
> +
> +/ {
> + psu_slot_a {
> + compatible = "atl,dts-overlay-gpio-psu-slot";
> + slot-name = "PSU Bay A";
> + board-index = <1>;
> + present-gpio = <&misc_gpio 1 GPIO_ACTIVE_LOW>;
> + output-ok-gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
> + interrupt-parent = <&misc_gpio>;
> + interrupts = <1 IRQ_TYPE_EDGE_BOTH>;
> + overlay = <&psu_a_overlay>;
> + };
> +
> + psu_slot_b {
> + compatible = "atl,dts-overlay-gpio-psu-slot";
> + slot-name = "PSU Bay B";
> + board-index = <2>;
> + present-gpio = <&misc_gpio 2 GPIO_ACTIVE_LOW>;
> + output-ok-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
> + interrupt-parent = <&misc_gpio>;
> + interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
> + overlay = <&psu_b_overlay>;
> + };
> +
> + fan_slot_a {
> + compatible = "atl,fan05-slot";
> + slot-name = "Fan Bay A";
> + board-index = <3>;
> + present-gpio = <&misc_gpio 3 GPIO_ACTIVE_LOW>;
> + fault-gpio = <&misc_gpio 11 GPIO_ACTIVE_LOW>;
> + interrupt-parent = <&misc_gpio>;
> + interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
> + overlay = <&fan_a_overlay>;
> + };
> +};
> +
> +/ {
> + psu_a_overlay: psu_a {
> + fragment at 0 {
> + target = <&psu_a_adapter>;
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + psu at 51 {
> + compatible = "atl,atl-pwr-gen2";
> + reg = <0x51>;
> + board-index = <1>;
> + };
> + };
> + };
> + };
> +};
> +
> +/ {
> + psu_b_overlay: psu_b {
> + fragment at 0 {
> + target = <&psu_b_adapter>;
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + psu at 51 {
> + compatible = "atl,atl-pwr-gen2";
> + reg = <0x51>;
> + board-index = <2>;
> + };
> + };
> + };
> + };
> +};
> +
> +/ {
> + fan_a_overlay:fan_a {
> + fragment at 1 {
> + target-path = "/";
> + __overlay__ {
> + fan at 1 {
> + compatible = "atl,fan05";
> + board-index = <3>;
> + module-id-gpios =
> + <&misc_gpio 4 GPIO_ACTIVE_HIGH>,
> + <&misc_gpio 5 GPIO_ACTIVE_HIGH>,
> + <&misc_gpio 6 GPIO_ACTIVE_HIGH>;
> + };
> + };
> + };
> + };
> +};
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index d1f71338ac2a..7dda04e0e34e 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -132,6 +132,10 @@ config TARGET_CONTROLCENTERDC
> bool "Support CONTROLCENTERDC"
> select 88F6820
>
> +config TARGET_X530
> + bool "Support Allied Telesis x530"
> + select 88F6820
> +
> endchoice
>
> config SYS_BOARD
> @@ -149,6 +153,7 @@ config SYS_BOARD
> default "maxbcm" if TARGET_MAXBCM
> default "theadorable" if TARGET_THEADORABLE
> default "a38x" if TARGET_CONTROLCENTERDC
> + default "x530" if TARGET_X530
>
> config SYS_CONFIG_NAME
> default "clearfog" if TARGET_CLEARFOG
> @@ -165,6 +170,7 @@ config SYS_CONFIG_NAME
> default "turris_omnia" if TARGET_TURRIS_OMNIA
> default "turris_mox" if TARGET_TURRIS_MOX
> default "controlcenterdc" if TARGET_CONTROLCENTERDC
> + default "x530" if TARGET_X530
>
> config SYS_VENDOR
> default "Marvell" if TARGET_DB_MV784MP_GP
> @@ -179,6 +185,7 @@ config SYS_VENDOR
> default "CZ.NIC" if TARGET_TURRIS_OMNIA
> default "CZ.NIC" if TARGET_TURRIS_MOX
> default "gdsys" if TARGET_CONTROLCENTERDC
> + default "alliedtelesis" if TARGET_X530
>
> config SYS_SOC
> default "mvebu"
> diff --git a/board/alliedtelesis/common/gpio_hog.c b/board/alliedtelesis/common/gpio_hog.c
> new file mode 100644
> index 000000000000..1f87b3ac1b72
> --- /dev/null
> +++ b/board/alliedtelesis/common/gpio_hog.c
> @@ -0,0 +1,36 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018 Allied Telesis Labs
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <asm/gpio.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int gpio_hog_list(struct gpio_desc *gpiod, int max_count,
> + const char *node_name, const char *gpio_name, int value)
> +{
> + int node;
> + int count;
> + int i;
> +
> + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, node_name);
> + if (node < 0)
> + return -ENODEV;
> +
> + if (!dm_gpio_is_valid(gpiod)) {
> + count =
> + gpio_request_list_by_name_nodev(offset_to_ofnode(node),
> + gpio_name, gpiod, max_count,
> + GPIOD_IS_OUT);
> + if (count < 0)
> + return count;
> +
> + for (i = 0; i < count; i++)
> + dm_gpio_set_value(&gpiod[i], value);
> + }
> +
> + return 0;
> +}
> diff --git a/board/alliedtelesis/common/gpio_hog.h b/board/alliedtelesis/common/gpio_hog.h
> new file mode 100644
> index 000000000000..edb744313186
> --- /dev/null
> +++ b/board/alliedtelesis/common/gpio_hog.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2017 Allied Telesis Labs
> + */
> +
> +int gpio_hog_list(struct gpio_desc *gpiod, int max_count, const char *node_name,
> + const char *gpio_name, int value);
> +
> +static inline int gpio_hog(struct gpio_desc *gpiod, const char *node_name,
> + const char *gpio_name, int value)
> +{
> + return gpio_hog_list(gpiod, 1, node_name, gpio_name, value);
> +}
> diff --git a/board/alliedtelesis/x530/MAINTAINERS b/board/alliedtelesis/x530/MAINTAINERS
> new file mode 100644
> index 000000000000..b6cca33c083a
> --- /dev/null
> +++ b/board/alliedtelesis/x530/MAINTAINERS
> @@ -0,0 +1,12 @@
> +x530 BOARD
> +M: Chris Packham <chris.packham at alliedtelesis.co.nz>
> +S: Maintained
> +F: board/alliedtelesis/x530/
> +F: board/alliedtelesis/common/gpio_hog.c
> +F: board/alliedtelesis/common/gpio_hog.h
> +F: arch/arm/dts/x530.dts
> +F: arch/arm/dts/x530.dtsi
> +F: arch/arm/dts/x530DP.dts
> +F: arch/arm/dts/x530DP.dtsi
> +F: include/configs/x530.h
> +F: configs/x530_defconfig
> diff --git a/board/alliedtelesis/x530/Makefile b/board/alliedtelesis/x530/Makefile
> new file mode 100644
> index 000000000000..97de1d463fe8
> --- /dev/null
> +++ b/board/alliedtelesis/x530/Makefile
> @@ -0,0 +1,9 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2017 Allied Telesis Labs
> +#
> +
> +obj-y := $(BOARD).o
> +ifndef CONFIG_SPL_BUILD
> +obj-y += ../common/gpio_hog.o
> +endif
> diff --git a/board/alliedtelesis/x530/kwbimage.cfg b/board/alliedtelesis/x530/kwbimage.cfg
> new file mode 100644
> index 000000000000..f58d388825e7
> --- /dev/null
> +++ b/board/alliedtelesis/x530/kwbimage.cfg
> @@ -0,0 +1,12 @@
> +#
> +# Copyright (C) 2017 Allied Telesis Labs
> +#
> +
> +# Armada XP uses version 1 image format
> +VERSION 1
> +
> +# Boot Media configurations
> +BOOT_FROM spi
> +
> +# Binary Header (bin_hdr) with DDR3 training code
> +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
> diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c
> new file mode 100644
> index 000000000000..b34ae5134547
> --- /dev/null
> +++ b/board/alliedtelesis/x530/x530.c
> @@ -0,0 +1,161 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2017 Allied Telesis Labs
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +#include <dm.h>
> +#include <i2c.h>
> +#include <asm/gpio.h>
> +#include <linux/mbus.h>
> +#include <linux/io.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/soc.h>
> +#include "../common/gpio_hog.h"
> +
> +#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
> +#include <../serdes/a38x/high_speed_env_spec.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))
> +
> +#define CONFIG_NVS_LOCATION 0xf4800000
> +#define CONFIG_NVS_SIZE (512 << 10)
> +
> +static struct serdes_map board_serdes_map[] = {
> + {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
> + {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
> + {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
> + {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
> + {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
> + {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
> +};
> +
> +int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
> +{
> + *serdes_map_array = board_serdes_map;
> + *count = ARRAY_SIZE(board_serdes_map);
> + return 0;
> +}
> +
> +/*
> + * Define the DDR layout / topology here in the board file. This will
> + * be used by the DDR3 init code in the SPL U-Boot version to configure
> + * the DDR3 controller.
> + */
> +static struct mv_ddr_topology_map board_topology_map = {
> + DEBUG_LEVEL_ERROR,
> + 0x1, /* active interfaces */
> + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
> + { { { {0x1, 0, 0, 0},
> + {0x1, 0, 0, 0},
> + {0x1, 0, 0, 0},
> + {0x1, 0, 0, 0},
> + {0x1, 0, 0, 0} },
> + SPEED_BIN_DDR_1866M, /* speed_bin */
> + MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
> + MV_DDR_DIE_CAP_4GBIT, /* die capacity */
> + MV_DDR_FREQ_933, /* frequency */
> + 0, 0, /* cas_l cas_wl */
> + MV_DDR_TEMP_LOW, /* temperature */
> + MV_DDR_TIM_2T} }, /* timing */
> + BUS_MASK_32BIT_ECC, /* subphys mask */
> + MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
> + { {0} }, /* raw spd data */
> + {0} /* timing parameters */
> +};
> +
> +struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
> +{
> + /* Return the board topology as defined in the board code */
> + return &board_topology_map;
> +}
> +
> +int board_early_init_f(void)
> +{
> + /* Configure MPP */
> + writel(0x00001111, MVEBU_MPP_BASE + 0x00);
> + writel(0x00000000, MVEBU_MPP_BASE + 0x04);
> + writel(0x55000000, MVEBU_MPP_BASE + 0x08);
> + writel(0x55550550, MVEBU_MPP_BASE + 0x0c);
> + writel(0x55555555, MVEBU_MPP_BASE + 0x10);
> + writel(0x00100565, MVEBU_MPP_BASE + 0x14);
> + writel(0x40000000, MVEBU_MPP_BASE + 0x18);
> + writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
> +
> + /* window for NVS */
> + mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
> + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
> +
> + /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
> + writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
> +
> + return 0;
> +}
> +
> +static int led_7seg_init(unsigned int segments)
> +{
> + int node;
> + int ret;
> + int i;
> + struct gpio_desc desc[8];
> +
> + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
> + "atl,of-led-7seg");
> + if (node < 0)
> + return -ENODEV;
> +
> + ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
> + "segment-gpios", desc,
> + ARRAY_SIZE(desc), GPIOD_IS_OUT);
> + if (ret < 0)
> + return ret;
> +
> + for (i = 0; i < ARRAY_SIZE(desc); i++) {
> + ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i)));
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_MISC_INIT_R
> +int misc_init_r(void)
> +{
> + static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {},
> + led_en = {};
> +
> + gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1);
> + gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1);
> + gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0);
> + gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1);
> +
> +#ifdef MTDPARTS_MTDOOPS
> + env_set("mtdoops", MTDPARTS_MTDOOPS);
> +#endif
> +
> + led_7seg_init(0xff);
> +
> + return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_DISPLAY_BOARDINFO
> +int checkboard(void)
> +{
> + puts("Board: " CONFIG_SYS_BOARD "\n");
> +
> + return 0;
> +}
> +#endif
> diff --git a/configs/x530_defconfig b/configs/x530_defconfig
> new file mode 100644
> index 000000000000..a9f1344a18d2
> --- /dev/null
> +++ b/configs/x530_defconfig
> @@ -0,0 +1,71 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MVEBU=y
> +CONFIG_SYS_TEXT_BASE=0x00800000
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_TARGET_X530=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL=y
> +CONFIG_DEBUG_UART_BASE=0xd0012000
> +CONFIG_DEBUG_UART_CLOCK=250000000
> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
> +CONFIG_SPL_SPI_SUPPORT=y
> +CONFIG_DEBUG_UART=y
> +CONFIG_NR_DRAM_BANKS=2
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SILENT_CONSOLE=y
> +CONFIG_SILENT_U_BOOT_ONLY=y
> +CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC=y
> +CONFIG_MISC_INIT_R=y
> +CONFIG_CMD_MEMINFO=y
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_USB=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_TFTPPUT=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_DEFAULT_DEVICE_TREE="x530"
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_SPL_OF_TRANSLATE=y
> +CONFIG_BLK=y
> +CONFIG_DM_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_MVTWSI=y
> +CONFIG_I2C_MUX=y
> +CONFIG_I2C_MUX_PCA954x=y
> +CONFIG_MISC=y
> +# CONFIG_MMC is not set
> +CONFIG_NAND=y
> +CONFIG_NAND_PXA3XX=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_SPI_FLASH_SST=y
> +CONFIG_MTD_UBI=y
> +CONFIG_PCI=y
> +CONFIG_DM_RTC=y
> +CONFIG_RTC_DS1307=y
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_SYS_NS16550=y
> +CONFIG_KIRKWOOD_SPI=y
> +CONFIG_USB=y
> +CONFIG_DM_USB=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_HOST_ETHER=y
> +CONFIG_USB_ETHER_ASIX=y
> +CONFIG_USB_ETHER_ASIX88179=y
> diff --git a/include/configs/x530.h b/include/configs/x530.h
> new file mode 100644
> index 000000000000..a1ef301d35e0
> --- /dev/null
> +++ b/include/configs/x530.h
> @@ -0,0 +1,134 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2018 Allied Telesis Labs
> + */
> +
> +#ifndef _CONFIG_X530_H
> +#define _CONFIG_X530_H
> +
> +/*
> + * High Level Configuration Options (easy to change)
> + */
> +
> +#define CONFIG_DISPLAY_BOARDINFO_LATE
> +
> +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
> +
> +/*
> + * NS16550 Configuration
> + */
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
> +#if !defined(CONFIG_DM_SERIAL)
> +#define CONFIG_SYS_NS16550_REG_SIZE (-4)
> +#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
> +#endif
> +
> +/*
> + * Serial Port configuration
> + * The following definitions let you select what serial you want to use
> + * for your console driver.
> + */
> +
> +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
> +
> +/*
> + * Commands configuration
> + */
> +#define CONFIG_CMD_PCI
> +
> +/* NAND */
> +#define CONFIG_SYS_NAND_ONFI_DETECTION
> +#define CONFIG_SYS_NAND_USE_FLASH_BBT
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +
> +#define BBT_CUSTOM_SCAN
> +#define BBT_CUSTOM_SCAN_PAGE 0
> +#define BBT_CUSTOM_SCAN_POSITION 2048
> +
> +/* SPI NOR flash default params, used by sf commands */
> +#define CONFIG_SF_DEFAULT_BUS 1
> +#define CONFIG_SF_DEFAULT_SPEED 50000000
> +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
> +
> +#define MTDIDS_DEFAULT "nand0=nand"
> +#define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)"
> +#define MTDPARTS_MTDOOPS "errlog"
> +
> +/* Partition support */
> +
> +/* Additional FS support/configuration */
> +
> +/* USB/EHCI configuration */
> +#define CONFIG_EHCI_IS_TDI
> +
> +/* Environment in SPI NOR flash */
> +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
> +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
> +#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
> +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
> +#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
> +#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
> +
> +#define CONFIG_PHY_MARVELL /* there is a marvell phy */
> +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
> +
> +/* PCIe support */
> +#ifndef CONFIG_SPL_BUILD
> +#define CONFIG_PCI_MVEBU
> +#define CONFIG_PCI_SCAN_SHOW
> +#endif
> +
> +/* NAND */
> +#define CONFIG_SYS_NAND_USE_FLASH_BBT
> +#define CONFIG_SYS_NAND_ONFI_DETECTION
> +#define CONFIG_CMD_UBI
> +#define CONFIG_CMD_UBIFS
> +#define CONFIG_LZO
> +#define CONFIG_MTD_DEVICE
> +#define CONFIG_CMD_MTDPARTS
> +
> +#define CONFIG_SYS_MALLOC_LEN (4 << 20)
> +
> +#include <asm/arch/config.h>
> +
> +/*
> + * Other required minimal configurations
> + */
> +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
> +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
> +
> +#define CONFIG_SYS_ALT_MEMTEST
> +
> +/* Keep device tree and initrd in low memory so the kernel can access them */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "fdt_high=0x10000000\0" \
> + "initrd_high=0x10000000\0"
> +
> +#define CONFIG_SYS_LOAD_ADDR 0x1000000
> +#define CONFIG_UBI_PART user
> +#define CONFIG_UBIFS_VOLUME user
> +
> +/* SPL */
> +
> +/* Defines for SPL */
> +#define CONFIG_SPL_SIZE (140 << 10)
> +#define CONFIG_SPL_TEXT_BASE 0x40000030
> +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
> +
> +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
> +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
> +
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SYS_MALLOC_SIMPLE
> +#endif
> +
> +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
> +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
> +
> +/* SPL related SPI defines */
> +#define CONFIG_SPL_SPI_LOAD
> +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
> +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
> +
> +#endif /* _CONFIG_X530_H */
>
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr at denx.de
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