[U-Boot] [PATCH 08/11] tegra: sound: Add an I2S driver

Simon Glass sjg at chromium.org
Thu Dec 27 20:24:43 UTC 2018 

Add a driver which supports transmitting digital sound to an audio codec.
This uses fixed parameters as a device-tree binding is not currently
defined.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

 arch/arm/include/asm/arch-tegra/tegra_i2s.h | 206 ++++++++++++++++++++
 drivers/sound/Makefile                      |   2 +-
 drivers/sound/tegra_i2s.c                   | 124 ++++++++++++
 drivers/sound/tegra_i2s_priv.h              |  29 +++
 4 files changed, 360 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/arch-tegra/tegra_i2s.h
 create mode 100644 drivers/sound/tegra_i2s.c
 create mode 100644 drivers/sound/tegra_i2s_priv.h

diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2s.h b/arch/arm/include/asm/arch-tegra/tegra_i2s.h
new file mode 100644
index 00000000000..9319383f7c1
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/tegra_i2s.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * tegra_i2s.h - Definitions for Tegra124 I2S driver.
+ * Note, some structures (ex, CIF) are different in Tegra114.
+ *
+ * NVIDIA Tegra I2S controller
+ * Modified from dc tegra_regs.h
+ *
+ * Copyright 2018 Google LLC
+ *
+ * Copyright (c) 2011-2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _TEGRA_I2S_H_
+#define _TEGRA_I2S_H_
+
+struct i2s_ctlr {
+	u32 ctrl;		/* I2S_CTRL_0, 0x00 */
+	u32 timing;		/* I2S_TIMING_0, 0x04 */
+	u32 offset;		/* I2S_OFFSET_0, 0x08 */
+	u32 ch_ctrl;		/* I2S_CH_CTRL_0, 0x0C */
+	u32 slot_ctrl;		/* I2S_SLOT_CTRL_0, 0x10 */
+	u32 cif_tx_ctrl;	/* I2S_CIF_TX_CTRL_0, 0x14 */
+	u32 cif_rx_ctrl;	/* I2S_CIF_RX_CTRL_0, 0x18 */
+	u32 flowctl;		/* I2S_FLOWCTL_0, 0x1C */
+	u32 tx_step;		/* I2S_TX_STEP_0, 0x20 */
+	u32 flow_status;	/* I2S_FLOW_STATUS_0, 0x24 */
+	u32 flow_total;		/* I2S_FLOW_TOTAL_0, 0x28 */
+	u32 flow_over;		/* I2S_FLOW_OVER_0, 0x2C */
+	u32 flow_under;		/* I2S_FLOW_UNDER_0, 0x30 */
+	u32 reserved[12];	/* RESERVED, 0x34 - 0x60 */
+	u32 slot_ctrl2;		/* I2S_SLOT_CTRL2_0, 0x64*/
+};
+
+enum {
+	I2S_CTRL_XFER_EN_TX = 1 << 31,
+	I2S_CTRL_XFER_EN_RX = 1 << 30,
+	I2S_CTRL_CG_EN = 1 << 29,
+	I2S_CTRL_SOFT_RESET = 1 << 28,
+	I2S_CTRL_TX_FLOWCTL_EN = 1 << 27,
+
+	I2S_CTRL_OBS_SEL_SHIFT = 24,
+	I2S_CTRL_OBS_SEL_MASK = 7 << I2S_CTRL_OBS_SEL_SHIFT,
+
+	I2S_FRAME_FORMAT_LRCK = 0,
+	I2S_FRAME_FORMAT_FSYNC = 1,
+
+	I2S_CTRL_FRAME_FORMAT_SHIFT = 12,
+	I2S_CTRL_FRAME_FORMAT_MASK = 7 << I2S_CTRL_FRAME_FORMAT_SHIFT,
+	I2S_CTRL_FRAME_FORMAT_LRCK = I2S_FRAME_FORMAT_LRCK <<
+				     I2S_CTRL_FRAME_FORMAT_SHIFT,
+	I2S_CTRL_FRAME_FORMAT_FSYNC = I2S_FRAME_FORMAT_FSYNC <<
+				      I2S_CTRL_FRAME_FORMAT_SHIFT,
+
+	I2S_CTRL_MASTER_ENABLE = 1 << 10,
+
+	I2S_LRCK_LEFT_LOW = 0,
+	I2S_LRCK_RIGHT_LOW = 1,
+
+	I2S_CTRL_LRCK_SHIFT = 9,
+	I2S_CTRL_LRCK_MASK = 1 << I2S_CTRL_LRCK_SHIFT,
+	I2S_CTRL_LRCK_L_LOW = I2S_LRCK_LEFT_LOW  << I2S_CTRL_LRCK_SHIFT,
+	I2S_CTRL_LRCK_R_LOW = I2S_LRCK_RIGHT_LOW << I2S_CTRL_LRCK_SHIFT,
+
+	I2S_CTRL_LPBK_ENABLE = 1 << 8,
+
+	I2S_BIT_CODE_LINEAR = 0,
+	I2S_BIT_CODE_ULAW = 1,
+	I2S_BIT_CODE_ALAW = 2,
+
+	I2S_CTRL_BIT_CODE_SHIFT = 4,
+	I2S_CTRL_BIT_CODE_MASK = 3 << I2S_CTRL_BIT_CODE_SHIFT,
+	I2S_CTRL_BIT_CODE_LINEAR = I2S_BIT_CODE_LINEAR <<
+				   I2S_CTRL_BIT_CODE_SHIFT,
+	I2S_CTRL_BIT_CODE_ULAW = I2S_BIT_CODE_ULAW << I2S_CTRL_BIT_CODE_SHIFT,
+	I2S_CTRL_BIT_CODE_ALAW = I2S_BIT_CODE_ALAW << I2S_CTRL_BIT_CODE_SHIFT,
+
+	I2S_BITS_8 = 1,
+	I2S_BITS_12 = 2,
+	I2S_BITS_16 = 3,
+	I2S_BITS_20 = 4,
+	I2S_BITS_24 = 5,
+	I2S_BITS_28 = 6,
+	I2S_BITS_32 = 7,
+
+	/* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */
+	I2S_CTRL_BIT_SIZE_SHIFT = 0,
+	I2S_CTRL_BIT_SIZE_MASK = 7 << I2S_CTRL_BIT_SIZE_SHIFT,
+	I2S_CTRL_BIT_SIZE_8 = I2S_BITS_8  << I2S_CTRL_BIT_SIZE_SHIFT,
+	I2S_CTRL_BIT_SIZE_12 = I2S_BITS_12 << I2S_CTRL_BIT_SIZE_SHIFT,
+	I2S_CTRL_BIT_SIZE_16 = I2S_BITS_16 << I2S_CTRL_BIT_SIZE_SHIFT,
+	I2S_CTRL_BIT_SIZE_20 = I2S_BITS_20 << I2S_CTRL_BIT_SIZE_SHIFT,
+	I2S_CTRL_BIT_SIZE_24 = I2S_BITS_24 << I2S_CTRL_BIT_SIZE_SHIFT,
+	I2S_CTRL_BIT_SIZE_28 = I2S_BITS_28 << I2S_CTRL_BIT_SIZE_SHIFT,
+	I2S_CTRL_BIT_SIZE_32 = I2S_BITS_32 << I2S_CTRL_BIT_SIZE_SHIFT,
+
+	I2S_TIMING_NON_SYM_ENABLE = 1 << 12,
+	I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT = 0,
+	I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US = 0x7ff,
+	I2S_TIMING_CHANNEL_BIT_COUNT_MASK =
+			I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US <<
+			I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT,
+
+	I2S_OFFSET_RX_DATA_OFFSET_SHIFT = 16,
+	I2S_OFFSET_RX_DATA_OFFSET_MASK_US = 0x7ff,
+	I2S_OFFSET_RX_DATA_OFFSET_MASK = I2S_OFFSET_RX_DATA_OFFSET_MASK_US <<
+					 I2S_OFFSET_RX_DATA_OFFSET_SHIFT,
+	I2S_OFFSET_TX_DATA_OFFSET_SHIFT = 0,
+	I2S_OFFSET_TX_DATA_OFFSET_MASK_US = 0x7ff,
+	I2S_OFFSET_TX_DATA_OFFSET_MASK = I2S_OFFSET_TX_DATA_OFFSET_MASK_US <<
+					 I2S_OFFSET_TX_DATA_OFFSET_SHIFT,
+
+	/* FSYNC width - 1 in bit clocks */
+	I2S_CH_CTRL_FSYNC_WIDTH_SHIFT = 24,
+	I2S_CH_CTRL_FSYNC_WIDTH_MASK_US = 0xff,
+	I2S_CH_CTRL_FSYNC_WIDTH_MASK = I2S_CH_CTRL_FSYNC_WIDTH_MASK_US <<
+				       I2S_CH_CTRL_FSYNC_WIDTH_SHIFT,
+
+	I2S_HIGHZ_NO = 0,
+	I2S_HIGHZ_YES = 1,
+	I2S_HIGHZ_ON_HALF_BIT_CLK = 2,
+
+	I2S_CH_CTRL_HIGHZ_CTRL_SHIFT = 12,
+	I2S_CH_CTRL_HIGHZ_CTRL_MASK = 3 << I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
+	I2S_CH_CTRL_HIGHZ_CTRL_NO = I2S_HIGHZ_NO <<
+				    I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
+	I2S_CH_CTRL_HIGHZ_CTRL_YES = I2S_HIGHZ_YES <<
+				     I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
+	I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK = I2S_HIGHZ_ON_HALF_BIT_CLK <<
+						 I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
+
+	I2S_MSB_FIRST = 0,
+	I2S_LSB_FIRST = 1,
+
+	I2S_CH_CTRL_RX_BIT_ORDER_SHIFT = 10,
+	I2S_CH_CTRL_RX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
+	I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST <<
+					     I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
+	I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST <<
+					     I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
+	I2S_CH_CTRL_TX_BIT_ORDER_SHIFT = 9,
+	I2S_CH_CTRL_TX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
+	I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST <<
+					     I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
+	I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST <<
+					     I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
+
+	I2S_POS_EDGE = 0,
+	I2S_NEG_EDGE = 1,
+
+	I2S_CH_CTRL_EGDE_CTRL_SHIFT = 8,
+	I2S_CH_CTRL_EGDE_CTRL_MASK = 1 << I2S_CH_CTRL_EGDE_CTRL_SHIFT,
+	I2S_CH_CTRL_EGDE_CTRL_POS_EDGE = I2S_POS_EDGE <<
+					 I2S_CH_CTRL_EGDE_CTRL_SHIFT,
+	I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE = I2S_NEG_EDGE <<
+					 I2S_CH_CTRL_EGDE_CTRL_SHIFT,
+
+	/* Sample size is # bits from BIT_SIZE minus this field */
+	I2S_CH_CTRL_RX_MASK_BITS_SHIFT = 4,
+	I2S_CH_CTRL_RX_MASK_BITS_MASK_US = 7,
+	I2S_CH_CTRL_RX_MASK_BITS_MASK = I2S_CH_CTRL_RX_MASK_BITS_MASK_US <<
+					I2S_CH_CTRL_RX_MASK_BITS_SHIFT,
+
+	I2S_CH_CTRL_TX_MASK_BITS_SHIFT = 0,
+	I2S_CH_CTRL_TX_MASK_BITS_MASK_US = 7,
+	I2S_CH_CTRL_TX_MASK_BITS_MASK = I2S_CH_CTRL_TX_MASK_BITS_MASK_US <<
+					I2S_CH_CTRL_TX_MASK_BITS_SHIFT,
+
+	/* Number of slots in frame, minus 1 */
+	I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT = 16,
+	I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US = 7,
+	I2S_SLOT_CTRL_TOTAL_SLOTS_MASK = I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US <<
+					 I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT,
+
+	/* TDM mode slot enable bitmask */
+	I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT = 8,
+	I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK =
+			0xff << I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT,
+
+	I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT = 0,
+	I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK = 0xff <<
+					   I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT,
+
+	I2S_FILTER_LINEAR = 0,
+	I2S_FILTER_QUAD = 1,
+
+	I2S_FLOWCTL_FILTER_SHIFT = 31,
+	I2S_FLOWCTL_FILTER_MASK = 1 << I2S_FLOWCTL_FILTER_SHIFT,
+	I2S_FLOWCTL_FILTER_LINEAR = I2S_FILTER_LINEAR <<
+				    I2S_FLOWCTL_FILTER_SHIFT,
+	I2S_FLOWCTL_FILTER_QUAD = I2S_FILTER_QUAD << I2S_FLOWCTL_FILTER_SHIFT,
+
+	I2S_TX_STEP_SHIFT = 0,
+	I2S_TX_STEP_MASK_US = 0xffff,
+	I2S_TX_STEP_MASK = I2S_TX_STEP_MASK_US << I2S_TX_STEP_SHIFT,
+
+	I2S_FLOW_STATUS_UNDERFLOW = 1 << 31,
+	I2S_FLOW_STATUS_OVERFLOW = 1 << 30,
+	I2S_FLOW_STATUS_MONITOR_INT_EN = 1 << 4,
+	I2S_FLOW_STATUS_COUNTER_CLR = 1 << 3,
+	I2S_FLOW_STATUS_MONITOR_CLR = 1 << 2,
+	I2S_FLOW_STATUS_COUNTER_EN = 1 << 1,
+	I2S_FLOW_STATUS_MONITOR_EN = 1 << 0,
+};
+
+#endif	/* _TEGRA_I2C_H_ */
diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile
index 98d4f13688e..d444c28578a 100644
--- a/drivers/sound/Makefile
+++ b/drivers/sound/Makefile
@@ -10,7 +10,7 @@ obj-$(CONFIG_SOUND)	+= sound-uclass.o
 obj-$(CONFIG_I2S_SAMSUNG)	+= samsung-i2s.o
 obj-$(CONFIG_SOUND_SANDBOX)	+= sandbox.o
 obj-$(CONFIG_I2S_SAMSUNG)	+= samsung_sound.o
-obj-$(CONFIG_I2S_TEGRA)		+= tegra_ahub.o
+obj-$(CONFIG_I2S_TEGRA)		+= tegra_ahub.o tegra_i2s.o
 obj-$(CONFIG_SOUND_WM8994)	+= wm8994.o
 obj-$(CONFIG_SOUND_MAX98088)	+= max98088.o maxim_codec.o
 obj-$(CONFIG_SOUND_MAX98090)	+= max98090.o maxim_codec.o
diff --git a/drivers/sound/tegra_i2s.c b/drivers/sound/tegra_i2s.c
new file mode 100644
index 00000000000..200d005fb6b
--- /dev/null
+++ b/drivers/sound/tegra_i2s.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 Google LLC
+ * Written by Simon Glass <sjg at chromium.org>
+ */
+#define LOG_CATEGORY UCLASS_I2S
+#define LOG_DEBUG
+
+#include <common.h>
+#include <dm.h>
+#include <i2s.h>
+#include <misc.h>
+#include <sound.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/tegra_i2s.h>
+#include "tegra_i2s_priv.h"
+
+int tegra_i2s_set_cif_tx_ctrl(struct udevice *dev, u32 value)
+{
+	struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
+	struct i2s_ctlr *regs = (struct i2s_ctlr *)priv->base_address;
+
+	writel(value, &regs->cif_tx_ctrl);
+
+	return 0;
+}
+
+static void tegra_i2s_transmit_enable(struct i2s_ctlr *regs, int on)
+{
+	clrsetbits_le32(&regs->ctrl, I2S_CTRL_XFER_EN_TX,
+			on ? I2S_CTRL_XFER_EN_TX : 0);
+}
+
+static int i2s_tx_init(struct i2s_uc_priv *pi2s_tx)
+{
+	struct i2s_ctlr *regs = (struct i2s_ctlr *)pi2s_tx->base_address;
+	u32 audio_bits = (pi2s_tx->bitspersample >> 2) - 1;
+	u32 ctrl = readl(&regs->ctrl);
+
+	/* Set format to LRCK / Left Low */
+	ctrl &= ~(I2S_CTRL_FRAME_FORMAT_MASK | I2S_CTRL_LRCK_MASK);
+	ctrl |= I2S_CTRL_FRAME_FORMAT_LRCK;
+	ctrl |= I2S_CTRL_LRCK_L_LOW;
+
+	/* Disable all transmission until we are ready to transfer */
+	ctrl &= ~(I2S_CTRL_XFER_EN_TX | I2S_CTRL_XFER_EN_RX);
+
+	/* Serve as master */
+	ctrl |= I2S_CTRL_MASTER_ENABLE;
+
+	/* Configure audio bits size */
+	ctrl &= ~I2S_CTRL_BIT_SIZE_MASK;
+	ctrl |= audio_bits << I2S_CTRL_BIT_SIZE_SHIFT;
+	writel(ctrl, &regs->ctrl);
+
+	/* Timing in LRCK mode: */
+	writel(pi2s_tx->bitspersample, &regs->timing);
+
+	/* I2S mode has [TX/RX]_DATA_OFFSET both set to 1 */
+	writel(((1 << I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
+		(1 << I2S_OFFSET_TX_DATA_OFFSET_SHIFT)), &regs->offset);
+
+	/* FSYNC_WIDTH = 2 clocks wide, TOTAL_SLOTS = 2 slots per fsync */
+	writel((2 - 1) << I2S_CH_CTRL_FSYNC_WIDTH_SHIFT, &regs->ch_ctrl);
+	writel((2 - 1), &regs->slot_ctrl);
+
+	return 0;
+}
+
+static int tegra_i2s_tx_data(struct udevice *dev, void *data, uint data_size)
+{
+	struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
+	struct i2s_ctlr *regs = (struct i2s_ctlr *)priv->base_address;
+	int ret;
+
+	tegra_i2s_transmit_enable(regs, 1);
+	ret = misc_write(dev_get_parent(dev), 0, data, data_size);
+	tegra_i2s_transmit_enable(regs, 0);
+	if (ret < 0)
+		return ret;
+	else if (ret < data_size)
+		return -EIO;
+
+	return 0;
+}
+
+static int tegra_i2s_probe(struct udevice *dev)
+{
+	struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
+	ulong base;
+
+	base = dev_read_addr(dev);
+	if (base == FDT_ADDR_T_NONE) {
+		debug("%s: Missing i2s base\n", __func__);
+		return -EINVAL;
+	}
+	priv->base_address = base;
+	priv->id = 1;
+	priv->audio_pll_clk = 4800000;
+	priv->samplingrate = 48000;
+	priv->bitspersample = 16;
+	priv->channels = 2;
+	priv->rfs = 256;
+	priv->bfs = 32;
+
+	return i2s_tx_init(priv);
+}
+
+static const struct i2s_ops tegra_i2s_ops = {
+	.tx_data	= tegra_i2s_tx_data,
+};
+
+static const struct udevice_id tegra_i2s_ids[] = {
+	{ .compatible = "nvidia,tegra124-i2s" },
+	{ }
+};
+
+U_BOOT_DRIVER(tegra_i2s) = {
+	.name		= "tegra_i2s",
+	.id		= UCLASS_I2S,
+	.of_match	= tegra_i2s_ids,
+	.probe		= tegra_i2s_probe,
+	.ops		= &tegra_i2s_ops,
+};
diff --git a/drivers/sound/tegra_i2s_priv.h b/drivers/sound/tegra_i2s_priv.h
new file mode 100644
index 00000000000..7cd3fc808c8
--- /dev/null
+++ b/drivers/sound/tegra_i2s_priv.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 Google LLC
+ * Written by Simon Glass <sjg at chromium.org>
+ */
+
+#ifndef __TEGRA_I2S_PRIV_H
+#define __TEGRA_I2S_PRIV_H
+
+enum {
+	/* Set i2s device (in buf) */
+	AHUB_MISCOP_SET_I2S,
+};
+
+/*
+ * tegra_i2s_set_cif_tx_ctrl() - Set the I2C port to send to
+ *
+ * The CIF is not really part of I2S -- it's for Audio Hub to control
+ * the interface between I2S and Audio Hub.  However since it's put in
+ * the I2S registers domain instead of the Audio Hub, we need to export
+ * this as a function.
+ *
+ * @dev: I2S device
+ * @value: Value to write to CIF_TX_CTRL register
+ * @return 0
+ */
+int tegra_i2s_set_cif_tx_ctrl(struct udevice *dev, u32 value);
+
+#endif
-- 
2.20.1.415.g653613c723-goog

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