[U-Boot] [PATCH v2] rockchip: sdram-common: fix wrong size for 4GB in 32bit SoC

[Philipp Tomsich]

Kever,

I agree that getting LPAE enabled on the RK3288 (in one of the next releases)
would be great.
We could then turn on PHYS64_BIT, never worry about this again (and
not need a workaround at all) and have the hardware’s capabilities
accurately modelled.

Let me know if I can do anything to help towards that goal.

Thanks,
Philipp.


> On 28.12.2018, at 02:56, Kever Yang <kever.yang at rock-chips.com> wrote:
> 
> This is workaround for issue we can't get correct size for 4GB ram
> in 32bit system and available before we really need ram space
> out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
> The size of 4GB is '0x1 00000000', and this value will be truncated
> to 0 in 32bit system, and system can not get correct ram size.
> Rockchip SoCs reserve a blob of space for peripheral near 4GB,
> and we are now setting SDRAM_MAX_SIZE as max available space for
> ram in 4GB, so we can use this directly to workaround the issue.
> 
> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
> ---
> 
> Changes in v2:
> - update the commit message and comment to show this is a workaround.
> 
> arch/arm/mach-rockchip/sdram_common.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
> 
> diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c
> index 650d53e4d9..a27138083a 100644
> --- a/arch/arm/mach-rockchip/sdram_common.c
> +++ b/arch/arm/mach-rockchip/sdram_common.c
> @@ -48,6 +48,24 @@ size_t rockchip_sdram_size(phys_addr_t reg)
> 		      rank, col, bk, cs0_row, bw, row_3_4);
> 	}
> 
> +	/*
> +	 * This is workaround for issue we can't get correct size for 4GB ram
> +	 * in 32bit system and available before we really need ram space
> +	 * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
> +	 * The size of 4GB is '0x1 00000000', and this value will be truncated
> +	 * to 0 in 32bit system, and system can not get correct ram size.
> +	 * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
> +	 * and we are now setting SDRAM_MAX_SIZE as max available space for
> +	 * ram in 4GB, so we can use this directly to workaround the issue.
> +	 * TODO:
> +	 *   1. update correct value for SDRAM_MAX_SIZE as what dram
> +	 *   controller sees.
> +	 *   2. update board_get_usable_ram_top() and dram_init_banksize()
> +	 *   to reserve memory for peripheral space after previous update.
> +	 */
> +	if (size_mb > (SDRAM_MAX_SIZE >> 20))
> +		size_mb = (SDRAM_MAX_SIZE >> 20);
> +
> 	return (size_t)size_mb << 20;
> }
> 
> -- 
> 2.20.1
>