[U-Boot] [PATCH v2 10/13] armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure

[Joe Hershberger]

On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson at nxp.com> wrote:
> SoC specific PFE macros are defined and structure ccsr_scfg
> is updated with members defined for PFE.
>
> Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi at nxp.com>
> ---
> Changes in v2: None
> ---
>  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 38 ++++++++++++++++++++--
>  1 file changed, 36 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> index b195005..e1a57de 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> @@ -395,6 +395,21 @@ struct ccsr_gur {
>  #define SCFG_SNPCNFGCR_SATARDSNP       0x00800000
>  #define SCFG_SNPCNFGCR_SATAWRSNP       0x00400000
>
> +/* RGMIIPCR bit definitions*/
> +#define SCFG_RGMIIPCR_EN_AUTO          (0x00000008)
> +#define SCFG_RGMIIPCR_SETSP_1000M      (0x00000004)
> +#define SCFG_RGMIIPCR_SETSP_100M       (0x00000000)
> +#define SCFG_RGMIIPCR_SETSP_10M                (0x00000002)
> +#define SCFG_RGMIIPCR_SETFD            (0x00000001)
> +
> +/*PFEASBCR bit definitions */
> +#define SCFG_PFEASBCR_ARCACHE0         (0x80000000)
> +#define SCFG_PFEASBCR_AWCACHE0         (0x40000000)
> +#define SCFG_PFEASBCR_ARCACHE1         (0x20000000)
> +#define SCFG_PFEASBCR_AWCACHE1         (0x10000000)
> +#define SCFG_PFEASBCR_ARSNP            (0x08000000)
> +#define SCFG_PFEASBCR_AWSNP            (0x04000000)

I thought you were switching to using the BIT() macro.

> +
>  /* Supplemental Configuration Unit */
>  struct ccsr_scfg {
>         u8 res_000[0x100-0x000];
> @@ -412,7 +427,12 @@ struct ccsr_scfg {
>         u8 res_140[0x158-0x140];
>         u32 altcbar;
>         u32 qspi_cfg;
> -       u8 res_160[0x180-0x160];
> +       u8 res_160[0x164 - 0x160];
> +       u32 wr_qos1;
> +       u32 wr_qos2;
> +       u32 rd_qos1;
> +       u32 rd_qos2;
> +       u8 res_174[0x180 - 0x174];
>         u32 dmamcr;
>         u8 res_184[0x188-0x184];
>         u32 gic_align;
> @@ -443,7 +463,21 @@ struct ccsr_scfg {
>         u32 usb_refclk_selcr1;
>         u32 usb_refclk_selcr2;
>         u32 usb_refclk_selcr3;
> -       u8 res_424[0x600-0x424];
> +       u8 res_424[0x434 - 0x424];
> +       u32 rgmiipcr;
> +       u32 res_438;
> +       u32 rgmiipsr;
> +       u32 pfepfcssr1;
> +       u32 pfeintencr1;
> +       u32 pfepfcssr2;
> +       u32 pfeintencr2;
> +       u32 pfeerrcr;
> +       u32 pfeeerrintencr;
> +       u32 pfeasbcr;
> +       u32 pfebsbcr;
> +       u8 res_460[0x484 - 0x460];
> +       u32 mdioselcr;
> +       u8 res_468[0x600 - 0x488];
>         u32 scratchrw[4];
>         u8 res_610[0x680-0x610];
>         u32 corebcr;
> --
> 2.7.4
>
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