[U-Boot] [PATCH 06/12] net: phy: ti: Recover from "port mirroring" N/A MODE4

[Lukasz Majewski]

Hi Janine,

> The DP83867 when not properly bootstrapped - especially with LED_0
> pin - can enter N/A MODE4 for "port mirroring" feature.
> 
> To provide normal operation of the PHY, one needs not only to
> explicitly disable the port mirroring feature, but as well stop some
> IC internal testing (which disables RGMII communication).
> 
> To do that the STRAP_STS1 (0x006E) register must be read and RESERVED
> bit 11 examined. When it is set, the another RESERVED bit (11) at
> PHYCR (0x0010) register must be clear to disable testing mode and
> enable RGMII communication.
> 
> Thorough explanation of the problem can be found at following e2e
> thread: "DP83867IR: Problem with RESERVED bits in PHY Control
> Register (PHYCR) - Linux driver"
> 
> https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954
> 
> Based on commit 'ac6e058b75be71208e98a5808453aae9a17be480' of
> mainline linux kernel.
> 

Thanks for bringing it into u-boot.

Acked-by: Lukasz Majewski <lukma at denx.de>

> Signed-off-by: Janine Hagemann <j.hagemann at phytec.de>
> ---
>  drivers/net/phy/ti.c | 24 +++++++++++++++++++++++-
>  1 file changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
> index 086ea4a..16c8929 100644
> --- a/drivers/net/phy/ti.c
> +++ b/drivers/net/phy/ti.c
> @@ -26,6 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
>  /* Extended Registers */
>  #define DP83867_CFG4		0x0031
>  #define DP83867_RGMIICTL	0x0032
> +#define DP83867_STRAP_STS1	0x006E
>  #define DP83867_RGMIIDCTL	0x0086
>  #define DP83867_IO_MUX_CFG	0x0170
>  
> @@ -50,6 +51,9 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define DP83867_RGMII_TX_CLK_DELAY_EN		BIT(1)
>  #define DP83867_RGMII_RX_CLK_DELAY_EN		BIT(0)
>  
> +/* STRAP_STS1 bits */
> +#define DP83867_STRAP_STS1_RESERVED		BIT(11)
> +
>  /* PHY CTRL bits */
>  #define DP83867_PHYCR_FIFO_DEPTH_SHIFT		14
>  #define DP83867_PHYCR_FIFO_DEPTH_MASK	(3 << 14)
> @@ -251,7 +255,7 @@ static int dp83867_config(struct phy_device
> *phydev) {
>  	struct dp83867_private *dp83867;
>  	unsigned int val, delay, cfg2;
> -	int ret;
> +	int ret, bs;
>  
>  	if (!phydev->priv) {
>  		dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
> @@ -282,6 +286,24 @@ static int dp83867_config(struct phy_device
> *phydev) 
>  		if (ret)
>  			goto err_out;
> +
> +		/* The code below checks if "port mirroring" N/A
> MODE4 has been
> +		 * enabled during power on bootstrap.
> +		 *
> +		 * Such N/A mode enabled by mistake can put PHY IC
> in some
> +		 * internal testing mode and disable RGMII
> transmission.
> +		 *
> +		 * In this particular case one needs to check
> STRAP_STS1
> +		 * register's bit 11 (marked as RESERVED).
> +		 */
> +
> +		bs = phy_read_mmd_indirect(phydev,
> DP83867_STRAP_STS1,
> +						DP83867_DEVADDR,
> phydev->addr);
> +		if (bs & DP83867_STRAP_STS1_RESERVED)
> +			val &= ~DP83867_PHYCR_RESERVED_MASK;
> +
> +		phy_write(phydev, MDIO_DEVAD_NONE,
> MII_DP83867_PHYCTRL, val); +
>  	} else if (phy_interface_is_sgmii(phydev)) {
>  		phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
>  			  (BMCR_ANENABLE | BMCR_FULLDPLX |
> BMCR_SPEED1000));




Best regards,

Lukasz Majewski

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