[U-Boot] [PATCH] mmc: sdhci: consider SDHCI_QUIRK_NO_HISPD_BIT in host_caps

[Hannes Schmelzer]

Some IP-core implementations of the SDHCI have different troubles on the
silicon where they are placed.

On ZYNQ platform for example Xilinx doesn't accept the hold timing of an
eMMC chip which operates in High-Speed mode. Due to this fact the
"SDHCI_QUIRK_NO_HISPD_BIT" quirk was born.

This commit reflects this fact within the host-controller capabilities,
so that the layer above (mmc-driver) can setup the card correctly.

Otherwise the MMC card will be switched into high-speed mode and causes
possible timing violation on the host-controller side.

Signed-off-by: Hannes Schmelzer <oe5hpm at oevsv.at>

---

 drivers/mmc/sdhci.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index d31793a..defe6db 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -602,6 +602,11 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 			cfg->host_caps &= ~MMC_MODE_8BIT;
 	}
 
+	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) {
+		cfg->host_caps &= ~MMC_MODE_HS;
+		cfg->host_caps &= ~MMC_MODE_HS_52MHz;
+	}
+
 	if (host->host_caps)
 		cfg->host_caps |= host->host_caps;
 
-- 
2.7.4