[U-Boot] [PATCH] arm: socfpga: gen5: Enabling cache and TLB maintenance broadcast

[Marek Vasut]

On 02/28/2018 06:12 AM, chin.liang.see at intel.com wrote:
> From: Chin Liang See <chin.liang.see at intel.com>
> 
> Enabling cache and TLB maintenance broadcast through ACTLR as required
> by Linux.

This needs far more clarification. What is the problem you're fixing
here ? How does it fix the problem ?

> Signed-off-by: Chin Liang See <chin.liang.see at intel.com>
> ---
>  arch/arm/mach-socfpga/misc_gen5.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
> index a7dcacc..7c7a708 100644
> --- a/arch/arm/mach-socfpga/misc_gen5.c
> +++ b/arch/arm/mach-socfpga/misc_gen5.c
> @@ -239,7 +239,7 @@ static u32 iswgrp_handoff[8];
>  
>  int arch_early_init_r(void)
>  {
> -	int i;
> +	int i, val;
>  
>  	/*
>  	 * Write magic value into magic register to unlock support for
> @@ -285,6 +285,15 @@ int arch_early_init_r(void)
>  	socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
>  #endif
>  
> +	/* Enable cache and TLB maintainance broadcast as required by Linux */
> +	/* Read auxiliary control register */
> +	asm volatile ("mrc     p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
> +	val |= (1 << 0);
> +	/* Write auxiliary control register */
> +	asm volatile ("mcr     p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
> +	CP15DSB;
> +	CP15ISB;
> +
>  	return 0;
>  }
>  
> 


-- 
Best regards,
Marek Vasut