[U-Boot] [PATCH] arm: socfpga: gen5: Enabling cache and TLB maintenance broadcast

[Dinh Nguyen]

On 03/08/2018 08:01 AM, See, Chin Liang wrote:
> On Thu, 2018-03-01 at 17:17 +0100, Marek Vasut wrote:
>> On 02/28/2018 06:12 AM, chin.liang.see at intel.com wrote:
>>>
>>> From: Chin Liang See <chin.liang.see at intel.com>
>>>
>>> Enabling cache and TLB maintenance broadcast through ACTLR as
>>> required
>>> by Linux.
>> This needs far more clarification. What is the problem you're fixing
>> here ? How does it fix the problem ?
> 
> Sure. When the 2 processors is enabled with SMP, popen operation would
> fail as content are different after the copy. This issue goes away when
> we force Linux to run with 1 core only. Checked with ARM, this bit is
> required by Linux when running SMP.
> 

What's a "popen" operation? Shouldn't you also set the SMP along with
the FW bit?

Dinh