[U-Boot] [PATCH 1/2] ARM: dts: zynq: Update dts for Z-turn board
Michal Simek
michal.simek at xilinx.com
Thu Mar 15 06:44:41 UTC 2018
On 14.3.2018 23:40, Anton Gerasimov wrote:
> Hi Alexander,
>
>
>>> device_type = "memory";
>>> reg = <0x0 0x40000000>;
>>> };
>>> chosen {
>>> - stdout-path = "serial0:115200n8";
>> Nack. By default graphical output is quite unusable on this board, so we
>> want to output to serial.
>>
>> If your Linux submitted device tree doesn't contain this part, please
>> fix it there.
>>
>>> + bootargs = "console=ttyPS0,115200 earlyprintk
>>> root=/dev/mmcblk0p2 rootwait";
>> This is even worse. Please don't prepopulate any bootargs, otherwise
>> people may end up assuming that they're actually getting used.
>
> The older one is much cleaner I agree, thank you. I'll just need to test
> with both u-boot and linux.
>
>>> };
>>> gpio-leds {
>>> compatible = "gpio-leds";
>>> - led_r {
>>> - label = "led_r";
>>> - gpios = <&gpio0 0x72 0x1>;
>>> - default-state = "on";
>>> - linux,default-trigger = "heartbeat";
>>> - };
>>> -
>>> - led_g {
>>> - label = "led_g";
>>> - gpios = <&gpio0 0x73 0x1>;
>>> - default-state = "on";
>>> - linux,default-trigger = "heartbeat";
>>> - };
>>> -
>>> - led_b {
>>> - label = "led_b";
>>> - gpios = <&gpio0 0x74 0x1>;
>>> - default-state = "on";
>>> - linux,default-trigger = "heartbeat";
>>> - };
>> Why remove them? They're hard wired on the board, no?
> No this RGB LED is connected to PL, that's for sure.
>
>>> ps-clk-frequency = <33333333>;
>>> - fclk-enable = <0xf>;
>> Why?
>
>> IIRC on my Z-Turn, I had to take a PL clock back into the PS as AXI
>> reference clock. See "Connect clocks" here:
>>
>>
>>
>> https://wiki.hackerspace.pl/projects:zturn-hackers:helloworld
>>
>>
>>
>> So we need to have the PL clock enabled, no? Or is that only needed for
>> PL AXI peripherals?
>>
>
> As far as I understand M_AXI_GPn connects AXI slaves implemented on PL
> to AXI and S_AXI_HPn provides access for AXI slaves in PS to PL slaves.
> So both involve PL and can be disconnected if PL is not clocked.
As you see that connection is done via PL. I am booting zynq boards
without fclk-enable and without PL and they are booting properly.
I have never had a time to investing what it is broken if you don't load
bitstream. Definitely feel free to test.
And as you see only one clk is used not all 4.
>
>>> };
>>> &qspi {
>>> @@ -152,8 +114,8 @@
>>> reg = <0x49>;
>>> };
>>> - adxl345 at 53 {
>>> - compatible = "adi,adxl34x", "adxl34x";
>>> + accelerometer at 53 {
>>> + compatible = "adi,adxl345", "adxl345";
>> You can't just remove compatibles. Device trees are supposed to be
>> compatible with whatever used them before someone thought they want to
>> prettify them, so in this case you'd have to add the concrete names in
>> the list before the abstract ones:
>>
>> compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
> Yes sorry, I didn't realize that Linux kernel had both.
Ok. I think it will be good to sync these two dts with the kernel. It
means can you please send new updated version for linux kernel too?
Thanks,
Michal
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