[U-Boot] [PATCH v1 03/19] phy: marvell: a3700: Don't create functional macro for each register
Stefan Roese
sr at denx.de
Wed Mar 21 08:41:12 UTC 2018
On 07.03.2018 22:52, Marek Behún wrote:
> Currently there is for each register special functional macro, ie:
> LANE_CFG1_ADDR(u)
> GLOB_CLK_SRC_LO_ADDR(u)
> ...
> where can be either PCIE or USB3.
>
> Change this to one function PHY_ADDR(unit, addr). The code becomes:
> PHY_ADDR(PCIE, LANE_CFG1)
> PHY_ADDR(PCIE, GLOB_CLK_SRC_LO)
> ...
>
> Signed-off-by: Marek Behun <marek.behun at nic.cz>
> ---
> drivers/phy/marvell/comphy_a3700.c | 105 ++++++++++++++++++-------------------
> drivers/phy/marvell/comphy_a3700.h | 92 +++++++++++++-------------------
> 2 files changed, 89 insertions(+), 108 deletions(-)
>
> diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
> index 505e0933a3..6506c134e2 100644
> --- a/drivers/phy/marvell/comphy_a3700.c
> +++ b/drivers/phy/marvell/comphy_a3700.c
> @@ -141,72 +141,70 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
> /*
> * 1. Enable max PLL.
> */
> - reg_set16(LANE_CFG1_ADDR(PCIE), bf_use_max_pll_rate, 0);
> + reg_set16(PHY_ADDR(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0);
>
> /*
> * 2. Select 20 bit SERDES interface.
> */
> - reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE), bf_cfg_sel_20b, 0);
> + reg_set16(PHY_ADDR(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0);
>
> /*
> * 3. Force to use reg setting for PCIe mode
> */
> - reg_set16(MISC_REG1_ADDR(PCIE), bf_sel_bits_pcie_force, 0);
> + reg_set16(PHY_ADDR(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0);
>
> /*
> * 4. Change RX wait
> */
> - reg_set16(PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0xFFFF);
> + reg_set16(PHY_ADDR(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF);
>
> /*
> * 5. Enable idle sync
> */
> - reg_set16(UNIT_CTRL_ADDR(PCIE), 0x60 | rb_idle_sync_en, 0xFFFF);
> + reg_set16(PHY_ADDR(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF);
>
> /*
> * 6. Enable the output of 100M/125M/500M clock
> */
> - reg_set16(MISC_REG0_ADDR(PCIE),
> + reg_set16(PHY_ADDR(PCIE, MISC_REG0),
> 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF);
>
> /*
> * 7. Enable TX
> */
> - reg_set(PHY_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF);
> + reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF);
>
> /*
> * 8. Check crystal jumper setting and program the Power and PLL
> * Control accordingly
> */
> if (get_ref_clk() == 40) {
> - reg_set16(PWR_PLL_CTRL_ADDR(PCIE),
> - 0xFC63, 0xFFFF); /* 40 MHz */
> + /* 40 MHz */
> + reg_set16(PHY_ADDR(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF);
> } else {
> - reg_set16(PWR_PLL_CTRL_ADDR(PCIE),
> - 0xFC62, 0xFFFF); /* 25 MHz */
> + /* 25 MHz */
> + reg_set16(PHY_ADDR(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF);
> }
>
> /*
> * 9. Override Speed_PLL value and use MAC PLL
> */
> - reg_set16(KVCO_CAL_CTRL_ADDR(PCIE), 0x0040 | rb_use_max_pll_rate,
> + reg_set16(PHY_ADDR(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate,
> 0xFFFF);
>
> /*
> * 10. Check the Polarity invert bit
> */
> - if (invert & PHY_POLARITY_TXD_INVERT) {
> - reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_txd_inv, 0);
> - }
> + if (invert & PHY_POLARITY_TXD_INVERT)
> + reg_set16(PHY_ADDR(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
>
> - if (invert & PHY_POLARITY_RXD_INVERT) {
> - reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_rxd_inv, 0);
> - }
> + if (invert & PHY_POLARITY_RXD_INVERT)
> + reg_set16(PHY_ADDR(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
>
> /*
> * 11. Release SW reset
> */
> - reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE),
> + reg_set16(PHY_ADDR(PCIE, GLOB_PHY_CTRL0),
> rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32,
> bf_soft_rst | bf_mode_refdiv);
>
> @@ -214,11 +212,11 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
> udelay(PLL_SET_DELAY_US);
>
> /* Assert PCLK enabled */
> - ret = comphy_poll_reg(LANE_STAT1_ADDR(PCIE), /* address */
> - rb_txdclk_pclk_en, /* value */
> - rb_txdclk_pclk_en, /* mask */
> - PLL_LOCK_TIMEOUT, /* timeout */
> - POLL_16B_REG); /* 16bit */
> + ret = comphy_poll_reg(PHY_ADDR(PCIE, LANE_STAT1), /* address */
> + rb_txdclk_pclk_en, /* value */
> + rb_txdclk_pclk_en, /* mask */
> + PLL_LOCK_TIMEOUT, /* timeout */
> + POLL_16B_REG); /* 16bit */
> if (ret == 0)
> printf("Failed to lock PCIe PLL\n");
>
> @@ -322,7 +320,7 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert)
>
> /* 0xd005c300 = 0x1001 */
> /* set PRD_TXDEEMPH (3.5db de-emph) */
> - reg_set16(LANE_CFG0_ADDR(USB3), 0x1, 0xFF);
> + reg_set16(PHY_ADDR(USB3, LANE_CFG0), 0x1, 0xFF);
>
> /*
> * unset BIT0: set Tx Electrical Idle Mode: Transmitter is in
> @@ -330,81 +328,82 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert)
> */
> /* unset BIT4: set G2 Tx Datapath with no Delayed Latency */
> /* unset BIT6: set Tx Detect Rx Mode at LoZ mode */
> - reg_set16(LANE_CFG1_ADDR(USB3), 0x0, 0xFFFF);
> + reg_set16(PHY_ADDR(USB3, LANE_CFG1), 0x0, 0xFFFF);
>
>
> /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */
> - reg_set16(LANE_CFG4_ADDR(USB3), bf_spread_spectrum_clock_en, 0x80);
> + reg_set16(PHY_ADDR(USB3, LANE_CFG4), bf_spread_spectrum_clock_en, 0x80);
>
> /*
> * set Override Margining Controls From the MAC: Use margining signals
> * from lane configuration
> */
> - reg_set16(TEST_MODE_CTRL_ADDR(USB3), rb_mode_margin_override, 0xFFFF);
> + reg_set16(PHY_ADDR(USB3, TEST_MODE_CTRL), rb_mode_margin_override, 0xFFFF);
>
> /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */
> /* set Mode Clock Source = PCLK is generated from REFCLK */
> - reg_set16(GLOB_CLK_SRC_LO_ADDR(USB3), 0x0, 0xFF);
> + reg_set16(PHY_ADDR(USB3, GLOB_CLK_SRC_LO), 0x0, 0xFF);
>
> /* set G2 Spread Spectrum Clock Amplitude at 4K */
> - reg_set16(GEN2_SETTING_2_ADDR(USB3), g2_tx_ssc_amp, 0xF000);
> + reg_set16(PHY_ADDR(USB3, GEN2_SETTINGS_2), g2_tx_ssc_amp, 0xF000);
>
> /*
> * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register
> * Master Current Select
> */
> - reg_set16(GEN2_SETTING_3_ADDR(USB3), 0x0, 0xFFFF);
> + reg_set16(PHY_ADDR(USB3, GEN2_SETTINGS_3), 0x0, 0xFFFF);
>
> /*
> * 3. Check crystal jumper setting and program the Power and PLL
> * Control accordingly
> */
> if (get_ref_clk() == 40) {
> - reg_set16(PWR_PLL_CTRL_ADDR(USB3), 0xFCA3, 0xFFFF); /* 40 MHz */
> + /* 40 MHz */
> + reg_set16(PHY_ADDR(USB3, PWR_PLL_CTRL), 0xFCA3, 0xFFFF);
> } else {
> - reg_set16(PWR_PLL_CTRL_ADDR(USB3), 0xFCA2, 0xFFFF); /* 25 MHz */
> + /* 25 MHz */
> + reg_set16(PHY_ADDR(USB3, PWR_PLL_CTRL), 0xFCA2, 0xFFFF);
> }
>
> /*
> * 4. Change RX wait
> */
> - reg_set16(PWR_MGM_TIM1_ADDR(USB3), 0x10C, 0xFFFF);
> + reg_set16(PHY_ADDR(USB3, PWR_MGM_TIM1), 0x10C, 0xFFFF);
>
> /*
> * 5. Enable idle sync
> */
> - reg_set16(UNIT_CTRL_ADDR(USB3), 0x60 | rb_idle_sync_en, 0xFFFF);
> + reg_set16(PHY_ADDR(USB3, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF);
>
> /*
> * 6. Enable the output of 500M clock
> */
> - reg_set16(MISC_REG0_ADDR(USB3), 0xA00D | rb_clk500m_en, 0xFFFF);
> + reg_set16(PHY_ADDR(USB3, MISC_REG0), 0xA00D | rb_clk500m_en, 0xFFFF);
>
> /*
> * 7. Set 20-bit data width
> */
> - reg_set16(DIG_LB_EN_ADDR(USB3), 0x0400, 0xFFFF);
> + reg_set16(PHY_ADDR(USB3, DIG_LB_EN), 0x0400, 0xFFFF);
>
> /*
> * 8. Override Speed_PLL value and use MAC PLL
> */
> - reg_set16(KVCO_CAL_CTRL_ADDR(USB3), 0x0040 | rb_use_max_pll_rate, 0xFFFF);
> + reg_set16(PHY_ADDR(USB3, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate,
> + 0xFFFF);
>
> /*
> * 9. Check the Polarity invert bit
> */
> - if (invert & PHY_POLARITY_TXD_INVERT) {
> - reg_set16(SYNC_PATTERN_ADDR(USB3), phy_txd_inv, 0);
> - }
> + if (invert & PHY_POLARITY_TXD_INVERT)
> + reg_set16(PHY_ADDR(USB3, SYNC_PATTERN), phy_txd_inv, 0);
>
> - if (invert & PHY_POLARITY_RXD_INVERT) {
> - reg_set16(SYNC_PATTERN_ADDR(USB3), phy_rxd_inv, 0);
> - }
> + if (invert & PHY_POLARITY_RXD_INVERT)
> + reg_set16(PHY_ADDR(USB3, SYNC_PATTERN), phy_rxd_inv, 0);
>
> /*
> * 10. Release SW reset
> */
> - reg_set16(GLOB_PHY_CTRL0_ADDR(USB3),
> + reg_set16(PHY_ADDR(USB3, GLOB_PHY_CTRL0),
> rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 | 0x20,
> 0xFFFF);
>
> @@ -412,7 +411,7 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert)
> udelay(PLL_SET_DELAY_US);
>
> /* Assert PCLK enabled */
> - ret = comphy_poll_reg(LANE_STAT1_ADDR(USB3), /* address */
> + ret = comphy_poll_reg(PHY_ADDR(USB3, LANE_STAT1), /* address */
> rb_txdclk_pclk_en, /* value */
> rb_txdclk_pclk_en, /* mask */
> PLL_LOCK_TIMEOUT, /* timeout */
> @@ -673,25 +672,25 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
> mdelay(10);
>
> /* 9. Program COMPHY register PHY_MODE */
> - reg_set16(SGMIIPHY_ADDR(lane, PHY_PWR_PLL_CTRL_ADDR),
> + reg_set16(SGMIIPHY_ADDR(lane, PWR_PLL_CTRL),
> PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask);
>
> /*
> * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK
> * source
> */
> - reg_set16(SGMIIPHY_ADDR(lane, PHY_MISC_REG0_ADDR), 0, rb_ref_clk_sel);
> + reg_set16(SGMIIPHY_ADDR(lane, MISC_REG0), 0, rb_ref_clk_sel);
>
> /*
> * 11. Set correct reference clock frequency in COMPHY register
> * REF_FREF_SEL.
> */
> if (get_ref_clk() == 40) {
> - reg_set16(SGMIIPHY_ADDR(lane, PHY_PWR_PLL_CTRL_ADDR),
> + reg_set16(SGMIIPHY_ADDR(lane, PWR_PLL_CTRL),
> 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
> } else {
> /* 25MHz */
> - reg_set16(SGMIIPHY_ADDR(lane, PHY_PWR_PLL_CTRL_ADDR),
> + reg_set16(SGMIIPHY_ADDR(lane, PWR_PLL_CTRL),
> 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
> }
>
> @@ -708,7 +707,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
> * bus width
> */
> /* 10bit */
> - reg_set16(SGMIIPHY_ADDR(lane, PHY_DIG_LB_EN_ADDR), 0, rf_data_width_mask);
> + reg_set16(SGMIIPHY_ADDR(lane, DIG_LB_EN), 0, rf_data_width_mask);
>
> /*
> * 14. As long as DFE function needs to be enabled in any mode,
> @@ -751,10 +750,10 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
> * 18. Check the PHY Polarity invert bit
> */
> if (invert & PHY_POLARITY_TXD_INVERT)
> - reg_set16(SGMIIPHY_ADDR(lane, PHY_SYNC_PATTERN_ADDR), phy_txd_inv, 0);
> + reg_set16(SGMIIPHY_ADDR(lane, SYNC_PATTERN), phy_txd_inv, 0);
>
> if (invert & PHY_POLARITY_RXD_INVERT)
> - reg_set16(SGMIIPHY_ADDR(lane, PHY_SYNC_PATTERN_ADDR), phy_rxd_inv, 0);
> + reg_set16(SGMIIPHY_ADDR(lane, SYNC_PATTERN), phy_rxd_inv, 0);
>
> /*
> * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1
> diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h
> index a315bf2647..5031c25eb1 100644
> --- a/drivers/phy/marvell/comphy_a3700.h
> +++ b/drivers/phy/marvell/comphy_a3700.h
> @@ -71,116 +71,98 @@ static inline void __iomem *SGMIIPHY_ADDR(u32 lane, u32 addr)
> }
>
> /* units */
> -#define PCIE 1
> -#define USB3 2
> +enum phy_unit {
> + PCIE = 1,
> + USB3 = 2,
> +};
>
> -#define PHY_BASE(unit) ((unit == PCIE) ? PCIEPHY_BASE : USB3PHY_BASE)
> -#define PHY_SHFT(unit) ((unit == PCIE) ? PCIEPHY_SHFT : USB3PHY_SHFT)
> +static inline void __iomem *PHY_ADDR(enum phy_unit unit, u32 addr)
> +{
> + if (unit == PCIE)
> + return PCIEPHY_BASE + addr * PCIEPHY_SHFT;
> + else
> + return USB3PHY_BASE + addr * USB3PHY_SHFT;
> +}
Again, please lowercase functions names, when changing macros to (static
inline) functions. Please do this in all occurrences.
Thanks,
Stefan
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