[U-Boot] [PATCH v1 09/19] phy: marvell: a3700: revise the USB3 comphy setting during power on

[Stefan Roese]

On 07.03.2018 22:52, Marek Behún wrote:
> This commit is based on commit d9899826 by
>    zachary <zhangzg at marvell.com>
> from u-boot-marvell, see
> github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/d9899826

If its largely based on this commit, then you need to add a "From: ..."
as fist line of this patch to keep the authorship of this patch.

> - According to design specification, the transmitter should be set to high
>    impedence mode during electrical idle. Thus transmitter should detect RX
>    at high impedence mode also, and delay is needed to accommodate high
>    impedence off latency. Otherwise the USB3 will have detection issue that
>    most of the time the USB3 device can not be detected at all, or be
>    detected as USB2 device sometimes.
>    Modified registers: RD005C302h (R181h) (0051h) Lane Configuration 1
>    Bit 6: set to 1 to let Tx detect Rx at HiZ mode
>    Bit [3:4]: set to 2 to be delayed by 2 clock cycles
>    Bit 0: set to 1 to set transmitter to high impedance mode during idle.
> - USB3 De-emphasize level of -3.5dB is mandatory, but USB3 MAC selects 0x2
>    (emphasize disabled) in the MAC_PHY_TXDEEMPH [1:0], while it is supposed
>    to select 0x1(3.5dB emphasize). Thus need to override what comes from
>    the MAC(by setting register 0x1c2 bit2 to 0x1) and to configure the
>    overridded values of MAC_PHY_TXDEEMPH [1:0] to 0x1(bit15 of register
>    0x181 and bit0 of register 0x180).
> - According to USB3 application note, need to update below comphy
>    registers:
>    Set max speed generation to USB3.0 5Gbps(set RD005C04Ah bit[11:10] to 1)
>    Set capacitor value to 0xF(set RF005C224 bit[3:0] to 0xF)
> 
> Signed-off-by: Marek Behun <marek.behun at nic.cz>
> ---
>   drivers/phy/marvell/comphy_a3700.c | 31 +++++++++++++++++++++++--------
>   drivers/phy/marvell/comphy_a3700.h |  5 +++++
>   2 files changed, 28 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
> index 78caa96014..1182842609 100644
> --- a/drivers/phy/marvell/comphy_a3700.c
> +++ b/drivers/phy/marvell/comphy_a3700.c
> @@ -361,13 +361,18 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
>   	usb3_reg_set16(LANE_CFG0, 0x1, 0xFF);
>   
>   	/*
> -	 * unset BIT0: set Tx Electrical Idle Mode: Transmitter is in
> -	 *             low impedance mode during electrical idle
> -	 * unset BIT4: set G2 Tx Datapath with no Delayed Latency
> -	 * unset BIT6: set Tx Detect Rx Mode at LoZ mode
> -	 */
> -	usb3_reg_set16(LANE_CFG1, 0x0, 0xFFFF);
> -
> +	 * Set BIT0: enable transmitter in high impedance mode
> +	 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
> +	 * Set BIT6: Tx detect Rx at HiZ mode
> +	 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
> +	 *              together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR
> +	 *              register
> +	 */
> +	usb3_reg_set16(LANE_CFG1,
> +		       tx_det_rx_mode | gen2_tx_data_dly_deft
> +		       | tx_elec_idle_mode_en,
> +		       prd_txdeemph1_mask | tx_det_rx_mode
> +		       | gen2_tx_data_dly_mask | tx_elec_idle_mode_en);
>   
>   	/* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */
>   	usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80);
> @@ -436,7 +441,17 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
>   		usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0);
>   
>   	/*
> -	 * 10. Release SW reset
> +	 * 10. Set max speed generation to USB3.0 5Gbps
> +	 */
> +	usb3_reg_set16(SYNC_MASK_GEN, 0x0400, 0x0C00);
> +
> +	/*
> +	 * 11. Set capacitor value for FFE gain peaking to 0xF
> +	 */
> +	usb3_reg_set16(GEN3_SETTINGS_3, 0xF, 0xF);
> +
> +	/*
> +	 * 12. Release SW reset
>   	 */
>   	usb3_reg_set16(GLOB_PHY_CTRL0,
>   		       rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32
> diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h
> index 772e86515a..ef55f719b9 100644
> --- a/drivers/phy/marvell/comphy_a3700.h
> +++ b/drivers/phy/marvell/comphy_a3700.h
> @@ -142,6 +142,11 @@ static inline void __iomem *PHY_ADDR(enum phy_unit unit, u32 addr)
>   
>   #define LANE_CFG1			0x181
>   #define bf_use_max_pll_rate		BIT(9)
> +#define prd_txdeemph1_mask		BIT(15)
> +#define tx_det_rx_mode			BIT(6)
> +#define gen2_tx_data_dly_deft		(2 << 3)
> +#define gen2_tx_data_dly_mask		(BIT(3) | BIT(4))
> +#define tx_elec_idle_mode_en		BIT(0)

I know that you didn't introduce these macros in lowercase, but it would
be great if you could convert them into uppercase completely. Perhaps
in a separate patch.

Thanks,
Stefan