[U-Boot] [PATCH] timer: Add High Precision Event Timers (HPET) support
Ivan Gorinov
ivan.gorinov at intel.com
Thu Mar 29 00:58:44 UTC 2018
Adding HPET as an alternative timer for x86 (default is TSC).
HPET main counter has constant clock frequency, calibration is not required.
This change also makes TSC timer driver optional on x86 platforms.
If X86_TSC is disabled, early timer functions are provided by HPET.
HPET can be selected as the tick timer in the Device Tree "chosen" node:
/include/ "hpet.dtsi"
chosen {
tick-timer = "/hpet0";
};
Signed-off-by: Ivan Gorinov <ivan.gorinov at intel.com>
---
arch/Kconfig | 2 +-
arch/x86/dts/hpet.dtsi | 7 ++
drivers/timer/Kconfig | 6 ++
drivers/timer/Makefile | 1 +
drivers/timer/hpet_timer.c | 197 +++++++++++++++++++++++++++++++++++++++++++++
5 files changed, 212 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/dts/hpet.dtsi
create mode 100644 drivers/timer/hpet_timer.c
diff --git a/arch/Kconfig b/arch/Kconfig
index e599e7a..37dabae 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -104,7 +104,7 @@ config X86
select DM_PCI
select PCI
select TIMER
- select X86_TSC_TIMER
+ imply X86_TSC_TIMER
imply BLK
imply DM_ETH
imply DM_GPIO
diff --git a/arch/x86/dts/hpet.dtsi b/arch/x86/dts/hpet.dtsi
new file mode 100644
index 0000000..037dc7e
--- /dev/null
+++ b/arch/x86/dts/hpet.dtsi
@@ -0,0 +1,7 @@
+/ {
+ hpet0: hpet at fed00000 {
+ compatible = "hpet-x86";
+ u-boot,dm-pre-reloc;
+ reg = <0xfed00000 0x1000>;
+ };
+};
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 2c96896..72ae6c5 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -65,6 +65,12 @@ config X86_TSC_TIMER
help
Select this to enable Time-Stamp Counter (TSC) timer for x86.
+config HPET_TIMER
+ bool "High Precision Event Timers (HPET) support"
+ depends on TIMER && X86
+ help
+ Select this to enable High Precision Event Timers (HPET) for x86.
+
config OMAP_TIMER
bool "Omap timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index a6e7832..557fecc 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -8,6 +8,7 @@ obj-y += timer-uclass.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
+obj-$(CONFIG_HPET_TIMER) += hpet_timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
obj-$(CONFIG_AST_TIMER) += ast_timer.o
obj-$(CONFIG_STI_TIMER) += sti-timer.o
diff --git a/drivers/timer/hpet_timer.c b/drivers/timer/hpet_timer.c
new file mode 100644
index 0000000..66462a6
--- /dev/null
+++ b/drivers/timer/hpet_timer.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <timer.h>
+#include <asm/cpu.h>
+#include <asm/io.h>
+#include <asm/u-boot-x86.h>
+
+#define HPET_PERIOD_REG 0x004
+#define HPET_CONFIG_REG 0x010
+#define HPET_MAIN_COUNT_L 0x0f0
+#define HPET_MAIN_COUNT_H 0x0f4
+
+#define HPET_MAX_PERIOD 100000000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct hpet_timer_priv {
+ void *regs;
+};
+
+static inline u32 freq_hz(u32 period)
+{
+ u64 d = 1000000000000000ull;
+
+ d += period / 2;
+
+ return d / period;
+}
+
+static int hpet_timer_get_count(struct udevice *dev, u64 *count)
+{
+ struct hpet_timer_priv *priv = dev_get_priv(dev);
+ u64 now_tick;
+ u32 tl, th, th0;
+
+ th = readl(priv->regs + HPET_MAIN_COUNT_H);
+ do {
+ th0 = th;
+ tl = readl(priv->regs + HPET_MAIN_COUNT_L);
+ th = readl(priv->regs + HPET_MAIN_COUNT_H);
+ } while (th != th0);
+
+ now_tick = th;
+ now_tick <<= 32;
+ now_tick |= tl;
+
+ *count = now_tick;
+
+ return 0;
+}
+
+static int hpet_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct hpet_timer_priv *priv = dev_get_priv(dev);
+ u32 period, config;
+
+ period = readl(priv->regs + HPET_PERIOD_REG);
+ if (period == 0)
+ return -ENODEV;
+ if (period > HPET_MAX_PERIOD)
+ return -ENODEV;
+
+ config = readl(priv->regs + HPET_CONFIG_REG);
+ config &= ~1;
+ writel(config, priv->regs + HPET_CONFIG_REG);
+ writel(0, priv->regs + HPET_MAIN_COUNT_L);
+ writel(0, priv->regs + HPET_MAIN_COUNT_H);
+ config |= 1;
+ writel(config, priv->regs + HPET_CONFIG_REG);
+
+ uc_priv->clock_rate = freq_hz(period);
+
+ return 0;
+}
+
+#ifndef CONFIG_X86_TSC_TIMER
+
+#define EARLY_HPET_BASE 0xfed00000
+
+unsigned long notrace timer_early_get_rate(void)
+{
+ void *regs = (void *) EARLY_HPET_BASE;
+ u32 period, config;
+
+ period = readl(regs + HPET_PERIOD_REG);
+ if (period == 0)
+ return -ENODEV;
+ if (period > HPET_MAX_PERIOD)
+ return -ENODEV;
+
+ config = readl(regs + HPET_CONFIG_REG);
+ config |= 1;
+ writel(config, regs + HPET_CONFIG_REG);
+
+ return freq_hz(period);
+}
+
+u64 notrace timer_early_get_count(void)
+{
+ void *regs = (void *) EARLY_HPET_BASE;
+ u64 now_tick;
+ u32 tl, th, th0;
+
+ th = readl(regs + HPET_MAIN_COUNT_H);
+ do {
+ th0 = th;
+ tl = readl(regs + HPET_MAIN_COUNT_L);
+ th = readl(regs + HPET_MAIN_COUNT_H);
+ } while (th != th0);
+
+ now_tick = th;
+ now_tick <<= 32;
+ now_tick |= tl;
+
+ return now_tick;
+}
+
+int timer_init(void)
+{
+ void *regs = (void *) EARLY_HPET_BASE;
+ u32 period, config;
+
+ period = readl(regs + HPET_PERIOD_REG);
+ if (period == 0)
+ return -ENODEV;
+ if (period > HPET_MAX_PERIOD)
+ return -ENODEV;
+
+ config = readl(regs + HPET_CONFIG_REG);
+ config &= ~1;
+ writel(config, regs + HPET_CONFIG_REG);
+ writel(0, regs + HPET_MAIN_COUNT_L);
+ writel(0, regs + HPET_MAIN_COUNT_H);
+ config |= 1;
+ writel(config, regs + HPET_CONFIG_REG);
+
+ return 0;
+}
+
+ulong timer_get_boot_us(void)
+{
+ void *regs = (void *) EARLY_HPET_BASE;
+ u32 period;
+ u64 d;
+
+ period = readl(regs + HPET_PERIOD_REG);
+ if (period == 0)
+ return 0;
+ if (period > HPET_MAX_PERIOD)
+ return 0;
+
+ d = timer_early_get_count();
+
+ /* overflow at 2^64 femtoseconds (more than 5 hours) */
+ d *= period;
+
+ return d / 1000000000;
+}
+
+#endif
+
+static int hpet_timer_ofdata_to_platdata(struct udevice *dev)
+{
+ struct hpet_timer_priv *priv = dev_get_priv(dev);
+ priv->regs = map_physmem(devfdt_get_addr(dev), 0x1000, MAP_NOCACHE);
+
+ return 0;
+}
+
+static const struct timer_ops hpet_timer_ops = {
+ .get_count = hpet_timer_get_count,
+};
+
+static const struct udevice_id hpet_timer_ids[] = {
+ { .compatible = "hpet-x86", },
+ { .compatible = "intel,ce4100-hpet", },
+ { }
+};
+
+U_BOOT_DRIVER(hpet_timer) = {
+ .name = "hpet_timer",
+ .id = UCLASS_TIMER,
+ .of_match = hpet_timer_ids,
+ .ofdata_to_platdata = hpet_timer_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct hpet_timer_priv),
+ .probe = hpet_timer_probe,
+ .ops = &hpet_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.7.4
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