[U-Boot] [PATCH v1 1/2] imx: board: Add support for the K+P's kp_imx6q_tpc board
Stefano Babic
sbabic at denx.de
Thu Mar 29 16:10:04 UTC 2018
Hi Lukasz,
On 14/03/2018 11:07, Lukasz Majewski wrote:
> This commit provides support for Kieback & Peter GmbH IMX6Q based
> TPC board.
>
Maybe you can add the U-Boot output (as done by other boards) to make
clear which peripherals are available.
> Signed-off-by: Lukasz Majewski <lukma at denx.de>
>
> ---
>
> arch/arm/mach-imx/mx6/Kconfig | 11 ++
> board/k+p/kp_imx6q_tpc/Kconfig | 12 ++
> board/k+p/kp_imx6q_tpc/MAINTAINERS | 6 +
> board/k+p/kp_imx6q_tpc/Makefile | 11 ++
> board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c | 302 ++++++++++++++++++++++++++++++
> board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c | 283 ++++++++++++++++++++++++++++
> configs/kp_imx6q_tpc_defconfig | 42 +++++
> include/configs/kp_imx6q_tpc.h | 128 +++++++++++++
> 8 files changed, 795 insertions(+)
> create mode 100644 board/k+p/kp_imx6q_tpc/Kconfig
> create mode 100644 board/k+p/kp_imx6q_tpc/MAINTAINERS
> create mode 100644 board/k+p/kp_imx6q_tpc/Makefile
> create mode 100644 board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
> create mode 100644 board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
> create mode 100644 configs/kp_imx6q_tpc_defconfig
> create mode 100644 include/configs/kp_imx6q_tpc.h
>
> diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
> index d4ce38db8d..aa6f5facbf 100644
> --- a/arch/arm/mach-imx/mx6/Kconfig
> +++ b/arch/arm/mach-imx/mx6/Kconfig
> @@ -387,6 +387,16 @@ config TARGET_TBS2910
> config TARGET_TITANIUM
> bool "titanium"
>
> +config TARGET_KP_IMX6Q_TPC
> + bool "K+P KP_IMX6Q_TPC i.MX6 Quad"
> + select MX6QDL
> + select BOARD_LATE_INIT
> + select BOARD_EARLY_INIT_F
> + select SUPPORT_SPL
> + select DM
> + select DM_THERMAL
> + imply CMD_SPL
> +
> config TARGET_TQMA6
> bool "TQ Systems TQMa6 board"
> select BOARD_LATE_INIT
> @@ -493,6 +503,7 @@ source "board/tbs/tbs2910/Kconfig"
> source "board/tqc/tqma6/Kconfig"
> source "board/toradex/apalis_imx6/Kconfig"
> source "board/toradex/colibri_imx6/Kconfig"
> +source "board/k+p/kp_imx6q_tpc/Kconfig"
> source "board/udoo/Kconfig"
> source "board/udoo/neo/Kconfig"
> source "board/wandboard/Kconfig"
> diff --git a/board/k+p/kp_imx6q_tpc/Kconfig b/board/k+p/kp_imx6q_tpc/Kconfig
> new file mode 100644
> index 0000000000..62e34978ec
> --- /dev/null
> +++ b/board/k+p/kp_imx6q_tpc/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_KP_IMX6Q_TPC
> +
> +config SYS_BOARD
> + default "kp_imx6q_tpc"
> +
> +config SYS_VENDOR
> + default "k+p"
> +
> +config SYS_CONFIG_NAME
> + default "kp_imx6q_tpc"
> +
> +endif
> diff --git a/board/k+p/kp_imx6q_tpc/MAINTAINERS b/board/k+p/kp_imx6q_tpc/MAINTAINERS
> new file mode 100644
> index 0000000000..6c4c8dd28e
> --- /dev/null
> +++ b/board/k+p/kp_imx6q_tpc/MAINTAINERS
> @@ -0,0 +1,6 @@
> +KP_IMX6Q_TPC BOARD
> +M: Lukasz Majewski <lukma at denx.de>
> +S: Maintained
> +F: board/k+p/kp_imx6q_tpc/
> +F: include/configs/kp_imx6q_tpc.h
> +F: configs/kp_imx6q_tpc_defconfig
> diff --git a/board/k+p/kp_imx6q_tpc/Makefile b/board/k+p/kp_imx6q_tpc/Makefile
> new file mode 100644
> index 0000000000..51cbd3e843
> --- /dev/null
> +++ b/board/k+p/kp_imx6q_tpc/Makefile
> @@ -0,0 +1,11 @@
> +#
> +# Copyright (C) 2018 Lukasz Majewski <lukma at denx.de>
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y := kp_imx6q_tpc_spl.o
> +else
> +obj-y := kp_imx6q_tpc.o
> +endif
> diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
> new file mode 100644
> index 0000000000..9a5b88029f
> --- /dev/null
> +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
> @@ -0,0 +1,302 @@
> +/*
> + * K+P iMX6Q KP_IMX6Q_TPC board configuration
> + *
> + * Copyright (C) 2018 Lukasz Majewski <lukma at denx.de>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/mx6-pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <asm/mach-imx/boot_mode.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <errno.h>
> +#include <fsl_esdhc.h>
> +#include <fuse.h>
> +#include <i2c.h>
> +#include <miiphy.h>
> +#include <mmc.h>
> +#include <net.h>
> +#include <netdev.h>
> +#include <usb.h>
> +#include <usb/ehci-ci.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define ENET_PAD_CTRL \
> + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> + PAD_CTL_HYS)
> +
> +#define I2C_PAD_CTRL \
> + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> + PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
> +
> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> +
> +static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info0 = {
> + .scl = {
> + .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL | PC,
> + .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
> + .gp = IMX_GPIO_NR(5, 27)
> + },
> + .sda = {
> + .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA | PC,
> + .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
> + .gp = IMX_GPIO_NR(5, 26)
> + }
> +};
> +
> +static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info1 = {
> + .scl = {
> + .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
> + .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
> + .gp = IMX_GPIO_NR(4, 12)
> + },
> + .sda = {
> + .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
> + .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
> + .gp = IMX_GPIO_NR(4, 13)
> + }
> +};
> +
> +int dram_init(void)
> +{
> + gd->ram_size = imx_ddr_size();
> + return 0;
> +}
> +
> +/*
> + * Do not overwrite the console
> + * Use always serial for U-Boot console
> + */
> +int overwrite_console(void)
> +{
> + return 1;
> +}
> +
> +#ifdef CONFIG_FEC_MXC
> +static iomux_v3_cfg_t const enet_pads[] = {
> + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
> + MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
> + MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + /* AR8031 PHY Reset */
> + IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> +};
> +
> +static void eth_phy_reset(void)
> +{
> + /* Reset AR8031 PHY */
> + gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
> + mdelay(10);
> + gpio_set_value(IMX_GPIO_NR(1, 25), 1);
> + udelay(100);
> +}
> +
> +static int setup_fec_clock(void)
> +{
> + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> +
> + /* set gpr1[21] to select anatop clock */
> + clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
> +
> + return enable_fec_anatop_clock(0, ENET_50MHZ);
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + SETUP_IOMUX_PADS(enet_pads);
> + setup_fec_clock();
> + eth_phy_reset();
> +
> + return cpu_eth_init(bis);
> +}
> +
> +static int ar8031_phy_fixup(struct phy_device *phydev)
> +{
> + unsigned short val;
> +
> + /* To enable AR8031 output a 125MHz clk from CLK_25M */
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
> +
> + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
> + val &= 0xffe3;
> + val |= 0x18;
> + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
> +
> + /* introduce tx clock delay */
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
> + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
> + val |= 0x0100;
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
> +
> + return 0;
> +}
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> + ar8031_phy_fixup(phydev);
> +
> + if (phydev->drv->config)
> + phydev->drv->config(phydev);
> +
> + return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_FSL_ESDHC
> +
> +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
> +static struct fsl_esdhc_cfg usdhc_cfg[] = {
> + { USDHC2_BASE_ADDR },
> + { USDHC4_BASE_ADDR },
> +};
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> +
> + switch (cfg->esdhc_base) {
> + case USDHC2_BASE_ADDR:
> + return !gpio_get_value(USDHC2_CD_GPIO);
> + case USDHC4_BASE_ADDR:
> + return 1; /* eMMC/uSDHC4 is always present */
> + }
> +
> + return 0;
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + int i, ret;
> +
> + /*
> + * According to the board_mmc_init() the following map is done:
> + * (U-Boot device node) (Physical Port)
> + * mmc0 micro SD
> + * mmc2 eMMC
> + */
> + gpio_direction_input(USDHC2_CD_GPIO);
> +
> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
> +
> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_USB_EHCI_MX6
> +static void setup_usb(void)
> +{
> + /*
> + * Set daisy chain for otg_pin_id on MX6Q.
> + * For MX6DL, this bit is reserved.
> + */
> + imx_iomux_set_gpr_register(1, 13, 1, 0);
> +}
> +
> +int board_usb_phy_mode(int port)
> +{
> + if (port == 1)
> + return USB_INIT_HOST;
> + else
> + return USB_INIT_DEVICE;
> +}
> +
> +int board_ehci_power(int port, int on)
> +{
> + switch (port) {
> + case 0:
> + break;
> + case 1:
> + gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
> + break;
> + default:
> + printf("MXC USB port %d not yet supported\n", port);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +#endif
> +
> +int board_early_init_f(void)
> +{
> +#ifdef CONFIG_USB_EHCI_MX6
> + setup_usb();
> +#endif
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> + /* Enable eim_slow clocks */
> + setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
> +
> + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info0);
> + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info1);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_CMD_BMODE
> +static const struct boot_mode board_boot_modes[] = {
> + /* 4 bit bus width */
> + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
> + /* 8 bit bus width */
> + {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
> + {NULL, 0},
> +};
> +#endif
> +
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_CMD_BMODE
> + add_board_boot_modes(board_boot_modes);
> +#endif
> +
> + env_set("boardname", "kp-tpc");
> + env_set("boardsoc", "imx6q");
> + return 0;
> +}
> +
> +int checkboard(void)
> +{
> + puts("Board: K+P KP_IMX6Q_TPC i.MX6Q\n");
> + return 0;
> +}
> diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
> new file mode 100644
> index 0000000000..b5723b41c1
> --- /dev/null
> +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
> @@ -0,0 +1,283 @@
> +/*
> + * K+P iMX6Q KP_IMX6Q_TPC board configuration
> + *
> + * Copyright (C) 2018 Lukasz Majewski <lukma at denx.de>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/mx6-ddr.h>
> +#include <asm/arch/mx6-pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/gpio.h>
> +#include <asm/mach-imx/boot_mode.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <asm/io.h>
> +#include <errno.h>
> +#include <fuse.h>
> +#include <fsl_esdhc.h>
> +#include <i2c.h>
> +#include <mmc.h>
> +#include <spl.h>
> +
> +#define UART_PAD_CTRL \
> + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +#define USDHC_PAD_CTRL \
> + (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
> + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static void ccgr_init(void)
> +{
> + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +
> + writel(0x00C03F3F, &ccm->CCGR0);
> + writel(0x0030FC03, &ccm->CCGR1);
> + writel(0x0FFFC000, &ccm->CCGR2);
> + writel(0x3FF00000, &ccm->CCGR3);
> + writel(0x00FFF300, &ccm->CCGR4);
> + writel(0x0F0000C3, &ccm->CCGR5);
> + writel(0x000003FF, &ccm->CCGR6);
> +}
> +
> +/* onboard microSD */
> +static iomux_v3_cfg_t const usdhc2_pads[] = {
> + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> +};
> +
> +/* eMMC */
> +static iomux_v3_cfg_t const usdhc4_pads[] = {
> + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> +};
> +
> +/* SD */
> +static void setup_iomux_sd(void)
> +{
> + SETUP_IOMUX_PADS(usdhc2_pads);
> + SETUP_IOMUX_PADS(usdhc4_pads);
> +}
> +
> +/* UART */
> +static iomux_v3_cfg_t const uart1_pads[] = {
> + IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
> +};
> +
> +static void setup_iomux_uart(void)
> +{
> + SETUP_IOMUX_PADS(uart1_pads);
> +}
> +
> +/* USB */
> +static iomux_v3_cfg_t const usb_pads[] = {
> + IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> +};
> +
> +static void setup_iomux_usb(void)
> +{
> + SETUP_IOMUX_PADS(usb_pads);
> +}
> +
> +/*
> + * This code has been extracted from mx6q_8x_mt41K256.cfg DCD
> + * NXP's BSP u-boot mx6q_8x_mt41K256.cfg rel_imx_4.1.15_2.1.0_ga
> + */
> +static int mx6q_dcd_table[] = {
> + 0x020e0798, 0x000C0000,
> + 0x020e0758, 0x00000000,
Well.....
This is a Quad, well supported, we have a nice framework to setup the
DDR. I do not like to see this dump of table in code. Which is the added
value compared to the DCD table using the i.MX header ?
> + 0x020e0588, 0x00000030,
> + 0x020e0594, 0x00000030,
> + 0x020e056c, 0x00000030,
> + 0x020e0578, 0x00000030,
> + 0x020e074c, 0x00000030,
> + 0x020e057c, 0x00000030,
> + 0x020e058c, 0x00000000,
> + 0x020e059c, 0x00000030,
> + 0x020e05a0, 0x00000030,
> + 0x020e078c, 0x00000030,
There are structure and function to set these.
> + 0x020e0750, 0x00020000,
> + 0x020e05a8, 0x00000018,
> + 0x020e05b0, 0x00000018,
> + 0x020e0524, 0x00000018,
> + 0x020e051c, 0x00000018,
> + 0x020e0518, 0x00000018,
> + 0x020e050c, 0x00000018,
> + 0x020e05b8, 0x00000018,
> + 0x020e05c0, 0x00000018,
> + 0x020e0774, 0x00020000,
> + 0x020e0784, 0x00000018,
> + 0x020e0788, 0x00000018,
> + 0x020e0794, 0x00000018,
> + 0x020e079c, 0x00000018,
> + 0x020e07a0, 0x00000018,
> + 0x020e07a4, 0x00000018,
> + 0x020e07a8, 0x00000018,
> + 0x020e0748, 0x00000018,
> + 0x020e05ac, 0x00000018,
> + 0x020e05b4, 0x00000018,
> + 0x020e0528, 0x00000018,
> + 0x020e0520, 0x00000018,
> + 0x020e0514, 0x00000018,
> + 0x020e0510, 0x00000018,
> + 0x020e05bc, 0x00000018,
> + 0x020e05c4, 0x00000018,
> + 0x021b0800, 0xa1390003,
> + 0x021b080c, 0x001F001F,
> + 0x021b0810, 0x001F001F,
> + 0x021b480c, 0x001F001F,
> + 0x021b4810, 0x001F001F,
> + 0x021b083c, 0x43270338,
> + 0x021b0840, 0x03200314,
> + 0x021b483c, 0x431A032F,
> + 0x021b4840, 0x03200263,
> + 0x021b0848, 0x4B434748,
> + 0x021b4848, 0x4445404C,
> + 0x021b0850, 0x38444542,
> + 0x021b4850, 0x4935493A,
> + 0x021b081c, 0x33333333,
> + 0x021b0820, 0x33333333,
> + 0x021b0824, 0x33333333,
> + 0x021b0828, 0x33333333,
> + 0x021b481c, 0x33333333,
> + 0x021b4820, 0x33333333,
> + 0x021b4824, 0x33333333,
> + 0x021b4828, 0x33333333,
Like calibration and so on. Please change this as done by other board,
using structures ( mx6_ddr3_cfg, mx6dq_iomux_grp_regs) and calling
mx6dq_dram_iocfg() and mx6_dram_cfg() - thanks !
> + 0x021b08b8, 0x00000800,
> + 0x021b48b8, 0x00000800,
> + 0x021b0004, 0x00020036,
> + 0x021b0008, 0x09444040,
> + 0x021b000c, 0x8A8F7955,
> + 0x021b0010, 0xFF328F64,
> + 0x021b0014, 0x01FF00DB,
> + 0x021b0018, 0x00001740,
> + 0x021b001c, 0x00008000,
> + 0x021b002c, 0x000026d2,
> + 0x021b0030, 0x008F1023,
> + 0x021b0040, 0x00000047,
> + 0x021b0000, 0x841A0000,
> + 0x021b001c, 0x04088032,
> + 0x021b001c, 0x00008033,
> + 0x021b001c, 0x00048031,
> + 0x021b001c, 0x09408030,
> + 0x021b001c, 0x04008040,
> + 0x021b0020, 0x00005800,
> + 0x021b0818, 0x00011117,
> + 0x021b4818, 0x00011117,
> + 0x021b0004, 0x00025576,
> + 0x021b0404, 0x00011006,
> + 0x021b001c, 0x00000000,
> +};
> +
> +static void ddr_init(int *table, int size)
> +{
> + int i;
> +
> + for (i = 0; i < size / 2 ; i++)
> + writel(table[2 * i + 1], table[2 * i]);
Quite nasty....
> +}
> +
> +struct fsl_esdhc_cfg usdhc_cfg[] = {
> + {USDHC2_BASE_ADDR},
> + {USDHC4_BASE_ADDR},
> +};
> +
> +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> + int ret = 0;
> +
> + switch (cfg->esdhc_base) {
> + case USDHC2_BASE_ADDR:
> + ret = !gpio_get_value(USDHC2_CD_GPIO);
> + break;
> + case USDHC4_BASE_ADDR:
> + ret = 1; /* eMMC/uSDHC4 is always present */
> + break;
> + }
> +
> + return ret;
> +}
> +
> +int board_mmc_init(bd_t *bd)
> +{
> + struct src *psrc = (struct src *)SRC_BASE_ADDR;
> + unsigned int reg = readl(&psrc->sbmr1) >> 11;
> + /*
> + * Upon reading BOOT_CFG register the following map is done:
> + * Bit 11 and 12 of BOOT_CFG register can determine the current
> + * mmc port
> + * 0x1 SD1
> + * 0x3 SD4
> + */
> +
> + switch (reg & 0x3) {
> + case 0x1:
> + SETUP_IOMUX_PADS(usdhc2_pads);
> + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
> + break;
> + case 0x3:
> + SETUP_IOMUX_PADS(usdhc4_pads);
> + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
> + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
> + break;
> + }
> +
> + return fsl_esdhc_initialize(bd, &usdhc_cfg[0]);
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> + /* Setup DDR3 from NXP's BSP DCD file */
> + ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
> +
> + /* setup AIPS and disable watchdog */
> + arch_cpu_init();
> +
> + ccgr_init();
> + gpr_init();
> +
> + /* setup GP timer */
> + timer_init();
> +
> + setup_iomux_sd();
> + setup_iomux_uart();
> + setup_iomux_usb();
> +
> + /* UART clocks enabled and gd valid - init serial console */
> + preloader_console_init();
> +
> + /* Clear the BSS. */
> + memset(__bss_start, 0, __bss_end - __bss_start);
> +
> + /* load/boot image from boot device */
> + board_init_r(NULL, 0);
> +}
> diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig
> new file mode 100644
> index 0000000000..d2c6e2e6ba
> --- /dev/null
> +++ b/configs/kp_imx6q_tpc_defconfig
> @@ -0,0 +1,42 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MX6=y
> +CONFIG_SYS_TEXT_BASE=0x17800000
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_MX6_DDRCAL=y
> +CONFIG_TARGET_KP_IMX6Q_TPC=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL_WATCHDOG_SUPPORT=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_FIT=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
> +CONFIG_BOOTDELAY=3
> +# CONFIG_USE_BOOTCOMMAND is not set
> +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
> +CONFIG_SPL=y
> +CONFIG_SPL_RAW_IMAGE_SUPPORT=y
> +CONFIG_AUTOBOOT_KEYED=y
> +CONFIG_AUTOBOOT_STOP_STR="."
> +# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
> +# CONFIG_CMD_ELF is not set
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_EXT4_WRITE=y
> +# CONFIG_ISO_PARTITION is not set
> +# CONFIG_EFI_PARTITION is not set
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_ATHEROS=y
> +CONFIG_NETDEVICES=y
> +CONFIG_FEC_MXC=y
> +CONFIG_IMX_THERMAL=y
> +CONFIG_USB=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_OF_LIBFDT=y
> diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
> new file mode 100644
> index 0000000000..74143a2dba
> --- /dev/null
> +++ b/include/configs/kp_imx6q_tpc.h
> @@ -0,0 +1,128 @@
> +/*
> + * K+P iMX6Q KP_IMX6Q_TPC board configuration
> + *
> + * Copyright (C) 2018 Lukasz Majewski <lukma at denx.de>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __KP_IMX6Q_TPC_IMX6_CONFIG_H_
> +#define __KP_IMX6Q_TPC_IMX6_CONFIG_H_
> +
> +#include <asm/arch/imx-regs.h>
> +
> +#include "mx6_common.h"
> +
> +/* SPL */
> +#include "imx6_spl.h" /* common IMX6 SPL configuration */
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_REVISION_TAG
> +
> +#define CONFIG_BOUNCE_BUFFER
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
> +
> +/* FEC ethernet */
> +#define CONFIG_MII
> +#define IMX_FEC_BASE ENET_BASE_ADDR
> +#define CONFIG_FEC_XCV_TYPE RGMII
> +#define CONFIG_ETHPRIME "FEC"
> +#define CONFIG_FEC_MXC_PHYADDR 0
> +#define CONFIG_ARP_TIMEOUT 200UL
> +
> +/* Fuses */
> +#ifdef CONFIG_CMD_FUSE
> +#define CONFIG_MXC_OCOTP
> +#endif
> +
> +/* I2C Configs */
> +#define CONFIG_SYS_I2C
> +#define CONFIG_SYS_I2C_MXC
> +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
> +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
> +#define CONFIG_SYS_I2C_SPEED 100000
> +
> +/* MMC Configs */
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_FSL_USDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +#define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */
> +
> +/* UART */
> +#define CONFIG_MXC_UART
> +#define CONFIG_MXC_UART_BASE UART1_BASE
> +#define CONFIG_CONS_INDEX 1
> +#define CONFIG_BAUDRATE 115200
> +
> +/* USB Configs */
> +#ifdef CONFIG_CMD_USB
> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> +#define CONFIG_USB_HOST_ETHER
> +#define CONFIG_USB_ETHER_ASIX
> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
> +#define CONFIG_MXC_USB_FLAGS 0
> +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
> +#endif
> +
> +/* Watchdog */
> +#define CONFIG_HW_WATCHDOG
> +#define CONFIG_IMX_WATCHDOG
> +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +
> +#define CONFIG_LOADADDR 0x12000000
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#ifndef CONFIG_SPL_BUILD
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "console=ttymxc0,115200\0" \
> + "fdt_addr=0x18000000\0" \
> + "fdt_high=0xffffffff\0" \
> + "initrd_high=0xffffffff\0" \
> + "kernel_addr_r=0x10008000\0" \
> + "fdt_addr_r=0x13000000\0" \
> + "ramdisk_addr_r=0x18000000\0" \
> + "scriptaddr=0x14000000\0" \
> + "kernel_file=fitImage\0"\
> + BOOTENV
> +
> +#define CONFIG_BOOTCOMMAND "run distro_bootcmd"
> +
> +#define BOOT_TARGET_DEVICES(func) \
> + func(MMC, mmc, 0) \
> + func(MMC, mmc, 1) \
> + func(USB, usb, 0) \
> + func(DHCP, dhcp, na)
> +
> +#include <config_distro_bootcmd.h>
> +#endif
> +
> +/* Physical Memory Map */
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
> +
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* Environment */
> +#define CONFIG_ENV_SIZE (SZ_8K)
> +#define CONFIG_ENV_OFFSET 0x100000
> +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
> +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
> +
> +#endif /* __KP_IMX6Q_TPC_IMX6_CONFIG_H_ */
>
Best regards,
Stefano Babic
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
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