[U-Boot] [PATCH 1/7] drivers: Add AXI uclass and ihs_axi driver
Simon Glass
sjg at chromium.org
Fri Mar 30 08:41:31 UTC 2018
Hi Mario,
On 28 March 2018 at 20:40, Mario Six <mario.six at gdsys.cc> wrote:
> Add a uclass for AXI (Advanced eXtensible Interface) busses, and a
> driver for the gdsys IHS AXI bus on IHS FPGAs.
>
> Signed-off-by: Mario Six <mario.six at gdsys.cc>
> ---
> drivers/Kconfig | 2 +
> drivers/Makefile | 1 +
> drivers/axi/Kconfig | 24 ++++++
> drivers/axi/Makefile | 9 +++
> drivers/axi/axi-uclass.c | 40 ++++++++++
> drivers/axi/ihs_axi.c | 199 +++++++++++++++++++++++++++++++++++++++++++++++
> include/axi.h | 75 ++++++++++++++++++
> include/dm/uclass-id.h | 1 +
> 8 files changed, 351 insertions(+)
> create mode 100644 drivers/axi/Kconfig
> create mode 100644 drivers/axi/Makefile
> create mode 100644 drivers/axi/axi-uclass.c
> create mode 100644 drivers/axi/ihs_axi.c
> create mode 100644 include/axi.h
Would UCLASS_MAILBOX be suitable here?
It's fine if you want a new uclass, just checking.
Please split out your driver into a separate patch. Adding the new
uclass should be in its own patch.
>
> diff --git a/drivers/Kconfig b/drivers/Kconfig
> index c2e813f5ad..eeaaa7575c 100644
> --- a/drivers/Kconfig
> +++ b/drivers/Kconfig
> @@ -8,6 +8,8 @@ source "drivers/adc/Kconfig"
>
> source "drivers/ata/Kconfig"
>
> +source "drivers/axi/Kconfig"
> +
> source "drivers/block/Kconfig"
>
> source "drivers/bootcount/Kconfig"
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 6846d181aa..f54a10f3ad 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -100,6 +100,7 @@ obj-y += input/
> obj-y += soc/
> obj-$(CONFIG_REMOTEPROC) += remoteproc/
> obj-y += thermal/
> +obj-y += axi/
>
> obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
> endif
> diff --git a/drivers/axi/Kconfig b/drivers/axi/Kconfig
> new file mode 100644
> index 0000000000..19e1b7fd2f
> --- /dev/null
> +++ b/drivers/axi/Kconfig
> @@ -0,0 +1,24 @@
> +menuconfig AXI
> + bool "AXI bus drivers"
> + help
> + Support AXI (Advanced eXtensible Interface) busses, a on-chip
> + interconnect specification for managing functional blocks in SoC
> + designs, which is also often used in designs involving FPGAs (e.g.
> + communication with IP cores in Xilinx FPGAs).
> +
> + These types of busses expose a virtual address space that can be
> + accessed using different address widths (8, 16, and 32 are supported
> + for now).
> +
> + Other similar bus architectures may be compatible as well.
> +
> +if AXI
> +
> +config IHS_AXI
> + bool "Enable IHS AXI driver"
> + depends on DM
> + help
> + Support for IHS AXI bus on a gdsys IHS FPGA used to communicate with
> + IP cores in the FPGA (e.g. video transmitter cores).
Please also spell out the abbreviations in the help
[...]
Regards,
Simon
More information about the U-Boot
mailing list