[U-Boot] [PATCH v1 08/16] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

[Ley Foon Tan]

On Fri, May 11, 2018 at 4:44 PM, Marek Vasut <marex at denx.de> wrote:
> On 05/11/2018 07:45 AM, Ley Foon Tan wrote:
>> On Thu, May 10, 2018 at 6:09 PM, Marek Vasut <marex at denx.de> wrote:
>>> On 05/10/2018 10:45 AM, Ley Foon Tan wrote:
>>>> On Tue, May 8, 2018 at 5:21 PM, Marek Vasut <marex at denx.de> wrote:
>>>>> On 05/08/2018 08:49 AM, Ley Foon Tan wrote:
>>>>>> On Thu, Apr 19, 2018 at 10:53 AM, Marek Vasut <marex at denx.de> wrote:
>>>>>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>>>>> Add mailbox support for Stratix SoC
>>>>>>>>
>>>>>>>> Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
>>>>>>>> Signed-off-by: Chin Liang See <chin.liang.see at intel.com>
>>>>>>>> ---
>>>>>
>>>>> [...]
>>>>>
>>>>>>>> +static __always_inline int mbox_polling_resp(u32 rout)
>>>>>>>> +{
>>>>>>>> +     static const struct socfpga_mailbox *mbox_base =
>>>>>>>> +                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
>>>>>>>> +     u32 rin;
>>>>>>>> +     unsigned long i = ~0;
>>>>>>>> +
>>>>>>>> +     while (i) {
>>>>>>>> +             rin = readl(&mbox_base->rin);
>>>>>>>> +             if (rout != rin)
>>>>>>>> +                     return 0;
>>>>>>>
>>>>>>> This looks like include/wait_bit.h reimplementation
>>>>>> The reason we use this method instead of using wait_bit because this
>>>>>> function will use in Secure Monitor Call (SMC) call as well.
>>>>>> When run in secure section, timer is not available.  So, we can't use
>>>>>> wait_for_bit.
>>>>>
>>>>> Can't you just do timer_init() then ?
>>>> We can't use timer in secure region. This SMC code is resident in
>>>> onchip memory (secure region) while Linux is running.
>>>> So, timer might be used by Linux.
>>>
>>> So pieces of U-Boot remain in memory and get called by Linux, right ?
>> Normal U-boot (in DDR) is destroyed after Linux is running, only SMC
>> code Onchip memory will remain.
>> The existing U-boot have support this SMC feature, platform just need
>> to configure the CONFIG_ARMV8_SECURE_BASE for the secure section.
>> Of course, we need to enable CONFIG_ARMV8_PSCI too.
>
> So piece of U-Boot then becomes the part which handles PSCI calls from
> Linux, do I understand it correctly ?
Yes, and we put this piece of code in onchip memory in our platform so
it doesn't corrupted by Linux.

You can see detail in
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv8/u-boot.lds
All code related to PSCI/SMC will put in secure section.

>
>>> I am CCing a few more people , since this might need further discussion.
>>>
>>> btw does this work when Linux is compiled in AArch32 mode while U-Boot
>>> is AArch64 ? I think it might not.
>> It should work. PSCI handle checks ESR_EL3.EC field to know whether it
>> is SMC32 or SMC64.
>> See code in handle_sync near line 230 in
>> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv8/psci.S
> Will do, thanks!
>
> --

Regards
Ley Foon