[U-Boot] [PATCH 40/41] dts: imx8qxp: Add DTS and binding header files
Peng Fan
peng.fan at nxp.com
Mon May 28 12:25:25 UTC 2018
Introduce dtsi file for i.MX8QXP.
Signed-off-by: Peng Fan <peng.fan at nxp.com>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/fsl-imx8qxp-mek.dts | 416 ++++++++
arch/arm/dts/fsl-imx8qxp.dtsi | 1593 +++++++++++++++++++++++++++++
include/dt-bindings/clock/imx8qxp-clock.h | 533 ++++++++++
include/dt-bindings/soc/imx8_pd.h | 197 ++++
5 files changed, 2741 insertions(+)
create mode 100644 arch/arm/dts/fsl-imx8qxp-mek.dts
create mode 100644 arch/arm/dts/fsl-imx8qxp.dtsi
create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h
create mode 100644 include/dt-bindings/soc/imx8_pd.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a0349a8975..da9cdeef1e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -432,6 +432,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
+dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
+
dtb-$(CONFIG_RCAR_GEN3) += \
r8a7795-h3ulcb.dtb \
r8a7795-salvator-x.dtb \
diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts
new file mode 100644
index 0000000000..55960d0a67
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-mek.dts
@@ -0,0 +1,416 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/* Last 127M is for M4/RPMSG */
+/memreserve/ 0x80000000 0x08000000;
+
+#include "fsl-imx8qxp.dtsi"
+
+/ {
+ model = "Freescale i.MX8QXP MEK";
+ compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
+
+ aliases {
+ i2c4 = &bb_i2c1;
+ i2c5 = &mfi_i2c1;
+ i2c6 = &i2cexp1_i2c1;
+ i2c7 = &i2cexp2_i2c1;
+ };
+
+ chosen {
+ bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
+ stdout-path = &lpuart0;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usdhc2_vmmc: usdhc2_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "SD1_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ };
+
+ reg_usb_otg1_vbus: regulator at 0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ imx8qxp-mek {
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
+ SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048
+ SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048
+ SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048
+ SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048
+ SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048
+ SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048
+ SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048
+ SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048
+ SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048
+ SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048
+ SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048
+ SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048
+ SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048
+ SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048
+ >;
+ };
+
+ pinctrl_fec2: fec2grp {
+ fsl,pins = <
+ SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000048
+ SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000048
+ SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000048
+ SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000048
+ SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000048
+ SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000048
+ SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000048
+ SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000048
+ SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000048
+ SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000048
+ SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000048
+ SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000048
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi1cgrp {
+ fsl,pins = <
+ SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000020
+ SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000020
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x06000021
+ SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x06000021
+ SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000021
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000021
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000021
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000021
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000021
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000021
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000020
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000020
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000020
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000020
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000020
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000020
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000020
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000020
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000020
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000020
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000020
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000020
+ >;
+ };
+
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c
+ SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c
+ SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c
+ SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c
+ SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c
+ SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c
+ SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c
+ SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c
+ SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c
+ SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c
+ SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c
+ SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c
+ SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c
+ SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c
+ SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c
+ SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c
+ >;
+ };
+
+ pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp {
+ fsl,pins = <
+ SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
+ SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020
+ >;
+ };
+
+ pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp {
+ fsl,pins = <
+ SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020
+ SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020
+ >;
+ };
+ };
+};
+
+&lpuart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart0>;
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy0>;
+ fsl,ar8031-phy-fixup;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy at 0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy at 1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec2>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy1>;
+ fsl,ar8031-phy-fixup;
+ fsl,magic-packet;
+ status = "okay";
+};
+
+&flexspi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ status = "okay";
+
+ flash0: mt35xu512aba at 0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <29000000>;
+ spi-nor,ddr-quad-read-dummy = <8>;
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ status = "okay";
+
+ pca9646_switch: mux at 71 {
+ compatible = "nxp,pca9646";
+ reg = <0x71>;
+ u-boot,i2c-offset-len = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bb_i2c1: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+ };
+
+ mfi_i2c1: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+ };
+
+ i2cexp1_i2c1: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ };
+
+ i2cexp2_i2c1: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ pca9557_a: gpio at 1a {
+ compatible = "nxp,pca9557";
+ reg = <0x1a>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pca9557_b: gpio at 1d {
+ compatible = "nxp,pca9557";
+ reg = <0x1d>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+ };
+};
+
+&i2c0_mipi_lvds0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c0_mipi_lvds1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-imx8qxp.dtsi b/arch/arm/dts/fsl-imx8qxp.dtsi
new file mode 100644
index 0000000000..b2c7168127
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp.dtsi
@@ -0,0 +1,1593 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/imx_rsrc.h>
+#include <dt-bindings/soc/imx8_pd.h>
+#include <dt-bindings/clock/imx8qxp-clock.h>
+#include <dt-bindings/pinctrl/pads-imx8qxp.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "fsl,imx8qxp";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &fec1;
+ ethernet1 = &fec2;
+ serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial2 = &lpuart2;
+ serial3 = &lpuart3;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ gpio5 = &gpio5;
+ gpio6 = &gpio6;
+ gpio7 = &gpio7;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c13 = &i2c0_mipi_lvds0;
+ i2c15 = &i2c0_mipi_lvds1;
+ spi0 = &flexspi0;
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x40000000>;
+ /* DRAM space - 1, size : 1 GB DRAM */
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x28000000>;
+ alloc-ranges = <0 0x80000000 0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
+ gic: interrupt-controller at 51a00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+ <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ mu: mu at 5d1b0000 {
+ compatible = "fsl,imx8-mu";
+ reg = <0x0 0x5d1b0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,scu_ap_mu_id = <0>;
+ #mbox-cells = <4>;
+ status = "okay";
+ };
+
+ mu13: mu13 at 5d280000 {
+ compatible = "fsl,imx8-mu-hifi";
+ reg = <0x0 0x5d280000 0x0 0x10000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,hifi_ap_mu_id = <13>;
+ status = "okay";
+ };
+
+ clk: clk {
+ compatible = "fsl,imx8qxp-clk";
+ #clock-cells = <1>;
+ };
+
+ iomuxc: iomuxc {
+ compatible = "fsl,imx8qxp-iomuxc";
+ };
+
+ rtc: rtc {
+ compatible = "fsl,imx-sc-rtc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+ clock-frequency = <8000000>;
+ };
+
+ imx8qx-pm {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_lsio: PD_LSIO {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_LAST>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_lsio_pwm0: PD_LSIO_PWM_0 {
+ reg = <SC_R_PWM_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_pwm1: PD_LSIO_PWM_1 {
+ reg = <SC_R_PWM_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_pwm2: PD_LSIO_PWM_2 {
+ reg = <SC_R_PWM_2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_pwm3: PD_LSIO_PWM_3 {
+ reg = <SC_R_PWM_3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_pwm4: PD_LSIO_PWM_4 {
+ reg = <SC_R_PWM_4>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_pwm5: PD_LSIO_PWM_5 {
+ reg = <SC_R_PWM_5>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_pwm6: PD_LSIO_PWM_6 {
+ reg = <SC_R_PWM_6>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_pwm7: PD_LSIO_PWM_7 {
+ reg = <SC_R_PWM_7>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_kpp: PD_LSIO_KPP {
+ reg = <SC_R_KPP>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpio0: PD_LSIO_GPIO_0 {
+ reg = <SC_R_GPIO_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpio1: PD_LSIO_GPIO_1 {
+ reg = <SC_R_GPIO_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpio2: PD_LSIO_GPIO_2 {
+ reg = <SC_R_GPIO_2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpio3: PD_LSIO_GPIO_3 {
+ reg = <SC_R_GPIO_3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpio4: PD_LSIO_GPIO_4 {
+ reg = <SC_R_GPIO_4>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpio5: PD_LSIO_GPIO_5{
+ reg = <SC_R_GPIO_5>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpio6:PD_LSIO_GPIO_6 {
+ reg = <SC_R_GPIO_6>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpio7: PD_LSIO_GPIO_7 {
+ reg = <SC_R_GPIO_7>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpt0: PD_LSIO_GPT_0 {
+ reg = <SC_R_GPT_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpt1: PD_LSIO_GPT_1 {
+ reg = <SC_R_GPT_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpt2: PD_LSIO_GPT_2 {
+ reg = <SC_R_GPT_2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpt3: PD_LSIO_GPT_3 {
+ reg = <SC_R_GPT_3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpt4: PD_LSIO_GPT_4 {
+ reg = <SC_R_GPT_4>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_flexspi0: PD_LSIO_FSPI_0 {
+ reg = <SC_R_FSPI_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_flexspi1: PD_LSIO_FSPI_1{
+ reg = <SC_R_FSPI_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ };
+
+ pd_conn: PD_CONN {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_LAST>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_conn_usbotg0: PD_CONN_USB_0 {
+ reg = <SC_R_USB_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ };
+ pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY {
+ reg = <SC_R_USB_0_PHY>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ };
+ pd_conn_usbotg1: PD_CONN_USB_1 {
+ reg = <SC_R_USB_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ };
+ pd_conn_usb2: PD_CONN_USB_2 {
+ reg = <SC_R_USB_2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ };
+ pd_conn_usb2_phy: PD_CONN_USB_2_PHY {
+ reg = <SC_R_USB_2_PHY>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ };
+ pd_conn_sdch0: PD_CONN_SDHC_0 {
+ reg = <SC_R_SDHC_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ };
+ pd_conn_sdch1: PD_CONN_SDHC_1 {
+ reg = <SC_R_SDHC_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ };
+ pd_conn_sdch2: PD_CONN_SDHC_2 {
+ reg = <SC_R_SDHC_2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ };
+ pd_conn_enet0: PD_CONN_ENET_0 {
+ reg = <SC_R_ENET_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ };
+ pd_conn_enet1: PD_CONN_ENET_1 {
+ reg = <SC_R_ENET_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ };
+ pd_conn_nand: PD_CONN_NAND {
+ reg = <SC_R_NAND>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ };
+ pd_conn_mlb0: PD_CONN_MLB_0 {
+ reg = <SC_R_MLB_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ };
+ pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 {
+ reg = <SC_R_DMA_4_CH0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_conn>;
+ };
+ pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 {
+ reg = <SC_R_DMA_4_CH1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_conn>;
+ };
+ pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 {
+ reg = <SC_R_DMA_4_CH2>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_conn>;
+ };
+ pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 {
+ reg = <SC_R_DMA_4_CH3>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_conn>;
+ };
+ pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 {
+ reg = <SC_R_DMA_4_CH4>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_conn>;
+ };
+ };
+
+ pd_audio: PD_AUDIO {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_LAST>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_asrc0:PD_AUD_ASRC_0 {
+ reg = <SC_R_ASRC_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_asrc1: PD_AUD_ASRC_1 {
+ reg = <SC_R_ASRC_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_esai0: PD_AUD_ESAI_0 {
+ reg = <SC_R_ESAI_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_spdif0: PD_AUD_SPDIF_0 {
+ reg = <SC_R_SPDIF_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_sai0:PD_AUD_SAI_0 {
+ reg = <SC_R_SAI_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_sai1: PD_AUD_SAI_1 {
+ reg = <SC_R_SAI_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_sai2: PD_AUD_SAI_2 {
+ reg = <SC_R_SAI_2>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_sai3: PD_AUD_SAI_3 {
+ reg = <SC_R_SAI_3>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_sai4: PD_AUD_SAI_4 {
+ reg = <SC_R_SAI_4>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_sai5: PD_AUD_SAI_5 {
+ reg = <SC_R_SAI_5>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_gpt5: PD_AUD_GPT_5 {
+ reg = <SC_R_GPT_5>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_gpt6: PD_AUD_GPT_6 {
+ reg = <SC_R_GPT_6>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_gpt7: PD_AUD_GPT_7 {
+ reg = <SC_R_GPT_7>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_gpt8: PD_AUD_GPT_8 {
+ reg = <SC_R_GPT_8>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_gpt9: PD_AUD_GPT_9 {
+ reg = <SC_R_GPT_9>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_gpt10: PD_AUD_GPT_10 {
+ reg = <SC_R_GPT_10>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_amix: PD_AUD_AMIX {
+ reg = <SC_R_AMIX>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_mqs0: PD_AUD_MQS_0 {
+ reg = <SC_R_MQS_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_hifi: PD_AUD_HIFI {
+ reg = <SC_R_DSP>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_hifi_ram: PD_AUD_OCRAM {
+ reg = <SC_R_DSP_RAM>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_mclk_out0: PD_AUD_MCLK_OUT_0 {
+ reg = <SC_R_MCLK_OUT_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_mclk_out1: PD_AUD_MCLK_OUT_1 {
+ reg = <SC_R_MCLK_OUT_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_audio_pll0: PD_AUD_AUDIO_PLL_0 {
+ reg = <SC_R_AUDIO_PLL_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_audio_pll1: PD_AUD_AUDIO_PLL_1 {
+ reg = <SC_R_AUDIO_PLL_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_audio_clk0: PD_AUD_AUDIO_CLK_0 {
+ reg = <SC_R_AUDIO_CLK_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_audio_clk1: PD_AUD_AUDIO_CLK_1 {
+ reg = <SC_R_AUDIO_CLK_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ };
+
+ pd_dma: PD_DMA {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_LAST>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_dma_flexcan0: PD_DMA_CAN_0 {
+ reg = <SC_R_CAN_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_flexcan1: PD_DMA_CAN_1 {
+ reg = <SC_R_CAN_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_flexcan2: PD_DMA_CAN_2 {
+ reg = <SC_R_CAN_2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_ftm0: PD_DMA_FTM_0 {
+ reg = <SC_R_FTM_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_ftm1: PD_DMA_FTM_1 {
+ reg = <SC_R_FTM_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_adc0: PD_DMA_ADC_0 {
+ reg = <SC_R_ADC_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpi2c0: PD_DMA_I2C_0 {
+ reg = <SC_R_I2C_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpi2c1: PD_DMA_I2C_1 {
+ reg = <SC_R_I2C_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpi2c2:PD_DMA_I2C_2 {
+ reg = <SC_R_I2C_2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpi2c3: PD_DMA_I2C_3 {
+ reg = <SC_R_I2C_3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpuart0: PD_DMA_UART0 {
+ reg = <SC_R_UART_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpuart1: PD_DMA_UART1 {
+ reg = <SC_R_UART_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpuart2: PD_DMA_UART2 {
+ reg = <SC_R_UART_2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpuart3: PD_DMA_UART3 {
+ reg = <SC_R_UART_3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpspi0: PD_DMA_SPI_0 {
+ reg = <SC_R_SPI_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpspi1: PD_DMA_SPI_1 {
+ reg = <SC_R_SPI_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpspi2: PD_DMA_SPI_2 {
+ reg = <SC_R_SPI_2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpspi3: PD_DMA_SPI_3 {
+ reg = <SC_R_SPI_3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_pwm0: PD_DMA_PWM_0 {
+ reg = <SC_R_LCD_0_PWM_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lcd0: PD_DMA_LCD_0 {
+ reg = <SC_R_LCD_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ };
+
+ pd_gpu: gpu-power-domain {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_LAST>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_gpu0: gpu0 {
+ name = "gpu0";
+ reg = <SC_R_GPU_0_PID0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_gpu>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ pd_vpu: vpu-power-domain {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_VPU>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_vpu_core: vpu_core {
+ name = "vpu_core";
+ reg = <SC_R_VPUCORE>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_vpu>;
+ };
+ };
+
+ pd_hsio: hsio-power-domain {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_LAST>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_serdes1: PD_HSIO_SERDES_1 {
+ reg = <SC_R_SERDES_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_hsio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_pcie: PD_HSIO_PCIE_B {
+ reg = <SC_R_PCIE_B>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_serdes1>;
+ };
+ };
+ };
+
+ pd_cm40: PD_CM40 {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_LAST>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_cm40_i2c: PD_CM40_I2C {
+ reg = <SC_R_M4_0_I2C>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_cm40>;
+ };
+
+ pd_cm40_intmux: PD_CM40_INTMUX {
+ reg = <SC_R_M4_0_INTMUX>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_cm40>;
+ };
+ };
+
+
+ pd_dc0: PD_DC_0 {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_DC_0>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_dc0_pll0: PD_DC_0_PLL_0{
+ reg = <SC_R_DC_0_PLL_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_dc0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_dc0_pll1: PD_DC_0_PLL_1{
+ reg = <SC_R_DC_0_PLL_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_dc0_pll0>;
+ };
+ };
+ pd_mipi_dsi0: PD_MIPI_0_DSI {
+ reg = <SC_R_MIPI_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_dc0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_mipi_dsi_0_lvds: PD_LVDS0 {
+ reg = <SC_R_LVDS_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_mipi_dsi0>;
+ };
+
+ pd_mipi_dsi_0_i2c0: PD_MIPI_0_DSI_I2C0 {
+ reg = <SC_R_MIPI_0_I2C_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_mipi_dsi0>;
+ };
+ pd_mipi_dsi_0_i2c1: PD_MIPI_0_DSI_I2C1 {
+ reg = <SC_R_MIPI_0_I2C_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_mipi_dsi0>;
+ };
+ pd_mipi_0_pwm0: PD_MIPI_0_DSI_PWM0 {
+ reg = <SC_R_MIPI_0_PWM_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_mipi_dsi0>;
+ };
+ };
+
+ pd_mipi_dsi1: PD_MIPI_1_DSI {
+ reg = <SC_R_MIPI_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_dc0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_mipi_dsi_1_lvds: PD_LVDS1 {
+ reg = <SC_R_LVDS_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_mipi_dsi1>;
+ };
+
+ pd_mipi_dsi_1_i2c0: PD_MIPI_1_DSI_I2C0 {
+ reg = <SC_R_MIPI_1_I2C_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_mipi_dsi1>;
+ };
+ pd_mipi_dsi_1_i2c1: PD_MIPI_1_DSI_I2C1 {
+ reg = <SC_R_MIPI_1_I2C_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_mipi_dsi1>;
+ };
+ pd_mipi_1_pwm0: PD_MIPI_1_DSI_PWM0 {
+ reg = <SC_R_MIPI_1_PWM_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_mipi_dsi1>;
+ };
+ };
+ };
+
+ pd_isi_ch0: PD_IMAGING {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_ISI_CH0>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_mipi_csi: PD_MIPI_CSI0 {
+ reg = <SC_R_CSI_0>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains =<&pd_isi_ch0>;
+
+ pd_mipi_csi_i2c0: PD_MIPI_CSI0_I2C {
+ name = "mipi_csi0_i2c";
+ reg = <SC_R_CSI_0_I2C_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_mipi_csi>;
+ };
+
+ pd_mipi_csi_pwm0: PD_MIPI_CSI0_PWM {
+ name = "mipi_csi0_pwm";
+ reg = <SC_R_CSI_0_PWM_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_mipi_csi>;
+ };
+ };
+
+ pd_isi_ch1: PD_IMAGING_PDMA1 {
+ reg = <SC_R_ISI_CH1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_isi_ch0>;
+ };
+
+ pd_isi_ch2: PD_IMAGING_PDMA2 {
+ reg = <SC_R_ISI_CH2>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_isi_ch0>;
+ };
+
+ pd_isi_ch3: PD_IMAGING_PDMA3 {
+ reg = <SC_R_ISI_CH3>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_isi_ch0>;
+ };
+
+ pd_isi_ch4: PD_IMAGING_PDMA4 {
+ reg = <SC_R_ISI_CH4>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_isi_ch0>;
+ };
+
+ pd_isi_ch5: PD_IMAGING_PDMA5 {
+ reg = <SC_R_ISI_CH5>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_isi_ch0>;
+ };
+
+ pd_isi_ch6: PD_IMAGING_PDMA6 {
+ reg = <SC_R_ISI_CH6>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_isi_ch0>;
+ };
+
+ pd_isi_ch7: PD_IMAGING_PDMA7 {
+ reg = <SC_R_ISI_CH7>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_isi_ch0>;
+ };
+ };
+ };
+
+ tsens: thermal-sensor {
+ compatible = "nxp,imx8qxp-sc-tsens";
+ u-boot,dm-pre-reloc;
+ /* number of the temp sensor on the chip */
+ tsens-num = <1>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ /* cpu thermal */
+ cpu-thermal0 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ /*the slope and offset of the temp sensor */
+ thermal-sensors = <&tsens 0>;
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit0: trip1 {
+ temperature = <127000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ gpio0: gpio at 5d080000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d080000 0x0 0x10000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd_lsio_gpio0>;
+ };
+
+ gpio1: gpio at 5d090000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d090000 0x0 0x10000>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd_lsio_gpio1>;
+ };
+
+ gpio2: gpio at 5d0a0000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d0a0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd_lsio_gpio2>;
+ };
+
+ gpio3: gpio at 5d0b0000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d0b0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd_lsio_gpio3>;
+ };
+
+ gpio4: gpio at 5d0c0000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d0c0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd_lsio_gpio4>;
+ };
+
+ gpio5: gpio at 5d0d0000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d0d0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd_lsio_gpio5>;
+ };
+
+ gpio6: gpio at 5d0e0000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d0e0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd_lsio_gpio6>;
+ };
+
+ gpio7: gpio at 5d0f0000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d0f0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd_lsio_gpio7>;
+ };
+
+ irqsteer_csi: irqsteer at 58220000 {
+ compatible = "nxp,imx-irqsteer";
+ reg = <0x0 0x58220000 0x0 0x1000>;
+ interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ clocks = <&clk IMX8QXP_CSI0_IPG_CLK>;
+ clock-names = "ipg";
+ power-domains = <&pd_mipi_csi>;
+ };
+
+ i2c0_csi0: i2c at 58226000 {
+ compatible = "fsl,imx8qm-lpi2c";
+ reg = <0x0 0x58226000 0x0 0x1000>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&irqsteer_csi>;
+ clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>,
+ <&clk IMX8QXP_CSI0_I2C0_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd_mipi_csi_i2c0>;
+ status = "disabled";
+ };
+
+ irqsteer_mipi_lvds0: irqsteer at 56220000 {
+ compatible = "nxp,imx-irqsteer";
+ reg = <0x0 0x56220000 0x0 0x1000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ clocks = <&clk IMX8QXP_MIPI0_LIS_IPG_CLK>;
+ clock-names = "ipg";
+ power-domains = <&pd_mipi_dsi0>;
+ };
+
+ i2c0_mipi_lvds0: i2c at 56226000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c";
+ reg = <0x0 0x56226000 0x0 0x1000>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&irqsteer_mipi_lvds0>;
+ clocks = <&clk IMX8QXP_MIPI0_I2C0_CLK>,
+ <&clk IMX8QXP_MIPI0_I2C0_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QXP_MIPI0_I2C0_DIV>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd_mipi_dsi_0_i2c0>;
+ status = "disabled";
+ };
+
+ irqsteer_mipi_lvds1: irqsteer at 56240000 {
+ compatible = "nxp,imx-irqsteer";
+ reg = <0x0 0x56240000 0x0 0x1000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ clocks = <&clk IMX8QXP_MIPI1_LIS_IPG_CLK>;
+ clock-names = "ipg";
+ power-domains = <&pd_mipi_dsi1>;
+ };
+
+ i2c0_mipi_lvds1: i2c at 56246000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c";
+ reg = <0x0 0x56246000 0x0 0x1000>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&irqsteer_mipi_lvds1>;
+ clocks = <&clk IMX8QXP_MIPI1_I2C0_CLK>,
+ <&clk IMX8QXP_MIPI1_I2C0_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QXP_MIPI1_I2C0_DIV>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd_mipi_dsi_1_i2c0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c at 5a800000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x0 0x5a800000 0x0 0x4000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&clk IMX8QXP_I2C0_CLK>;
+ clock-names = "per";
+ assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd_dma_lpi2c0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 5a810000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x0 0x5a810000 0x0 0x4000>;
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&clk IMX8QXP_I2C1_CLK>,
+ <&clk IMX8QXP_I2C1_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd_dma_lpi2c1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 5a820000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x0 0x5a820000 0x0 0x4000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&clk IMX8QXP_I2C2_CLK>;
+ clock-names = "per";
+ assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd_dma_lpi2c2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at 5a830000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x0 0x5a830000 0x0 0x4000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&clk IMX8QXP_I2C3_CLK>,
+ <&clk IMX8QXP_I2C3_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd_dma_lpi2c3>;
+ status = "disabled";
+ };
+
+ lpuart0: serial at 5a060000 {
+ compatible = "fsl,imx8qm-lpuart";
+ reg = <0x0 0x5a060000 0x0 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&clk IMX8QXP_UART0_CLK>,
+ <&clk IMX8QXP_UART0_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&pd_dma_lpuart0>;
+ status = "disabled";
+ };
+
+ lpuart1: serial at 5a070000 {
+ compatible = "fsl,imx8qm-lpuart";
+ reg = <0x0 0x5a070000 0x0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&clk IMX8QXP_UART1_CLK>,
+ <&clk IMX8QXP_UART1_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&pd_dma_lpuart1>;
+ dma-names = "tx","rx";
+ dmas = <&edma0 11 0 0>,
+ <&edma0 10 0 1>;
+ status = "disabled";
+ };
+
+ lpuart2: serial at 5a080000 {
+ compatible = "fsl,imx8qm-lpuart";
+ reg = <0x0 0x5a080000 0x0 0x1000>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&clk IMX8QXP_UART2_CLK>,
+ <&clk IMX8QXP_UART2_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&pd_dma_lpuart2>;
+ dma-names = "tx","rx";
+ dmas = <&edma0 13 0 0>,
+ <&edma0 12 0 1>;
+ status = "disabled";
+ };
+
+ lpuart3: serial at 5a090000 {
+ compatible = "fsl,imx8qm-lpuart";
+ reg = <0x0 0x5a090000 0x0 0x1000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&clk IMX8QXP_UART3_CLK>,
+ <&clk IMX8QXP_UART3_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&pd_dma_lpuart3>;
+ dma-names = "tx","rx";
+ dmas = <&edma0 15 0 0>,
+ <&edma0 14 0 1>;
+ status = "disabled";
+ };
+
+ edma0: dma-controller at 5a1f0000 {
+ compatible = "fsl,imx8qm-edma";
+ reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */
+ <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */
+ <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */
+ <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */
+ <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */
+ <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */
+ <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */
+ <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */
+ #dma-cells = <3>;
+ dma-channels = <8>;
+ interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-chan8-tx", "edma-chan9-tx",
+ "edma-chan10-tx", "edma-chan11-tx",
+ "edma-chan12-tx", "edma-chan13-tx",
+ "edma-chan14-tx", "edma-chan15-tx";
+ status = "okay";
+ };
+
+ edma2: dma-controller at 591F0000 {
+ compatible = "fsl,imx8qm-edma";
+ reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */
+ <0x0 0x59210000 0x0 0x10000>,
+ <0x0 0x59220000 0x0 0x10000>,
+ <0x0 0x59230000 0x0 0x10000>,
+ <0x0 0x59240000 0x0 0x10000>,
+ <0x0 0x59250000 0x0 0x10000>,
+ <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */
+ <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */
+ <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */
+ <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */
+ <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */
+ <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */
+ <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */
+ <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */
+ <0x0 0x59350000 0x0 0x10000>,
+ <0x0 0x59370000 0x0 0x10000>;
+ #dma-cells = <3>;
+ shared-interrupt;
+ dma-channels = <16>;
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc0 */
+ "edma-chan2-tx", "edma-chan3-tx",
+ "edma-chan4-tx", "edma-chan5-tx",
+ "edma-chan6-tx", "edma-chan7-tx", /* esai0 */
+ "edma-chan8-tx", "edma-chan9-tx", /* spdif0 */
+ "edma-chan12-tx", "edma-chan13-tx", /* sai0 */
+ "edma-chan14-tx", "edma-chan15-tx", /* sai1 */
+ "edma-chan21-tx", /* gpt5 */
+ "edma-chan23-tx"; /* gpt7 */
+ status = "okay";
+ };
+
+ edma3: dma-controller at 599F0000 {
+ compatible = "fsl,imx8qm-edma";
+ reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */
+ <0x0 0x59A10000 0x0 0x10000>,
+ <0x0 0x59A20000 0x0 0x10000>,
+ <0x0 0x59A30000 0x0 0x10000>,
+ <0x0 0x59A40000 0x0 0x10000>,
+ <0x0 0x59A50000 0x0 0x10000>,
+ <0x0 0x59A80000 0x0 0x10000>, /* sai4 rx */
+ <0x0 0x59A90000 0x0 0x10000>, /* sai4 tx */
+ <0x0 0x59AA0000 0x0 0x10000>; /* sai5 tx */
+ #dma-cells = <3>;
+ shared-interrupt;
+ dma-channels = <9>;
+ interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
+ interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc1 */
+ "edma-chan2-tx", "edma-chan3-tx",
+ "edma-chan4-tx", "edma-chan5-tx",
+ "edma-chan8-tx", "edma-chan9-tx", /* sai4 */
+ "edma-chan10-tx"; /* sai5 */
+ status = "okay";
+ };
+
+ acm: acm at 59e00000 {
+ compatible = "nxp,imx8qm-acm";
+ reg = <0x0 0x59e00000 0x0 0x1D0000>;
+ status = "disabled";
+ };
+
+ sai0: sai at 59040000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x0 0x59040000 0x0 0x10000>;
+ interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_AUD_SAI_0_MCLK>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&edma2 12 0 1>, <&edma2 13 0 0>;
+ status = "disabled";
+ power-domains = <&pd_sai0>;
+ };
+
+ sai1: sai at 59050000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x0 0x59050000 0x0 0x10000>;
+ interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_AUD_SAI_1_MCLK>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&edma2 14 0 1>, <&edma2 15 0 0>;
+ status = "disabled";
+ power-domains = <&pd_sai1>;
+ };
+
+ sai4: sai at 59820000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x0 0x59820000 0x0 0x10000>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QXP_AUD_SAI_4_IPG>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_AUD_SAI_4_MCLK>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>;
+ dmas = <&edma3 8 0 1>, <&edma3 9 0 0>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ status = "disabled";
+ power-domains = <&pd_sai4>;
+ };
+
+ sai5: sai at 59830000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x0 0x59830000 0x0 0x10000>;
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QXP_AUD_SAI_5_IPG>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_AUD_SAI_5_MCLK>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx";
+ dmas = <&edma3 10 0 0>;
+ status = "disabled";
+ power-domains = <&pd_sai5>;
+ };
+
+ amix: amix at 59840000 {
+ compatible = "fsl,imx8qm-amix";
+ reg = <0x0 0x59840000 0x0 0x10000>;
+ clocks = <&clk IMX8QXP_AUD_AMIX_IPG>;
+ clock-names = "ipg";
+ power-domains = <&pd_amix>;
+ status = "disabled";
+ };
+
+ asrc0: asrc at 59000000 {
+ compatible = "fsl,imx8qm-asrc0";
+ reg = <0x0 0x59000000 0x0 0x10000>;
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
+ <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>;
+ clock-names = "ipg", "mem",
+ "asrck_0", "asrck_1", "asrck_2", "asrck_3",
+ "asrck_4", "asrck_5", "asrck_6", "asrck_7",
+ "asrck_8", "asrck_9", "asrck_a", "asrck_b",
+ "asrck_c", "asrck_d", "asrck_e", "asrck_f",
+ "spba";
+ dmas = <&edma2 0 0 0>, <&edma2 1 0 0>, <&edma2 2 0 0>,
+ <&edma2 3 0 1>, <&edma2 4 0 1>, <&edma2 5 0 1>;
+ dma-names = "rxa", "rxb", "rxc",
+ "txa", "txb", "txc";
+ fsl,asrc-rate = <8000>;
+ fsl,asrc-width = <16>;
+ power-domains = <&pd_asrc0>;
+ status = "disabled";
+ };
+
+ asrc1: asrc at 59800000 {
+ compatible = "fsl,imx8qm-asrc1";
+ reg = <0x0 0x59800000 0x0 0x10000>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QXP_AUD_ASRC_1_IPG>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
+ <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>,
+ <&clk IMX8QXP_CLK_DUMMY>;
+ clock-names = "ipg", "mem",
+ "asrck_0", "asrck_1", "asrck_2", "asrck_3",
+ "asrck_4", "asrck_5", "asrck_6", "asrck_7",
+ "asrck_8", "asrck_9", "asrck_a", "asrck_b",
+ "asrck_c", "asrck_d", "asrck_e", "asrck_f",
+ "spba";
+ dmas = <&edma3 0 0 0>, <&edma3 1 0 0>, <&edma3 2 0 0>,
+ <&edma3 3 0 1>, <&edma3 4 0 1>, <&edma3 5 0 1>;
+ dma-names = "rxa", "rxb", "rxc",
+ "txa", "txb", "txc";
+ fsl,asrc-rate = <8000>;
+ fsl,asrc-width = <16>;
+ power-domains = <&pd_asrc1>;
+ status = "disabled";
+ };
+
+ mqs: mqs at 59850000 {
+ compatible = "fsl,imx8qm-mqs";
+ reg = <0x0 0x59850000 0x0 0x10000>;
+ clocks = <&clk IMX8QXP_AUD_MQS_IPG>,
+ <&clk IMX8QXP_AUD_MQS_HMCLK>;
+ clock-names = "core", "mclk";
+ power-domains = <&pd_mqs0>;
+ status = "disabled";
+ };
+
+ usdhc1: usdhc at 5b010000 {
+ compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x5b010000 0x0 0x10000>;
+ clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>,
+ <&clk IMX8QXP_SDHC0_CLK>,
+ <&clk IMX8QXP_CLK_DUMMY>;
+ clock-names = "ipg", "per", "ahb";
+ assigned-clocks = <&clk IMX8QXP_SDHC0_DIV>;
+ assigned-clock-rates = <400000000>;
+ power-domains = <&pd_conn_sdch0>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc2: usdhc at 5b020000 {
+ compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x5b020000 0x0 0x10000>;
+ clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>,
+ <&clk IMX8QXP_SDHC1_CLK>,
+ <&clk IMX8QXP_CLK_DUMMY>;
+ clock-names = "ipg", "per", "ahb";
+ assigned-clocks = <&clk IMX8QXP_SDHC1_DIV>;
+ assigned-clock-rates = <200000000>;
+ power-domains = <&pd_conn_sdch1>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc3: usdhc at 5b030000 {
+ compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x5b030000 0x0 0x10000>;
+ clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>,
+ <&clk IMX8QXP_SDHC2_CLK>,
+ <&clk IMX8QXP_CLK_DUMMY>;
+ clock-names = "ipg", "per", "ahb";
+ assigned-clocks = <&clk IMX8QXP_SDHC2_DIV>;
+ assigned-clock-rates = <200000000>;
+ power-domains = <&pd_conn_sdch2>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step = <2>;
+ status = "disabled";
+ };
+
+ fec1: ethernet at 5b040000 {
+ compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
+ reg = <0x0 0x5b040000 0x0 0x10000>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>,
+ <&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>;
+ clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
+ assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>,
+ <&clk IMX8QXP_ENET0_REF_DIV>,
+ <&clk IMX8QXP_ENET0_PTP_CLK>;
+ assigned-clock-rates = <250000000>, <125000000>, <125000000>;
+ fsl,num-tx-queues=<3>;
+ fsl,num-rx-queues=<3>;
+ power-domains = <&pd_conn_enet0>;
+ status = "disabled";
+ };
+
+ fec2: ethernet at 5b050000 {
+ compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
+ reg = <0x0 0x5b050000 0x0 0x10000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, <&clk IMX8QXP_ENET1_RGMII_TX_CLK>,
+ <&clk IMX8QXP_ENET1_PTP_CLK>, <&clk IMX8QXP_ENET1_TX_CLK>;
+ clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
+ assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>,
+ <&clk IMX8QXP_ENET1_REF_DIV>,
+ <&clk IMX8QXP_ENET1_PTP_CLK>;
+ assigned-clock-rates = <250000000>, <125000000>, <125000000>;
+ fsl,num-tx-queues=<3>;
+ fsl,num-rx-queues=<3>;
+ power-domains = <&pd_conn_enet1>;
+ status = "disabled";
+ };
+
+ mlb: mlb at 5B060000 {
+ compatible = "fsl,imx6q-mlb150";
+ reg = <0x0 0x5B060000 0x0 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>,
+ <0 266 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QXP_MLB_CLK>,
+ <&clk IMX8QXP_MLB_HCLK>,
+ <&clk IMX8QXP_MLB_IPG_CLK>;
+ clock-names = "mlb", "hclk", "ipg";
+ assigned-clocks = <&clk IMX8QXP_MLB_CLK>,
+ <&clk IMX8QXP_MLB_HCLK>,
+ <&clk IMX8QXP_MLB_IPG_CLK>;
+ assigned-clock-rates = <333333333>, <333333333>, <83333333>;
+ power-domains = <&pd_conn_mlb0>;
+ status = "disabled";
+ };
+
+ hifi4: hifi4 at 586e8000 {
+ compatible = "fsl,imx8qxp-hifi4";
+ reg = <0x0 0x596e8000 0x0 0x88000>;
+ clocks = <&clk IMX8QXP_AUD_HIFI_IPG>,
+ <&clk IMX8QXP_AUD_OCRAM_IPG>,
+ <&clk IMX8QXP_AUD_HIFI_CORE_CLK>;
+ clock-names = "ipg", "ocram", "core";
+ fsl,hifi4-firmware = "imx/hifi/hifi4.bin";
+ power-domains = <&pd_hifi>;
+ };
+
+ esai0: esai at 59010000 {
+ compatible = "fsl,imx6ull-esai";
+ reg = <0x0 0x59010000 0x0 0x10000>;
+ interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>,
+ <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>,
+ <&clk IMX8QXP_AUD_ESAI_0_IPG>;
+ clock-names = "core", "extal", "fsys";
+ dmas = <&edma2 6 0 1>, <&edma2 7 0 0>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_esai0>;
+ status = "disabled";
+ };
+
+ spdif0: spdif at 59020000 {
+ compatible = "fsl,imx8qm-spdif";
+ reg = <0x0 0x59020000 0x0 0x10000>;
+ interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
+ clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */
+ <&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */
+ <&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */
+ <&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */
+ <&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */
+ <&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */
+ <&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */
+ <&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */
+ <&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */
+ <&clk IMX8QXP_CLK_DUMMY>; /* spba */
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+ "rxtx7", "spba";
+ dmas = <&edma2 8 0 5>, <&edma2 9 0 4>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_spdif0>;
+ status = "disabled";
+ };
+
+ flexspi0: flexspi at 05d120000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qm-flexspi";
+ reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x19ffffff>;
+ reg-names = "FlexSPI", "FlexSPI-memory";
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>,
+ <&clk IMX8QXP_LSIO_FSPI0_CLK>;
+ assigned-clock-rates = <29000000>,<29000000>;
+ clock-names = "qspi_en", "qspi";
+ power-domains = <&pd_lsio_flexspi0>;
+ status = "disabled";
+ };
+};
diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h
new file mode 100644
index 0000000000..a31c120dc0
--- /dev/null
+++ b/include/dt-bindings/clock/imx8qxp-clock.h
@@ -0,0 +1,533 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H
+#define __DT_BINDINGS_CLOCK_IMX8QXP_H
+
+#define IMX8QXP_CLK_DUMMY 0
+
+#define IMX8QXP_UART0_IPG_CLK 1
+#define IMX8QXP_UART0_DIV 2
+#define IMX8QXP_UART0_CLK 3
+
+#define IMX8QXP_IPG_DMA_CLK_ROOT 4
+
+/* GPU Clocks. */
+#define IMX8QXP_GPU0_CORE_DIV 5
+#define IMX8QXP_GPU0_CORE_CLK 6
+#define IMX8QXP_GPU0_SHADER_DIV 7
+#define IMX8QXP_GPU0_SHADER_CLK 8
+
+#define IMX8QXP_24MHZ 9
+#define IMX8QXP_GPT_3M 10
+#define IMX8QXP_32KHZ 11
+
+/* LSIO SS */
+#define IMX8QXP_LSIO_MEM_CLK 12
+#define IMX8QXP_LSIO_BUS_CLK 13
+#define IMX8QXP_LSIO_PWM0_DIV 14
+#define IMX8QXP_LSIO_PWM0_IPG_S_CLK 15
+#define IMX8QXP_LSIO_PWM0_IPG_SLV_CLK 16
+#define IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK 17
+#define IMX8QXP_LSIO_PWM0_HF_CLK 18
+#define IMX8QXP_LSIO_PWM0_CLK 19
+#define IMX8QXP_LSIO_PWM1_DIV 20
+#define IMX8QXP_LSIO_PWM1_IPG_S_CLK 21
+#define IMX8QXP_LSIO_PWM1_IPG_SLV_CLK 22
+#define IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK 23
+#define IMX8QXP_LSIO_PWM1_HF_CLK 24
+#define IMX8QXP_LSIO_PWM1_CLK 25
+#define IMX8QXP_LSIO_PWM2_DIV 26
+#define IMX8QXP_LSIO_PWM2_IPG_S_CLK 27
+#define IMX8QXP_LSIO_PWM2_IPG_SLV_CLK 28
+#define IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK 29
+#define IMX8QXP_LSIO_PWM2_HF_CLK 30
+#define IMX8QXP_LSIO_PWM2_CLK 31
+#define IMX8QXP_LSIO_PWM3_DIV 32
+#define IMX8QXP_LSIO_PWM3_IPG_S_CLK 33
+#define IMX8QXP_LSIO_PWM3_IPG_SLV_CLK 34
+#define IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK 35
+#define IMX8QXP_LSIO_PWM3_HF_CLK 36
+#define IMX8QXP_LSIO_PWM3_CLK 37
+#define IMX8QXP_LSIO_PWM4_DIV 38
+#define IMX8QXP_LSIO_PWM4_IPG_S_CLK 39
+#define IMX8QXP_LSIO_PWM4_IPG_SLV_CLK 40
+#define IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK 42
+#define IMX8QXP_LSIO_PWM4_HF_CLK 43
+#define IMX8QXP_LSIO_PWM4_CLK 44
+#define IMX8QXP_LSIO_PWM5_DIV 45
+#define IMX8QXP_LSIO_PWM5_IPG_S_CLK 46
+#define IMX8QXP_LSIO_PWM5_IPG_SLV_CLK 47
+#define IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK 48
+#define IMX8QXP_LSIO_PWM5_HF_CLK 49
+#define IMX8QXP_LSIO_PWM5_CLK 50
+#define IMX8QXP_LSIO_PWM6_DIV 51
+#define IMX8QXP_LSIO_PWM6_IPG_S_CLK 52
+#define IMX8QXP_LSIO_PWM6_IPG_SLV_CLK 53
+#define IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK 54
+#define IMX8QXP_LSIO_PWM6_HF_CLK 55
+#define IMX8QXP_LSIO_PWM6_CLK 56
+#define IMX8QXP_LSIO_PWM7_DIV 57
+#define IMX8QXP_LSIO_PWM7_IPG_S_CLK 58
+#define IMX8QXP_LSIO_PWM7_IPG_SLV_CLK 59
+#define IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK 60
+#define IMX8QXP_LSIO_PWM7_HF_CLK 61
+#define IMX8QXP_LSIO_PWM7_CLK 62
+#define IMX8QXP_LSIO_GPT0_DIV 63
+#define IMX8QXP_LSIO_GPT0_IPG_S_CLK 64
+#define IMX8QXP_LSIO_GPT0_IPG_SLV_CLK 65
+#define IMX8QXP_LSIO_GPT0_IPG_MSTR_CLK 66
+#define IMX8QXP_LSIO_GPT0_HF_CLK 67
+#define IMX8QXP_LSIO_GPT0_CLK 68
+#define IMX8QXP_LSIO_GPT1_DIV 69
+#define IMX8QXP_LSIO_GPT1_IPG_S_CLK 70
+#define IMX8QXP_LSIO_GPT1_IPG_SLV_CLK 71
+#define IMX8QXP_LSIO_GPT1_IPG_MSTR_CLK 72
+#define IMX8QXP_LSIO_GPT1_HF_CLK 73
+#define IMX8QXP_LSIO_GPT1_CLK 74
+#define IMX8QXP_LSIO_GPT2_DIV 75
+#define IMX8QXP_LSIO_GPT2_IPG_S_CLK 76
+#define IMX8QXP_LSIO_GPT2_IPG_SLV_CLK 77
+#define IMX8QXP_LSIO_GPT2_IPG_MSTR_CLK 78
+#define IMX8QXP_LSIO_GPT2_HF_CLK 79
+#define IMX8QXP_LSIO_GPT2_CLK 80
+#define IMX8QXP_LSIO_GPT3_DIV 81
+#define IMX8QXP_LSIO_GPT3_IPG_S_CLK 82
+#define IMX8QXP_LSIO_GPT3_IPG_SLV_CLK 83
+#define IMX8QXP_LSIO_GPT3_IPG_MSTR_CLK 84
+#define IMX8QXP_LSIO_GPT3_HF_CLK 85
+#define IMX8QXP_LSIO_GPT3_CLK 86
+#define IMX8QXP_LSIO_GPT4_DIV 87
+#define IMX8QXP_LSIO_GPT4_IPG_S_CLK 88
+#define IMX8QXP_LSIO_GPT4_IPG_SLV_CLK 89
+#define IMX8QXP_LSIO_GPT4_IPG_MSTR_CLK 90
+#define IMX8QXP_LSIO_GPT4_HF_CLK 91
+#define IMX8QXP_LSIO_GPT4_CLK 92
+#define IMX8QXP_LSIO_FSPI0_DIV 93
+#define IMX8QXP_LSIO_FSPI0_HCLK 94
+#define IMX8QXP_LSIO_FSPI0_IPG_S_CLK 95
+#define IMX8QXP_LSIO_FSPI0_IPG_CLK 96
+#define IMX8QXP_LSIO_FSPI0_CLK 97
+#define IMX8QXP_LSIO_FSPI1_DIV 98
+#define IMX8QXP_LSIO_FSPI1_HCLK 99
+#define IMX8QXP_LSIO_FSPI1_IPG_S_CLK 100
+#define IMX8QXP_LSIO_FSPI1_IPG_CLK 101
+#define IMX8QXP_LSIO_FSPI1_CLK 102
+#define IMX8QXP_LSIO_GPIO0_IPG_S_CLK 103
+#define IMX8QXP_LSIO_GPIO1_IPG_S_CLK 104
+#define IMX8QXP_LSIO_GPIO2_IPG_S_CLK 105
+#define IMX8QXP_LSIO_GPIO3_IPG_S_CLK 106
+#define IMX8QXP_LSIO_GPIO4_IPG_S_CLK 107
+#define IMX8QXP_LSIO_GPIO5_IPG_S_CLK 108
+#define IMX8QXP_LSIO_GPIO6_IPG_S_CLK 109
+#define IMX8QXP_LSIO_GPIO7_IPG_S_CLK 110
+#define IMX8QXP_LSIO_ROMCP_REG_CLK 111
+#define IMX8QXP_LSIO_ROMCP_CLK 112
+#define IMX8QXP_LSIO_96KROM_CLK 113
+#define IMX8QXP_LSIO_OCRAM_MEM_CLK 114
+#define IMX8QXP_LSIO_OCRAM_CTRL_CLK 115
+
+/* ADMA SS */
+#define IMX8QXP_UART1_IPG_CLK 116
+#define IMX8QXP_UART2_IPG_CLK 117
+#define IMX8QXP_UART3_IPG_CLK 118
+#define IMX8QXP_UART1_DIV 119
+#define IMX8QXP_UART2_DIV 120
+#define IMX8QXP_UART3_DIV 121
+#define IMX8QXP_UART1_CLK 122
+#define IMX8QXP_UART2_CLK 123
+#define IMX8QXP_UART3_CLK 124
+#define IMX8QXP_SPI0_IPG_CLK 125
+#define IMX8QXP_SPI1_IPG_CLK 126
+#define IMX8QXP_SPI2_IPG_CLK 127
+#define IMX8QXP_SPI3_IPG_CLK 128
+#define IMX8QXP_SPI0_DIV 129
+#define IMX8QXP_SPI1_DIV 130
+#define IMX8QXP_SPI2_DIV 131
+#define IMX8QXP_SPI3_DIV 132
+#define IMX8QXP_SPI0_CLK 133
+#define IMX8QXP_SPI1_CLK 134
+#define IMX8QXP_SPI2_CLK 135
+#define IMX8QXP_SPI3_CLK 136
+#define IMX8QXP_CAN0_IPG_CHI_CLK 137
+#define IMX8QXP_CAN1_IPG_CHI_CLK 138
+#define IMX8QXP_CAN2_IPG_CHI_CLK 139
+#define IMX8QXP_CAN0_IPG_CLK 140
+#define IMX8QXP_CAN1_IPG_CLK 141
+#define IMX8QXP_CAN2_IPG_CLK 142
+#define IMX8QXP_CAN0_DIV 143
+#define IMX8QXP_CAN1_DIV 144
+#define IMX8QXP_CAN2_DIV 145
+#define IMX8QXP_CAN0_CLK 146
+#define IMX8QXP_CAN1_CLK 147
+#define IMX8QXP_CAN2_CLK 148
+#define IMX8QXP_I2C0_IPG_CLK 149
+#define IMX8QXP_I2C1_IPG_CLK 150
+#define IMX8QXP_I2C2_IPG_CLK 151
+#define IMX8QXP_I2C3_IPG_CLK 152
+#define IMX8QXP_I2C0_DIV 153
+#define IMX8QXP_I2C1_DIV 154
+#define IMX8QXP_I2C2_DIV 155
+#define IMX8QXP_I2C3_DIV 156
+#define IMX8QXP_I2C0_CLK 157
+#define IMX8QXP_I2C1_CLK 158
+#define IMX8QXP_I2C2_CLK 159
+#define IMX8QXP_I2C3_CLK 160
+#define IMX8QXP_FTM0_IPG_CLK 161
+#define IMX8QXP_FTM1_IPG_CLK 162
+#define IMX8QXP_FTM0_DIV 163
+#define IMX8QXP_FTM1_DIV 164
+#define IMX8QXP_FTM0_CLK 165
+#define IMX8QXP_FTM1_CLK 166
+#define IMX8QXP_ADC0_IPG_CLK 167
+#define IMX8QXP_ADC0_DIV 168
+#define IMX8QXP_ADC0_CLK 169
+#define IMX8QXP_PWM_IPG_CLK 170
+#define IMX8QXP_PWM_DIV 171
+#define IMX8QXP_PWM_CLK 172
+#define IMX8QXP_LCD_IPG_CLK 173
+#define IMX8QXP_LCD_DIV 174
+#define IMX8QXP_LCD_CLK 175
+
+/* Connectivity SS */
+#define IMX8QXP_AXI_CONN_CLK_ROOT 176
+#define IMX8QXP_AHB_CONN_CLK_ROOT 177
+#define IMX8QXP_IPG_CONN_CLK_ROOT 178
+#define IMX8QXP_SDHC0_IPG_CLK 179
+#define IMX8QXP_SDHC1_IPG_CLK 180
+#define IMX8QXP_SDHC2_IPG_CLK 181
+#define IMX8QXP_SDHC0_DIV 182
+#define IMX8QXP_SDHC1_DIV 183
+#define IMX8QXP_SDHC2_DIV 184
+#define IMX8QXP_SDHC0_CLK 185
+#define IMX8QXP_SDHC1_CLK 186
+#define IMX8QXP_SDHC2_CLK 187
+#define IMX8QXP_ENET0_ROOT_DIV 188
+#define IMX8QXP_ENET0_REF_DIV 189
+#define IMX8QXP_ENET1_REF_DIV 190
+#define IMX8QXP_ENET0_BYPASS_DIV 191
+#define IMX8QXP_ENET0_RGMII_DIV 192
+#define IMX8QXP_ENET1_ROOT_DIV 193
+#define IMX8QXP_ENET1_BYPASS_DIV 194
+#define IMX8QXP_ENET1_RGMII_DIV 195
+#define IMX8QXP_ENET0_AHB_CLK 196
+#define IMX8QXP_ENET0_IPG_S_CLK 197
+#define IMX8QXP_ENET0_IPG_CLK 198
+#define IMX8QXP_ENET1_AHB_CLK 199
+#define IMX8QXP_ENET1_IPG_S_CLK 200
+#define IMX8QXP_ENET1_IPG_CLK 201
+#define IMX8QXP_ENET0_ROOT_CLK 202
+#define IMX8QXP_ENET1_ROOT_CLK 203
+#define IMX8QXP_ENET0_TX_CLK 204
+#define IMX8QXP_ENET1_TX_CLK 205
+#define IMX8QXP_ENET0_PTP_CLK 206
+#define IMX8QXP_ENET1_PTP_CLK 207
+#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_SEL 208
+#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_SEL 209
+#define IMX8QXP_ENET0_RMII_TX_SEL 210
+#define IMX8QXP_ENET1_RMII_TX_SEL 211
+#define IMX8QXP_ENET0_RGMII_TX_CLK 212
+#define IMX8QXP_ENET1_RGMII_TX_CLK 213
+#define IMX8QXP_ENET0_RMII_RX_CLK 214
+#define IMX8QXP_ENET1_RMII_RX_CLK 215
+#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_CLK 216
+#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_CLK 217
+#define IMX8QXP_ENET0_REF_50MHZ_CLK 218
+#define IMX8QXP_ENET1_REF_50MHZ_CLK 219
+#define IMX8QXP_GPMI_BCH_IO_DIV 220
+#define IMX8QXP_GPMI_BCH_DIV 221
+#define IMX8QXP_GPMI_APB_CLK 222
+#define IMX8QXP_GPMI_APB_BCH_CLK 223
+#define IMX8QXP_GPMI_BCH_IO_CLK 224
+#define IMX8QXP_GPMI_BCH_CLK 225
+#define IMX8QXP_APBHDMA_CLK 226
+#define IMX8QXP_USB3_ACLK_DIV 227
+#define IMX8QXP_USB3_BUS_DIV 228
+#define IMX8QXP_USB3_LPM_DIV 229
+#define IMX8QXP_USB3_IPG_CLK 230
+#define IMX8QXP_USB3_CORE_PCLK 231
+#define IMX8QXP_USB3_PHY_CLK 232
+#define IMX8QXP_USB3_ACLK 233
+#define IMX8QXP_USB3_BUS_CLK 234
+#define IMX8QXP_USB3_LPM_CLK 235
+#define IMX8QXP_USB2_OH_AHB_CLK 236
+#define IMX8QXP_USB2_OH_IPG_S_CLK 237
+#define IMX8QXP_USB2_OH_IPG_S_PL301_CLK 238
+#define IMX8QXP_USB2_PHY_IPG_CLK 239
+#define IMX8QXP_EDMA_CLK 240
+#define IMX8QXP_EDMA_IPG_CLK 241
+#define IMX8QXP_MLB_HCLK 242
+#define IMX8QXP_MLB_CLK 243
+#define IMX8QXP_MLB_IPG_CLK 244
+
+/* Display controller SS */
+/* DC part1 */
+#define IMX8QXP_DC_AXI_EXT_CLK 245
+#define IMX8QXP_DC_AXI_INT_CLK 246
+#define IMX8QXP_DC_CFG_CLK 247
+#define IMX8QXP_DC0_DISP0_CLK 248
+#define IMX8QXP_DC0_DISP1_CLK 249
+#define IMX8QXP_DC0_PRG0_RTRAM_CLK 250
+#define IMX8QXP_DC0_PRG0_APB_CLK 251
+#define IMX8QXP_DC0_PRG1_RTRAM_CLK 252
+#define IMX8QXP_DC0_PRG1_APB_CLK 253
+#define IMX8QXP_DC0_PRG2_RTRAM_CLK 254
+#define IMX8QXP_DC0_PRG2_APB_CLK 255
+#define IMX8QXP_DC0_PRG3_RTRAM_CLK 256
+#define IMX8QXP_DC0_PRG3_APB_CLK 257
+#define IMX8QXP_DC0_PRG4_RTRAM_CLK 258
+#define IMX8QXP_DC0_PRG4_APB_CLK 259
+#define IMX8QXP_DC0_PRG5_RTRAM_CLK 260
+#define IMX8QXP_DC0_PRG5_APB_CLK 261
+#define IMX8QXP_DC0_PRG6_RTRAM_CLK 262
+#define IMX8QXP_DC0_PRG6_APB_CLK 263
+#define IMX8QXP_DC0_PRG7_RTRAM_CLK 264
+#define IMX8QXP_DC0_PRG7_APB_CLK 265
+#define IMX8QXP_DC0_PRG8_RTRAM_CLK 266
+#define IMX8QXP_DC0_PRG8_APB_CLK 267
+#define IMX8QXP_DC0_DPR0_APB_CLK 268
+#define IMX8QXP_DC0_DPR0_B_CLK 269
+#define IMX8QXP_DC0_RTRAM0_CLK 270
+#define IMX8QXP_DC0_RTRAM1_CLK 271
+
+/* MIPI-LVDS part1 */
+#define IMX8QXP_MIPI_IPG_CLK 272
+#define IMX8QXP_MIPI0_I2C0_DIV 273
+#define IMX8QXP_MIPI0_I2C1_DIV 274
+#define IMX8QXP_MIPI0_I2C0_CLK 275
+#define IMX8QXP_MIPI0_I2C1_CLK 276
+#define IMX8QXP_MIPI0_I2C0_IPG_S_CLK 277
+#define IMX8QXP_MIPI0_I2C0_IPG_CLK 278
+#define IMX8QXP_MIPI0_I2C1_IPG_S_CLK 279
+#define IMX8QXP_MIPI0_I2C1_IPG_CLK 280
+#define IMX8QXP_MIPI0_PWM_IPG_S_CLK 281
+#define IMX8QXP_MIPI0_PWM_IPG_CLK 282
+#define IMX8QXP_MIPI0_PWM_32K_CLK 283
+#define IMX8QXP_MIPI0_GPIO_IPG_CLK 284
+
+#define IMX8QXP_IMG_JPEG_ENC_IPG_CLK 285
+#define IMX8QXP_IMG_JPEG_ENC_CLK 286
+#define IMX8QXP_IMG_JPEG_DEC_IPG_CLK 287
+#define IMX8QXP_IMG_JPEG_DEC_CLK 288
+#define IMX8QXP_IMG_PXL_LINK_DC0_CLK 289
+#define IMX8QXP_IMG_PXL_LINK_DC1_CLK 290
+#define IMX8QXP_IMG_PXL_LINK_CSI0_CLK 291
+#define IMX8QXP_IMG_PXL_LINK_CSI1_CLK 292
+#define IMX8QXP_IMG_PXL_LINK_HDMI_IN_CLK 293
+#define IMX8QXP_IMG_PDMA_0_CLK 294
+#define IMX8QXP_IMG_PDMA_1_CLK 295
+#define IMX8QXP_IMG_PDMA_2_CLK 296
+#define IMX8QXP_IMG_PDMA_3_CLK 297
+#define IMX8QXP_IMG_PDMA_4_CLK 298
+#define IMX8QXP_IMG_PDMA_5_CLK 299
+#define IMX8QXP_IMG_PDMA_6_CLK 300
+#define IMX8QXP_IMG_PDMA_7_CLK 301
+#define IMX8QXP_IMG_AXI_CLK 302
+#define IMX8QXP_IMG_IPG_CLK 303
+#define IMX8QXP_IMG_PXL_CLK 304
+
+#define IMX8QXP_CSI0_I2C0_DIV 305
+#define IMX8QXP_CSI0_PWM0_DIV 306
+#define IMX8QXP_CSI0_CORE_DIV 307
+#define IMX8QXP_CSI0_ESC_DIV 308
+#define IMX8QXP_CSI0_IPG_CLK_S 309
+#define IMX8QXP_CSI0_IPG_CLK 310
+#define IMX8QXP_CSI0_APB_CLK 311
+#define IMX8QXP_CSI0_I2C0_IPG_CLK 312
+#define IMX8QXP_CSI0_I2C0_CLK 313
+#define IMX8QXP_CSI0_PWM0_IPG_CLK 314
+#define IMX8QXP_CSI0_PWM0_CLK 315
+#define IMX8QXP_CSI0_CORE_CLK 316
+#define IMX8QXP_CSI0_ESC_CLK 317
+
+#define IMX8QXP_HSIO_AXI_CLK 318
+#define IMX8QXP_HSIO_PER_CLK 319
+#define IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK 320
+#define IMX8QXP_HSIO_PCIE_SLV_AXI_CLK 321
+#define IMX8QXP_HSIO_PCIE_DBI_AXI_CLK 322
+#define IMX8QXP_HSIO_PCIE_X1_PER_CLK 323
+#define IMX8QXP_HSIO_PHY_X1_PER_CLK 324
+#define IMX8QXP_HSIO_MISC_PER_CLK 325
+#define IMX8QXP_HSIO_PHY_X1_APB_CLK 326
+#define IMX8QXP_HSIO_GPIO_CLK 327
+#define IMX8QXP_HSIO_PHY_X1_PCLK 328
+
+#define IMX8QXP_A35_DIV 329
+
+/* ACM */
+#define IMX8QXP_EXT_AUD_MCLK0 330
+#define IMX8QXP_EXT_AUD_MCLK1 331
+#define IMX8QXP_ESAI0_RX_CLK 332
+#define IMX8QXP_ESAI0_RX_HF_CLK 333
+#define IMX8QXP_ESAI0_TX_CLK 334
+#define IMX8QXP_ESAI0_TX_HF_CLK 335
+#define IMX8QXP_SPDIF0_RX 336
+#define IMX8QXP_SAI0_RX_BCLK 337
+#define IMX8QXP_SAI0_TX_BCLK 338
+#define IMX8QXP_SAI1_RX_BCLK 339
+#define IMX8QXP_SAI1_TX_BCLK 340
+#define IMX8QXP_SAI2_RX_BCLK 341
+#define IMX8QXP_SAI3_RX_BCLK 342
+#define IMX8QXP_SAI4_RX_BCLK 343
+
+#define IMX8QXP_ACM_AUD_CLK0_SEL 344
+#define IMX8QXP_ACM_AUD_CLK0_CLK 345
+#define IMX8QXP_ACM_AUD_CLK1_SEL 346
+#define IMX8QXP_ACM_AUD_CLK1_CLK 347
+#define IMX8QXP_ACM_MCLKOUT0_SEL 348
+#define IMX8QXP_ACM_MCLKOUT0_CLK 349
+#define IMX8QXP_ACM_MCLKOUT1_SEL 350
+#define IMX8QXP_ACM_MCLKOUT1_CLK 351
+#define IMX8QXP_ACM_ESAI0_MCLK_SEL 352
+#define IMX8QXP_ACM_ESAI0_MCLK_CLK 353
+#define IMX8QXP_ACM_GPT0_MUX_CLK_SEL 354
+#define IMX8QXP_ACM_GPT0_MUX_CLK_CLK 355
+#define IMX8QXP_ACM_GPT1_MUX_CLK_SEL 356
+#define IMX8QXP_ACM_GPT1_MUX_CLK_CLK 357
+#define IMX8QXP_ACM_GPT2_MUX_CLK_SEL 358
+#define IMX8QXP_ACM_GPT2_MUX_CLK_CLK 359
+#define IMX8QXP_ACM_GPT3_MUX_CLK_SEL 360
+#define IMX8QXP_ACM_GPT3_MUX_CLK_CLK 361
+#define IMX8QXP_ACM_GPT4_MUX_CLK_SEL 362
+#define IMX8QXP_ACM_GPT4_MUX_CLK_CLK 363
+#define IMX8QXP_ACM_GPT5_MUX_CLK_SEL 364
+#define IMX8QXP_ACM_GPT5_MUX_CLK_CLK 365
+#define IMX8QXP_ACM_SAI0_MCLK_SEL 366
+#define IMX8QXP_ACM_SAI0_MCLK_CLK 367
+#define IMX8QXP_ACM_SAI1_MCLK_SEL 368
+#define IMX8QXP_ACM_SAI1_MCLK_CLK 369
+#define IMX8QXP_ACM_SAI2_MCLK_SEL 370
+#define IMX8QXP_ACM_SAI2_MCLK_CLK 371
+#define IMX8QXP_ACM_SAI3_MCLK_SEL 372
+#define IMX8QXP_ACM_SAI3_MCLK_CLK 373
+#define IMX8QXP_ACM_SAI4_MCLK_SEL 374
+#define IMX8QXP_ACM_SAI4_MCLK_CLK 375
+#define IMX8QXP_ACM_SAI5_MCLK_SEL 376
+#define IMX8QXP_ACM_SAI5_MCLK_CLK 377
+#define IMX8QXP_ACM_SPDIF0_TX_CLK_SEL 378
+#define IMX8QXP_ACM_SPDIF0_TX_CLK_CLK 379
+#define IMX8QXP_ACM_MQS_TX_CLK_SEL 380
+#define IMX8QXP_ACM_MQS_TX_CLK_CLK 381
+#define IMX8QXP_ACM_ASRC0_MUX_CLK_SEL 382
+#define IMX8QXP_ACM_ASRC1_MUX_CLK_SEL 383
+#define IMX8QXP_ACM_ASRC0_MUX_CLK_CLK 384
+#define IMX8QXP_ACM_ASRC1_MUX_CLK_CLK 385
+
+#define IMX8QXP_IPG_AUD_CLK_ROOT 386
+
+/* Audio */
+#define IMX8QXP_AUD_PLL0_DIV 387
+#define IMX8QXP_AUD_PLL0 388
+#define IMX8QXP_AUD_PLL1_DIV 389
+#define IMX8QXP_AUD_PLL1 390
+#define IMX8QXP_AUD_AMIX_IPG 391
+#define IMX8QXP_AUD_ESAI_0_IPG 392
+#define IMX8QXP_AUD_ESAI_0_EXTAL_IPG 393
+#define IMX8QXP_AUD_SAI_0_IPG 394
+#define IMX8QXP_AUD_SAI_0_MCLK 395
+#define IMX8QXP_AUD_SAI_1_IPG 396
+#define IMX8QXP_AUD_SAI_1_MCLK 397
+#define IMX8QXP_AUD_SAI_2_IPG 398
+#define IMX8QXP_AUD_SAI_2_MCLK 399
+#define IMX8QXP_AUD_SAI_3_IPG 400
+#define IMX8QXP_AUD_SAI_3_MCLK 401
+#define IMX8QXP_AUD_SAI_4_IPG 402
+#define IMX8QXP_AUD_SAI_4_MCLK 403
+#define IMX8QXP_AUD_SAI_5_IPG 404
+#define IMX8QXP_AUD_SAI_5_MCLK 405
+#define IMX8QXP_AUD_MQS_IPG 406
+#define IMX8QXP_AUD_MQS_HMCLK 407
+#define IMX8QXP_AUD_GPT5_IPG 408
+#define IMX8QXP_AUD_GPT5_CLKIN 409
+#define IMX8QXP_AUD_GPT6_IPG 410
+#define IMX8QXP_AUD_GPT6_CLKIN 411
+#define IMX8QXP_AUD_GPT7_IPG 412
+#define IMX8QXP_AUD_GPT7_CLKIN 413
+#define IMX8QXP_AUD_GPT8_IPG 414
+#define IMX8QXP_AUD_GPT8_CLKIN 415
+#define IMX8QXP_AUD_GPT9_IPG 416
+#define IMX8QXP_AUD_GPT9_CLKIN 417
+#define IMX8QXP_AUD_GPT10_IPG 418
+#define IMX8QXP_AUD_GPT10_CLKIN 419
+#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV 420
+#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK 421
+#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV 422
+#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK 423
+#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV 424
+#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_CLK 425
+#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV 426
+#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_CLK 427
+#define IMX8QXP_AUD_MCLKOUT0 428
+#define IMX8QXP_AUD_MCLKOUT1 429
+#define IMX8QXP_AUD_SPDIF_0_TX_CLK 430
+#define IMX8QXP_AUD_SPDIF_0_GCLKW 431
+#define IMX8QXP_AUD_SPDIF_0_IPG 432
+#define IMX8QXP_AUD_ASRC_0_IPG 433
+#define IMX8QXP_AUD_ASRC_1_IPG 434
+#define IMX8QXP_AUD_HIFI_ADB_ACLK 435
+#define IMX8QXP_AUD_HIFI_IPG 436
+#define IMX8QXP_AUD_HIFI_CORE_CLK 437
+#define IMX8QXP_AUD_OCRAM_IPG 438
+
+/* DC part2 */
+#define IMX8QXP_DC0_DISP0_DIV 439
+#define IMX8QXP_DC0_DISP1_DIV 440
+#define IMX8QXP_DC0_BYPASS_0_DIV 441
+#define IMX8QXP_DC0_BYPASS_1_DIV 442
+#define IMX8QXP_DC0_PLL0_DIV 443
+#define IMX8QXP_DC0_PLL1_DIV 444
+#define IMX8QXP_DC0_PLL0_CLK 445
+#define IMX8QXP_DC0_PLL1_CLK 446
+
+/* MIPI-LVDS part2 */
+#define IMX8QXP_MIPI0_BYPASS_CLK 447
+#define IMX8QXP_MIPI0_PIXEL_DIV 448
+#define IMX8QXP_MIPI0_PIXEL_CLK 449
+#define IMX8QXP_MIPI0_LVDS_PIXEL_DIV 450
+#define IMX8QXP_MIPI0_LVDS_PIXEL_CLK 451
+#define IMX8QXP_MIPI0_LVDS_BYPASS_CLK 452
+#define IMX8QXP_MIPI0_LVDS_PHY_DIV 453
+#define IMX8QXP_MIPI0_LVDS_PHY_CLK 454
+#define IMX8QXP_MIPI0_LIS_IPG_CLK 455
+#define IMX8QXP_MIPI1_I2C0_DIV 456
+#define IMX8QXP_MIPI1_I2C1_DIV 457
+#define IMX8QXP_MIPI1_I2C0_CLK 458
+#define IMX8QXP_MIPI1_I2C1_CLK 459
+#define IMX8QXP_MIPI1_I2C0_IPG_S_CLK 460
+#define IMX8QXP_MIPI1_I2C0_IPG_CLK 461
+#define IMX8QXP_MIPI1_I2C1_IPG_S_CLK 462
+#define IMX8QXP_MIPI1_I2C1_IPG_CLK 463
+#define IMX8QXP_MIPI1_PWM_IPG_S_CLK 464
+#define IMX8QXP_MIPI1_PWM_IPG_CLK 465
+#define IMX8QXP_MIPI1_PWM_32K_CLK 466
+#define IMX8QXP_MIPI1_GPIO_IPG_CLK 467
+#define IMX8QXP_MIPI1_BYPASS_CLK 468
+#define IMX8QXP_MIPI1_PIXEL_DIV 469
+#define IMX8QXP_MIPI1_PIXEL_CLK 470
+#define IMX8QXP_MIPI1_LVDS_PIXEL_DIV 471
+#define IMX8QXP_MIPI1_LVDS_PIXEL_CLK 472
+#define IMX8QXP_MIPI1_LVDS_BYPASS_CLK 473
+#define IMX8QXP_MIPI1_LVDS_PHY_DIV 474
+#define IMX8QXP_MIPI1_LVDS_PHY_CLK 475
+#define IMX8QXP_MIPI1_LIS_IPG_CLK 476
+
+/* CM40 */
+#define IMX8QXP_CM40_IPG_CLK 477
+#define IMX8QXP_CM40_I2C_DIV 478
+#define IMX8QXP_CM40_I2C_CLK 479
+#define IMX8QXP_CM40_I2C_IPG_CLK 480
+
+#define IMX8QXP_CLK_END 481
+#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */
diff --git a/include/dt-bindings/soc/imx8_pd.h b/include/dt-bindings/soc/imx8_pd.h
new file mode 100644
index 0000000000..ef685fe73b
--- /dev/null
+++ b/include/dt-bindings/soc/imx8_pd.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_IMX8_PD_H
+#define __DT_BINDINGS_IMX8_PD_H
+
+/*!
+ * These defines are used to indicate a resource. Resources include peripherals
+ * and bus masters (but not memory regions). Note items from list should
+ * never be changed or removed (only added to at the end of the list).
+ */
+#define PD_DC_0 dc0_power_domain
+#define PD_DC_0_PLL_0 dc0_pll0
+#define PD_DC_0_PLL_1 dc0_pll1
+#define PD_LVDS0 lvds0_power_domain
+#define PD_LVDS0_I2C0 lvds0_i2c0
+#define PD_LVDS0_I2C1 lvds0_i2c1
+#define PD_LVDS0_PWM lvds0_pwm
+#define PD_LVDS0_PWM lvds0_pwm
+#define PD_LVDS0_GPIO lvds0_gpio
+#define PD_DC_1 dc1_power_domain
+#define PD_DC_1_PLL_0 dc1_pll0
+#define PD_DC_1_PLL_1 dc1_pll1
+#define PD_LVDS1 lvds1_power_domain
+#define PD_LVDS1_I2C0 lvds1_i2c0
+#define PD_LVDS1_I2C1 lvds1_i2c1
+#define PD_LVDS1_PWM lvds1_pwm
+#define PD_LVDS1_GPIO lvds1_gpio
+
+#define PD_DMA dma_power_domain
+#define PD_DMA_SPI_0 dma_spi0
+#define PD_DMA_SPI_1 dma_spi1
+#define PD_DMA_SPI_2 dma_spi2
+#define PD_DMA_SPI_3 dma_spi3
+#define PD_DMA_UART0 dma_lpuart0
+#define PD_DMA_UART1 dma_lpuart1
+#define PD_DMA_UART2 dma_lpuart2
+#define PD_DMA_UART3 dma_lpuart3
+#define PD_DMA_UART4 dma_lpuart4
+#define PD_DMA_EMVSIM_0 dma_emvsim0
+#define PD_DMA_EMVSIM_1 dma_emvsim1
+#define PD_DMA_I2C_0 dma_lpi2c0
+#define PD_DMA_I2C_1 dma_lpi2c1
+#define PD_DMA_I2C_2 dma_lpi2c2
+#define PD_DMA_I2C_3 dma_lpi2c3
+#define PD_DMA_I2C_4 dma_lpi2c4
+#define PD_DMA_ADC_0 dma_adc0
+#define PD_DMA_ADC_1 dma_adc1
+#define PD_DMA_FTM_0 dma_ftm0
+#define PD_DMA_FTM_1 dma_ftm1
+#define PD_DMA_CAN_0 dma_flexcan0
+#define PD_DMA_CAN_1 dma_flexcan1
+#define PD_DMA_CAN_2 dma_flexcan2
+#define PD_DMA_PWM_0 dma_pwm0
+#define PD_DMA_LCD_0 dma_lcd0
+
+#define PD_HSIO hsio_power_domain
+#define PD_HSIO_PCIE_A hsio_pcie0
+#define PD_HSIO_PCIE_B hsio_pcie1
+#define PD_HSIO_SATA_0 hsio_sata0
+#define PD_HSIO_GPIO hsio_gpio
+
+#define PD_LCD_0 lcd0_power_domain
+#define PD_LCD_0_I2C_0 lcd0_i2c0
+#define PD_LCD_0_I2C_1 lcd0_i2c1
+#define PD_LCD_PWM_0 lcd0_pwm0
+
+#define PD_LSIO lsio_power_domain
+#define PD_LSIO_GPIO_0 lsio_gpio0
+#define PD_LSIO_GPIO_1 lsio_gpio1
+#define PD_LSIO_GPIO_2 lsio_gpio2
+#define PD_LSIO_GPIO_3 lsio_gpio3
+#define PD_LSIO_GPIO_4 lsio_gpio4
+#define PD_LSIO_GPIO_5 lsio_gpio5
+#define PD_LSIO_GPIO_6 lsio_gpio6
+#define PD_LSIO_GPIO_7 lsio_gpio7
+#define PD_LSIO_GPT_0 lsio_gpt0
+#define PD_LSIO_GPT_1 lsio_gpt1
+#define PD_LSIO_GPT_2 lsio_gpt2
+#define PD_LSIO_GPT_3 lsio_gpt3
+#define PD_LSIO_GPT_4 lsio_gpt4
+#define PD_LSIO_KPP lsio_kpp
+#define PD_LSIO_FSPI_0 lsio_fspi0
+#define PD_LSIO_FSPI_1 lsio_fspi1
+#define PD_LSIO_PWM_0 lsio_pwm0
+#define PD_LSIO_PWM_1 lsio_pwm1
+#define PD_LSIO_PWM_2 lsio_pwm2
+#define PD_LSIO_PWM_3 lsio_pwm3
+#define PD_LSIO_PWM_4 lsio_pwm4
+#define PD_LSIO_PWM_5 lsio_pwm5
+#define PD_LSIO_PWM_6 lsio_pwm6
+#define PD_LSIO_PWM_7 lsio_pwm7
+
+#define PD_CONN connectivity_power_domain
+#define PD_CONN_SDHC_0 conn_sdhc0
+#define PD_CONN_SDHC_1 conn_sdhc1
+#define PD_CONN_SDHC_2 conn_sdhc2
+#define PD_CONN_ENET_0 conn_enet0
+#define PD_CONN_ENET_1 conn_enet1
+#define PD_CONN_MLB_0 conn_mlb0
+#define PD_CONN_DMA_4_CH0 conn_dma4_ch0
+#define PD_CONN_DMA_4_CH1 conn_dma4_ch1
+#define PD_CONN_DMA_4_CH2 conn_dma4_ch2
+#define PD_CONN_DMA_4_CH3 conn_dma4_ch3
+#define PD_CONN_DMA_4_CH4 conn_dma4_ch4
+#define PD_CONN_USB_0 conn_usb0
+#define PD_CONN_USB_1 conn_usb1
+#define PD_CONN_USB_0_PHY conn_usb0_phy
+#define PD_CONN_USB_2 conn_usb2
+#define PD_CONN_USB_2_PHY conn_usb2_phy
+#define PD_CONN_NAND conn_nand
+
+#define PD_AUDIO audio_power_domain
+#define PD_AUD_SAI_0 audio_sai0
+#define PD_AUD_SAI_1 audio_sai1
+#define PD_AUD_SAI_2 audio_sai2
+#define PD_AUD_ASRC_0 audio_asrc0
+#define PD_AUD_ASRC_1 audio_asrc1
+#define PD_AUD_ESAI_0 audio_esai0
+#define PD_AUD_ESAI_1 audio_esai1
+#define PD_AUD_SPDIF_0 audio_spdif0
+#define PD_AUD_SPDIF_1 audio_spdif1
+#define PD_AUD_SAI_3 audio_sai3
+#define PD_AUD_SAI_4 audio_sai4
+#define PD_AUD_SAI_5 audio_sai5
+#define PD_AUD_SAI_6 audio_sai6
+#define PD_AUD_SAI_7 audio_sai7
+#define PD_AUD_GPT_5 audio_gpt5
+#define PD_AUD_GPT_6 audio_gpt6
+#define PD_AUD_GPT_7 audio_gpt7
+#define PD_AUD_GPT_8 audio_gpt8
+#define PD_AUD_GPT_9 audio_gpt9
+#define PD_AUD_GPT_10 audio_gpt10
+#define PD_AUD_AMIX audio_amix
+#define PD_AUD_MQS_0 audio_mqs0
+#define PD_AUD_HIFI audio_hifi
+#define PD_AUD_OCRAM audio_ocram
+#define PD_AUD_MCLK_OUT_0 audio_mclkout0
+#define PD_AUD_MCLK_OUT_1 audio_mclkout1
+#define PD_AUD_AUDIO_PLL_0 audio_audiopll0
+#define PD_AUD_AUDIO_PLL_1 audio_audiopll1
+#define PD_AUD_AUDIO_CLK_0 audio_audioclk0
+#define PD_AUD_AUDIO_CLK_1 audio_audioclk1
+
+#define PD_IMAGING imaging_power_domain
+#define PD_IMAGING_JPEG_DEC imaging_jpeg_dec
+#define PD_IMAGING_JPEG_ENC imaging_jpeg_enc
+#define PD_IMAGING_PDMA0 PD_IMAGING
+#define PD_IMAGING_PDMA1 imaging_pdma1
+#define PD_IMAGING_PDMA2 imaging_pdma2
+#define PD_IMAGING_PDMA3 imaging_pdma3
+#define PD_IMAGING_PDMA4 imaging_pdma4
+#define PD_IMAGING_PDMA5 imaging_pdma5
+#define PD_IMAGING_PDMA6 imaging_pdma6
+#define PD_IMAGING_PDMA7 imaging_pdma7
+
+#define PD_MIPI_0_DSI mipi0_dsi_power_domain
+#define PD_MIPI_0_DSI_I2C0 mipi0_dsi_i2c0
+#define PD_MIPI_0_DSI_I2C1 mipi0_dsi_i2c1
+#define PD_MIPI_0_DSI_PWM0 mipi0_dsi_pwm0
+#define PD_MIPI_1_DSI mipi1_dsi_power_domain
+#define PD_MIPI_1_DSI_I2C0 mipi1_dsi_i2c0
+#define PD_MIPI_1_DSI_I2C1 mipi1_dsi_i2c1
+#define PD_MIPI_1_DSI_PWM0 mipi1_dsi_pwm0
+
+#define PD_MIPI_CSI0 mipi_csi0_power_domain
+#define PD_MIPI_CSI0_PWM mipi_csi0_pwm
+#define PD_MIPI_CSI0_I2C mipi_csi0_i2c
+#define PD_MIPI_CSI1 mipi_csi1_power_domain
+#define PD_MIPI_CSI1_PWM_0 mipi_csi1_pwm
+#define PD_MIPI_CSI1_I2C_0 mipi_csi1_i2c
+
+#define PD_HDMI hdmi_power_domain
+#define PD_HDMI_I2C_0 hdmi_i2c
+#define PD_HDMI_PWM_0 hdmi_pwm
+#define PD_HDMI_GPIO_0 hdmi_gpio
+
+#define PD_HDMI_RX hdmi_rx_power_domain
+#define PD_HDMI_RX_I2C hdmi_rx_i2c
+#define PD_HDMI_RX_PWM hdmi_rx_pwm
+
+#define PD_CM40 cm40_power_domain
+#define PD_CM40_I2C cm40_i2c
+#define PD_CM40_INTMUX cm40_intmux
+
+#endif /* __DT_BINDINGS_IMX8_PD_H */
--
2.14.1
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