[U-Boot] [PATCH 01/41] imx: import SCFW API

Peng Fan peng.fan at nxp.com
Mon May 28 12:24:46 UTC 2018


The SCFW API files are generated from scfw source code and imported
to U-Boot source code withou code changes.

The commit in SCFW is
commit a5759de95691("SCF-69 Fix the voltage for 1.06GHz setpoint on A72.")

Signed-off-by: Peng Fan <peng.fan at nxp.com>
---
 arch/arm/include/asm/arch-imx8/imx8qm_pads.h       | 295 +++++++
 arch/arm/include/asm/arch-imx8/imx8qxp_pads.h      | 200 +++++
 arch/arm/include/asm/arch-imx8/sci/ipc.h           |  67 ++
 arch/arm/include/asm/arch-imx8/sci/rpc.h           | 131 +++
 arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h   | 160 ++++
 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h  | 523 +++++++++++
 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h   | 568 ++++++++++++
 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h    | 686 +++++++++++++++
 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h    | 759 ++++++++++++++++
 arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h | 306 +++++++
 arch/arm/include/asm/arch-imx8/sci/types.h         | 862 ++++++++++++++++++
 arch/arm/mach-imx/imx8/Makefile                    |  11 +
 arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h           |  54 ++
 arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c      |  76 ++
 arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h          |  76 ++
 arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c     | 515 +++++++++++
 arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h           |  68 ++
 arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c      | 475 ++++++++++
 arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h            |  73 ++
 arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c       | 460 ++++++++++
 arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h            |  83 ++
 arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c       | 645 ++++++++++++++
 arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h         |  67 ++
 arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c    | 365 ++++++++
 include/dt-bindings/pinctrl/pads-imx8qm.h          | 975 +++++++++++++++++++++
 include/dt-bindings/pinctrl/pads-imx8qxp.h         | 770 ++++++++++++++++
 include/dt-bindings/soc/imx_rsrc.h                 | 560 ++++++++++++
 27 files changed, 9830 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-imx8/imx8qm_pads.h
 create mode 100644 arch/arm/include/asm/arch-imx8/imx8qxp_pads.h
 create mode 100755 arch/arm/include/asm/arch-imx8/sci/ipc.h
 create mode 100755 arch/arm/include/asm/arch-imx8/sci/rpc.h
 create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h
 create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
 create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
 create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h
 create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h
 create mode 100755 arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h
 create mode 100755 arch/arm/include/asm/arch-imx8/sci/types.h
 create mode 100644 arch/arm/mach-imx/imx8/Makefile
 create mode 100644 arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h
 create mode 100644 arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c
 create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h
 create mode 100644 arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c
 create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h
 create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c
 create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h
 create mode 100644 arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c
 create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h
 create mode 100644 arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c
 create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h
 create mode 100644 arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c
 create mode 100644 include/dt-bindings/pinctrl/pads-imx8qm.h
 create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
 create mode 100644 include/dt-bindings/soc/imx_rsrc.h

diff --git a/arch/arm/include/asm/arch-imx8/imx8qm_pads.h b/arch/arm/include/asm/arch-imx8/imx8qm_pads.h
new file mode 100644
index 0000000000..5cd2b76759
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/imx8qm_pads.h
@@ -0,0 +1,295 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file used to configure SoC pad list.
+ */
+
+#ifndef SC_PADS_H
+#define SC_PADS_H
+
+/* Includes */
+
+/* Defines */
+
+/*!
+ * @name Pad Definitions
+ */
+/*@{*/
+#define SC_P_SIM0_CLK                            0    /*!< DMA.SIM0.CLK, LSIO.GPIO0.IO00 */
+#define SC_P_SIM0_RST                            1    /*!< DMA.SIM0.RST, LSIO.GPIO0.IO01 */
+#define SC_P_SIM0_IO                             2    /*!< DMA.SIM0.IO, LSIO.GPIO0.IO02 */
+#define SC_P_SIM0_PD                             3    /*!< DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */
+#define SC_P_SIM0_POWER_EN                       4    /*!< DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */
+#define SC_P_SIM0_GPIO0_00                       5    /*!< DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM           6    /*!<  */
+#define SC_P_M40_I2C0_SCL                        7    /*!< M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */
+#define SC_P_M40_I2C0_SDA                        8    /*!< M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */
+#define SC_P_M40_GPIO0_00                        9    /*!< M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */
+#define SC_P_M40_GPIO0_01                        10   /*!< M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */
+#define SC_P_M41_I2C0_SCL                        11   /*!< M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */
+#define SC_P_M41_I2C0_SDA                        12   /*!< M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */
+#define SC_P_M41_GPIO0_00                        13   /*!< M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */
+#define SC_P_M41_GPIO0_01                        14   /*!< M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */
+#define SC_P_GPT0_CLK                            15   /*!< LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */
+#define SC_P_GPT0_CAPTURE                        16   /*!< LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */
+#define SC_P_GPT0_COMPARE                        17   /*!< LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */
+#define SC_P_GPT1_CLK                            18   /*!< LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
+#define SC_P_GPT1_CAPTURE                        19   /*!< LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */
+#define SC_P_GPT1_COMPARE                        20   /*!< LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
+#define SC_P_UART0_RX                            21   /*!< DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */
+#define SC_P_UART0_TX                            22   /*!< DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */
+#define SC_P_UART0_RTS_B                         23   /*!< DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */
+#define SC_P_UART0_CTS_B                         24   /*!< DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */
+#define SC_P_UART1_TX                            25   /*!< DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */
+#define SC_P_UART1_RX                            26   /*!< DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */
+#define SC_P_UART1_RTS_B                         27   /*!< DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */
+#define SC_P_UART1_CTS_B                         28   /*!< DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH        29   /*!<  */
+#define SC_P_SCU_PMIC_MEMC_ON                    30   /*!< SCU.GPIO0.IOXX_PMIC_MEMC_ON */
+#define SC_P_SCU_WDOG_OUT                        31   /*!< SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SDA                        32   /*!< SCU.PMIC_I2C.SDA */
+#define SC_P_PMIC_I2C_SCL                        33   /*!< SCU.PMIC_I2C.SCL */
+#define SC_P_PMIC_EARLY_WARNING                  34   /*!< SCU.PMIC_EARLY_WARNING */
+#define SC_P_PMIC_INT_B                          35   /*!< SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00                        36   /*!< SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */
+#define SC_P_SCU_GPIO0_01                        37   /*!< SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */
+#define SC_P_SCU_GPIO0_02                        38   /*!< SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */
+#define SC_P_SCU_GPIO0_03                        39   /*!< SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */
+#define SC_P_SCU_GPIO0_04                        40   /*!< SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */
+#define SC_P_SCU_GPIO0_05                        41   /*!< SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */
+#define SC_P_SCU_GPIO0_06                        42   /*!< SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */
+#define SC_P_SCU_GPIO0_07                        43   /*!< SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */
+#define SC_P_SCU_BOOT_MODE0                      44   /*!< SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE1                      45   /*!< SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE2                      46   /*!< SCU.DSC.BOOT_MODE2 */
+#define SC_P_SCU_BOOT_MODE3                      47   /*!< SCU.DSC.BOOT_MODE3 */
+#define SC_P_SCU_BOOT_MODE4                      48   /*!< SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
+#define SC_P_SCU_BOOT_MODE5                      49   /*!< SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
+#define SC_P_LVDS0_GPIO00                        50   /*!< LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
+#define SC_P_LVDS0_GPIO01                        51   /*!< LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
+#define SC_P_LVDS0_I2C0_SCL                      52   /*!< LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
+#define SC_P_LVDS0_I2C0_SDA                      53   /*!< LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
+#define SC_P_LVDS0_I2C1_SCL                      54   /*!< LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
+#define SC_P_LVDS0_I2C1_SDA                      55   /*!< LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
+#define SC_P_LVDS1_GPIO00                        56   /*!< LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
+#define SC_P_LVDS1_GPIO01                        57   /*!< LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
+#define SC_P_LVDS1_I2C0_SCL                      58   /*!< LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
+#define SC_P_LVDS1_I2C0_SDA                      59   /*!< LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
+#define SC_P_LVDS1_I2C1_SCL                      60   /*!< LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
+#define SC_P_LVDS1_I2C1_SDA                      61   /*!< LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO      62   /*!<  */
+#define SC_P_MIPI_DSI0_I2C0_SCL                  63   /*!< MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
+#define SC_P_MIPI_DSI0_I2C0_SDA                  64   /*!< MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
+#define SC_P_MIPI_DSI0_GPIO0_00                  65   /*!< MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */
+#define SC_P_MIPI_DSI0_GPIO0_01                  66   /*!< MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
+#define SC_P_MIPI_DSI1_I2C0_SCL                  67   /*!< MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
+#define SC_P_MIPI_DSI1_I2C0_SDA                  68   /*!< MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
+#define SC_P_MIPI_DSI1_GPIO0_00                  69   /*!< MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */
+#define SC_P_MIPI_DSI1_GPIO0_01                  70   /*!< MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO   71   /*!<  */
+#define SC_P_MIPI_CSI0_MCLK_OUT                  72   /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
+#define SC_P_MIPI_CSI0_I2C0_SCL                  73   /*!< MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */
+#define SC_P_MIPI_CSI0_I2C0_SDA                  74   /*!< MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */
+#define SC_P_MIPI_CSI0_GPIO0_00                  75   /*!< MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_CSI0_GPIO0_01                  76   /*!< MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_CSI1_MCLK_OUT                  77   /*!< MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
+#define SC_P_MIPI_CSI1_GPIO0_00                  78   /*!< MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
+#define SC_P_MIPI_CSI1_GPIO0_01                  79   /*!< MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
+#define SC_P_MIPI_CSI1_I2C0_SCL                  80   /*!< MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
+#define SC_P_MIPI_CSI1_I2C0_SDA                  81   /*!< MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
+#define SC_P_HDMI_TX0_TS_SCL                     82   /*!< HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
+#define SC_P_HDMI_TX0_TS_SDA                     83   /*!< HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
+#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO          84   /*!<  */
+#define SC_P_ESAI1_FSR                           85   /*!< AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
+#define SC_P_ESAI1_FST                           86   /*!< AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */
+#define SC_P_ESAI1_SCKR                          87   /*!< AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
+#define SC_P_ESAI1_SCKT                          88   /*!< AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */
+#define SC_P_ESAI1_TX0                           89   /*!< AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */
+#define SC_P_ESAI1_TX1                           90   /*!< AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */
+#define SC_P_ESAI1_TX2_RX3                       91   /*!< AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */
+#define SC_P_ESAI1_TX3_RX2                       92   /*!< AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */
+#define SC_P_ESAI1_TX4_RX1                       93   /*!< AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */
+#define SC_P_ESAI1_TX5_RX0                       94   /*!< AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */
+#define SC_P_SPDIF0_RX                           95   /*!< AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */
+#define SC_P_SPDIF0_TX                           96   /*!< AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */
+#define SC_P_SPDIF0_EXT_CLK                      97   /*!< AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */
+#define SC_P_SPI3_SCK                            98   /*!< DMA.SPI3.SCK, LSIO.GPIO2.IO17 */
+#define SC_P_SPI3_SDO                            99   /*!< DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */
+#define SC_P_SPI3_SDI                            100  /*!< DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */
+#define SC_P_SPI3_CS0                            101  /*!< DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */
+#define SC_P_SPI3_CS1                            102  /*!< DMA.SPI3.CS1, LSIO.GPIO2.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB       103  /*!<  */
+#define SC_P_ESAI0_FSR                           104  /*!< AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */
+#define SC_P_ESAI0_FST                           105  /*!< AUD.ESAI0.FST, LSIO.GPIO2.IO23 */
+#define SC_P_ESAI0_SCKR                          106  /*!< AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */
+#define SC_P_ESAI0_SCKT                          107  /*!< AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */
+#define SC_P_ESAI0_TX0                           108  /*!< AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */
+#define SC_P_ESAI0_TX1                           109  /*!< AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */
+#define SC_P_ESAI0_TX2_RX3                       110  /*!< AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */
+#define SC_P_ESAI0_TX3_RX2                       111  /*!< AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */
+#define SC_P_ESAI0_TX4_RX1                       112  /*!< AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */
+#define SC_P_ESAI0_TX5_RX0                       113  /*!< AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */
+#define SC_P_MCLK_IN0                            114  /*!< AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */
+#define SC_P_MCLK_OUT0                           115  /*!< AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC       116  /*!<  */
+#define SC_P_SPI0_SCK                            117  /*!< DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */
+#define SC_P_SPI0_SDO                            118  /*!< DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */
+#define SC_P_SPI0_SDI                            119  /*!< DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */
+#define SC_P_SPI0_CS0                            120  /*!< DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */
+#define SC_P_SPI0_CS1                            121  /*!< DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */
+#define SC_P_SPI2_SCK                            122  /*!< DMA.SPI2.SCK, LSIO.GPIO3.IO07 */
+#define SC_P_SPI2_SDO                            123  /*!< DMA.SPI2.SDO, LSIO.GPIO3.IO08 */
+#define SC_P_SPI2_SDI                            124  /*!< DMA.SPI2.SDI, LSIO.GPIO3.IO09 */
+#define SC_P_SPI2_CS0                            125  /*!< DMA.SPI2.CS0, LSIO.GPIO3.IO10 */
+#define SC_P_SPI2_CS1                            126  /*!< DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */
+#define SC_P_SAI1_RXC                            127  /*!< AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */
+#define SC_P_SAI1_RXD                            128  /*!< AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */
+#define SC_P_SAI1_RXFS                           129  /*!< AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */
+#define SC_P_SAI1_TXC                            130  /*!< AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */
+#define SC_P_SAI1_TXD                            131  /*!< AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */
+#define SC_P_SAI1_TXFS                           132  /*!< AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT       133  /*!<  */
+#define SC_P_ADC_IN7                             134  /*!< DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */
+#define SC_P_ADC_IN6                             135  /*!< DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */
+#define SC_P_ADC_IN5                             136  /*!< DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */
+#define SC_P_ADC_IN4                             137  /*!< DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */
+#define SC_P_ADC_IN3                             138  /*!< DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */
+#define SC_P_ADC_IN2                             139  /*!< DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */
+#define SC_P_ADC_IN1                             140  /*!< DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */
+#define SC_P_ADC_IN0                             141  /*!< DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */
+#define SC_P_MLB_SIG                             142  /*!< CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */
+#define SC_P_MLB_CLK                             143  /*!< CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */
+#define SC_P_MLB_DATA                            144  /*!< CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT       145  /*!<  */
+#define SC_P_FLEXCAN0_RX                         146  /*!< DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */
+#define SC_P_FLEXCAN0_TX                         147  /*!< DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */
+#define SC_P_FLEXCAN1_RX                         148  /*!< DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */
+#define SC_P_FLEXCAN1_TX                         149  /*!< DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */
+#define SC_P_FLEXCAN2_RX                         150  /*!< DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */
+#define SC_P_FLEXCAN2_TX                         151  /*!< DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR       152  /*!<  */
+#define SC_P_USB_SS3_TC0                         153  /*!< DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */
+#define SC_P_USB_SS3_TC1                         154  /*!< DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
+#define SC_P_USB_SS3_TC2                         155  /*!< DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */
+#define SC_P_USB_SS3_TC3                         156  /*!< DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO            157  /*!<  */
+#define SC_P_USDHC1_RESET_B                      158  /*!< CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */
+#define SC_P_USDHC1_VSELECT                      159  /*!< CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */
+#define SC_P_USDHC2_RESET_B                      160  /*!< CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */
+#define SC_P_USDHC2_VSELECT                      161  /*!< CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */
+#define SC_P_USDHC2_WP                           162  /*!< CONN.USDHC2.WP, LSIO.GPIO4.IO11 */
+#define SC_P_USDHC2_CD_B                         163  /*!< CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP       164  /*!<  */
+#define SC_P_ENET0_MDIO                          165  /*!< CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */
+#define SC_P_ENET0_MDC                           166  /*!< CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */
+#define SC_P_ENET0_REFCLK_125M_25M               167  /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */
+#define SC_P_ENET1_REFCLK_125M_25M               168  /*!< CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */
+#define SC_P_ENET1_MDIO                          169  /*!< CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */
+#define SC_P_ENET1_MDC                           170  /*!< CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT        171  /*!<  */
+#define SC_P_QSPI1A_SS0_B                        172  /*!< LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */
+#define SC_P_QSPI1A_SS1_B                        173  /*!< LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */
+#define SC_P_QSPI1A_SCLK                         174  /*!< LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */
+#define SC_P_QSPI1A_DQS                          175  /*!< LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */
+#define SC_P_QSPI1A_DATA3                        176  /*!< LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */
+#define SC_P_QSPI1A_DATA2                        177  /*!< LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */
+#define SC_P_QSPI1A_DATA1                        178  /*!< LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */
+#define SC_P_QSPI1A_DATA0                        179  /*!< LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1         180  /*!<  */
+#define SC_P_QSPI0A_DATA0                        181  /*!< LSIO.QSPI0A.DATA0 */
+#define SC_P_QSPI0A_DATA1                        182  /*!< LSIO.QSPI0A.DATA1 */
+#define SC_P_QSPI0A_DATA2                        183  /*!< LSIO.QSPI0A.DATA2 */
+#define SC_P_QSPI0A_DATA3                        184  /*!< LSIO.QSPI0A.DATA3 */
+#define SC_P_QSPI0A_DQS                          185  /*!< LSIO.QSPI0A.DQS */
+#define SC_P_QSPI0A_SS0_B                        186  /*!< LSIO.QSPI0A.SS0_B */
+#define SC_P_QSPI0A_SS1_B                        187  /*!< LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */
+#define SC_P_QSPI0A_SCLK                         188  /*!< LSIO.QSPI0A.SCLK */
+#define SC_P_QSPI0B_SCLK                         189  /*!< LSIO.QSPI0B.SCLK */
+#define SC_P_QSPI0B_DATA0                        190  /*!< LSIO.QSPI0B.DATA0 */
+#define SC_P_QSPI0B_DATA1                        191  /*!< LSIO.QSPI0B.DATA1 */
+#define SC_P_QSPI0B_DATA2                        192  /*!< LSIO.QSPI0B.DATA2 */
+#define SC_P_QSPI0B_DATA3                        193  /*!< LSIO.QSPI0B.DATA3 */
+#define SC_P_QSPI0B_DQS                          194  /*!< LSIO.QSPI0B.DQS */
+#define SC_P_QSPI0B_SS0_B                        195  /*!< LSIO.QSPI0B.SS0_B */
+#define SC_P_QSPI0B_SS1_B                        196  /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0         197  /*!<  */
+#define SC_P_PCIE_CTRL0_CLKREQ_B                 198  /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */
+#define SC_P_PCIE_CTRL0_WAKE_B                   199  /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */
+#define SC_P_PCIE_CTRL0_PERST_B                  200  /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */
+#define SC_P_PCIE_CTRL1_CLKREQ_B                 201  /*!< HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */
+#define SC_P_PCIE_CTRL1_WAKE_B                   202  /*!< HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */
+#define SC_P_PCIE_CTRL1_PERST_B                  203  /*!< HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP       204  /*!<  */
+#define SC_P_USB_HSIC0_DATA                      205  /*!< CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */
+#define SC_P_USB_HSIC0_STROBE                    206  /*!< CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */
+#define SC_P_CALIBRATION_0_HSIC                  207  /*!<  */
+#define SC_P_CALIBRATION_1_HSIC                  208  /*!<  */
+#define SC_P_EMMC0_CLK                           209  /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B */
+#define SC_P_EMMC0_CMD                           210  /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */
+#define SC_P_EMMC0_DATA0                         211  /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */
+#define SC_P_EMMC0_DATA1                         212  /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */
+#define SC_P_EMMC0_DATA2                         213  /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */
+#define SC_P_EMMC0_DATA3                         214  /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */
+#define SC_P_EMMC0_DATA4                         215  /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */
+#define SC_P_EMMC0_DATA5                         216  /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */
+#define SC_P_EMMC0_DATA6                         217  /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */
+#define SC_P_EMMC0_DATA7                         218  /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */
+#define SC_P_EMMC0_STROBE                        219  /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */
+#define SC_P_EMMC0_RESET_B                       220  /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX        221  /*!<  */
+#define SC_P_USDHC1_CLK                          222  /*!< CONN.USDHC1.CLK, AUD.MQS.R */
+#define SC_P_USDHC1_CMD                          223  /*!< CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */
+#define SC_P_USDHC1_DATA0                        224  /*!< CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */
+#define SC_P_USDHC1_DATA1                        225  /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */
+#define SC_P_CTL_NAND_RE_P_N                     226  /*!<  */
+#define SC_P_USDHC1_DATA2                        227  /*!< CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
+#define SC_P_USDHC1_DATA3                        228  /*!< CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
+#define SC_P_CTL_NAND_DQS_P_N                    229  /*!<  */
+#define SC_P_USDHC1_DATA4                        230  /*!< CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */
+#define SC_P_USDHC1_DATA5                        231  /*!< CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */
+#define SC_P_USDHC1_DATA6                        232  /*!< CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
+#define SC_P_USDHC1_DATA7                        233  /*!< CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */
+#define SC_P_USDHC1_STROBE                       234  /*!< CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2         235  /*!<  */
+#define SC_P_USDHC2_CLK                          236  /*!< CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */
+#define SC_P_USDHC2_CMD                          237  /*!< CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */
+#define SC_P_USDHC2_DATA0                        238  /*!< CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */
+#define SC_P_USDHC2_DATA1                        239  /*!< CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */
+#define SC_P_USDHC2_DATA2                        240  /*!< CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */
+#define SC_P_USDHC2_DATA3                        241  /*!< CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3         242  /*!<  */
+#define SC_P_ENET0_RGMII_TXC                     243  /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */
+#define SC_P_ENET0_RGMII_TX_CTL                  244  /*!< CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */
+#define SC_P_ENET0_RGMII_TXD0                    245  /*!< CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */
+#define SC_P_ENET0_RGMII_TXD1                    246  /*!< CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */
+#define SC_P_ENET0_RGMII_TXD2                    247  /*!< CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */
+#define SC_P_ENET0_RGMII_TXD3                    248  /*!< CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */
+#define SC_P_ENET0_RGMII_RXC                     249  /*!< CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */
+#define SC_P_ENET0_RGMII_RX_CTL                  250  /*!< CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */
+#define SC_P_ENET0_RGMII_RXD0                    251  /*!< CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */
+#define SC_P_ENET0_RGMII_RXD1                    252  /*!< CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */
+#define SC_P_ENET0_RGMII_RXD2                    253  /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */
+#define SC_P_ENET0_RGMII_RXD3                    254  /*!< CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB    255  /*!<  */
+#define SC_P_ENET1_RGMII_TXC                     256  /*!< CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */
+#define SC_P_ENET1_RGMII_TX_CTL                  257  /*!< CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */
+#define SC_P_ENET1_RGMII_TXD0                    258  /*!< CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */
+#define SC_P_ENET1_RGMII_TXD1                    259  /*!< CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */
+#define SC_P_ENET1_RGMII_TXD2                    260  /*!< CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */
+#define SC_P_ENET1_RGMII_TXD3                    261  /*!< CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */
+#define SC_P_ENET1_RGMII_RXC                     262  /*!< CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */
+#define SC_P_ENET1_RGMII_RX_CTL                  263  /*!< CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */
+#define SC_P_ENET1_RGMII_RXD0                    264  /*!< CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
+#define SC_P_ENET1_RGMII_RXD1                    265  /*!< CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
+#define SC_P_ENET1_RGMII_RXD2                    266  /*!< CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
+#define SC_P_ENET1_RGMII_RXD3                    267  /*!< CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA    268  /*!<  */
+/*@}*/
+
+#endif /* SC_PADS_H */
+
diff --git a/arch/arm/include/asm/arch-imx8/imx8qxp_pads.h b/arch/arm/include/asm/arch-imx8/imx8qxp_pads.h
new file mode 100644
index 0000000000..8db40c549a
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/imx8qxp_pads.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file used to configure SoC pad list.
+ */
+
+#ifndef SC_PADS_H
+#define SC_PADS_H
+
+/* Includes */
+
+/* Defines */
+
+/*!
+ * @name Pad Definitions
+ */
+/*@{*/
+#define SC_P_PCIE_CTRL0_PERST_B                  0    /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
+#define SC_P_PCIE_CTRL0_CLKREQ_B                 1    /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
+#define SC_P_PCIE_CTRL0_WAKE_B                   2    /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP       3    /*!<  */
+#define SC_P_USB_SS3_TC0                         4    /*!< ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */
+#define SC_P_USB_SS3_TC1                         5    /*!< ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
+#define SC_P_USB_SS3_TC2                         6    /*!< ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */
+#define SC_P_USB_SS3_TC3                         7    /*!< ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO            8    /*!<  */
+#define SC_P_EMMC0_CLK                           9    /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
+#define SC_P_EMMC0_CMD                           10   /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
+#define SC_P_EMMC0_DATA0                         11   /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
+#define SC_P_EMMC0_DATA1                         12   /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
+#define SC_P_EMMC0_DATA2                         13   /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
+#define SC_P_EMMC0_DATA3                         14   /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0       15   /*!<  */
+#define SC_P_EMMC0_DATA4                         16   /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */
+#define SC_P_EMMC0_DATA5                         17   /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */
+#define SC_P_EMMC0_DATA6                         18   /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
+#define SC_P_EMMC0_DATA7                         19   /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */
+#define SC_P_EMMC0_STROBE                        20   /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */
+#define SC_P_EMMC0_RESET_B                       21   /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1       22   /*!<  */
+#define SC_P_USDHC1_RESET_B                      23   /*!< CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */
+#define SC_P_USDHC1_VSELECT                      24   /*!< CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */
+#define SC_P_CTL_NAND_RE_P_N                     25   /*!<  */
+#define SC_P_USDHC1_WP                           26   /*!< CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */
+#define SC_P_USDHC1_CD_B                         27   /*!< CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */
+#define SC_P_CTL_NAND_DQS_P_N                    28   /*!<  */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP       29   /*!<  */
+#define SC_P_USDHC1_CLK                          30   /*!< CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */
+#define SC_P_USDHC1_CMD                          31   /*!< CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */
+#define SC_P_USDHC1_DATA0                        32   /*!< CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */
+#define SC_P_USDHC1_DATA1                        33   /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */
+#define SC_P_USDHC1_DATA2                        34   /*!< CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */
+#define SC_P_USDHC1_DATA3                        35   /*!< CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3         36   /*!<  */
+#define SC_P_ENET0_RGMII_TXC                     37   /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */
+#define SC_P_ENET0_RGMII_TX_CTL                  38   /*!< CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */
+#define SC_P_ENET0_RGMII_TXD0                    39   /*!< CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */
+#define SC_P_ENET0_RGMII_TXD1                    40   /*!< CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */
+#define SC_P_ENET0_RGMII_TXD2                    41   /*!< CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */
+#define SC_P_ENET0_RGMII_TXD3                    42   /*!< CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0   43   /*!<  */
+#define SC_P_ENET0_RGMII_RXC                     44   /*!< CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
+#define SC_P_ENET0_RGMII_RX_CTL                  45   /*!< CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
+#define SC_P_ENET0_RGMII_RXD0                    46   /*!< CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
+#define SC_P_ENET0_RGMII_RXD1                    47   /*!< CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
+#define SC_P_ENET0_RGMII_RXD2                    48   /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
+#define SC_P_ENET0_RGMII_RXD3                    49   /*!< CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1   50   /*!<  */
+#define SC_P_ENET0_REFCLK_125M_25M               51   /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */
+#define SC_P_ENET0_MDIO                          52   /*!< CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */
+#define SC_P_ENET0_MDC                           53   /*!< CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT        54   /*!<  */
+#define SC_P_ESAI0_FSR                           55   /*!< ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */
+#define SC_P_ESAI0_FST                           56   /*!< ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */
+#define SC_P_ESAI0_SCKR                          57   /*!< ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
+#define SC_P_ESAI0_SCKT                          58   /*!< ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */
+#define SC_P_ESAI0_TX0                           59   /*!< ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */
+#define SC_P_ESAI0_TX1                           60   /*!< ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */
+#define SC_P_ESAI0_TX2_RX3                       61   /*!< ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */
+#define SC_P_ESAI0_TX3_RX2                       62   /*!< ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */
+#define SC_P_ESAI0_TX4_RX1                       63   /*!< ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */
+#define SC_P_ESAI0_TX5_RX0                       64   /*!< ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */
+#define SC_P_SPDIF0_RX                           65   /*!< ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */
+#define SC_P_SPDIF0_TX                           66   /*!< ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */
+#define SC_P_SPDIF0_EXT_CLK                      67   /*!< ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB       68   /*!<  */
+#define SC_P_SPI3_SCK                            69   /*!< ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */
+#define SC_P_SPI3_SDO                            70   /*!< ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */
+#define SC_P_SPI3_SDI                            71   /*!< ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */
+#define SC_P_SPI3_CS0                            72   /*!< ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */
+#define SC_P_SPI3_CS1                            73   /*!< ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */
+#define SC_P_MCLK_IN1                            74   /*!< ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */
+#define SC_P_MCLK_IN0                            75   /*!< ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */
+#define SC_P_MCLK_OUT0                           76   /*!< ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */
+#define SC_P_UART1_TX                            77   /*!< ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */
+#define SC_P_UART1_RX                            78   /*!< ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
+#define SC_P_UART1_RTS_B                         79   /*!< ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
+#define SC_P_UART1_CTS_B                         80   /*!< ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK       81   /*!<  */
+#define SC_P_SAI0_TXD                            82   /*!< ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */
+#define SC_P_SAI0_TXC                            83   /*!< ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */
+#define SC_P_SAI0_RXD                            84   /*!< ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */
+#define SC_P_SAI0_TXFS                           85   /*!< ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */
+#define SC_P_SAI1_RXD                            86   /*!< ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */
+#define SC_P_SAI1_RXC                            87   /*!< ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */
+#define SC_P_SAI1_RXFS                           88   /*!< ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */
+#define SC_P_SPI2_CS0                            89   /*!< ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */
+#define SC_P_SPI2_SDO                            90   /*!< ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */
+#define SC_P_SPI2_SDI                            91   /*!< ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */
+#define SC_P_SPI2_SCK                            92   /*!< ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */
+#define SC_P_SPI0_SCK                            93   /*!< ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */
+#define SC_P_SPI0_SDI                            94   /*!< ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */
+#define SC_P_SPI0_SDO                            95   /*!< ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */
+#define SC_P_SPI0_CS1                            96   /*!< ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */
+#define SC_P_SPI0_CS0                            97   /*!< ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT       98   /*!<  */
+#define SC_P_ADC_IN1                             99   /*!< ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */
+#define SC_P_ADC_IN0                             100  /*!< ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */
+#define SC_P_ADC_IN3                             101  /*!< ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */
+#define SC_P_ADC_IN2                             102  /*!< ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */
+#define SC_P_ADC_IN5                             103  /*!< ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */
+#define SC_P_ADC_IN4                             104  /*!< ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */
+#define SC_P_FLEXCAN0_RX                         105  /*!< ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */
+#define SC_P_FLEXCAN0_TX                         106  /*!< ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */
+#define SC_P_FLEXCAN1_RX                         107  /*!< ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */
+#define SC_P_FLEXCAN1_TX                         108  /*!< ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
+#define SC_P_FLEXCAN2_RX                         109  /*!< ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
+#define SC_P_FLEXCAN2_TX                         110  /*!< ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
+#define SC_P_UART0_RX                            111  /*!< ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */
+#define SC_P_UART0_TX                            112  /*!< ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */
+#define SC_P_UART2_TX                            113  /*!< ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
+#define SC_P_UART2_RX                            114  /*!< ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH        115  /*!<  */
+#define SC_P_MIPI_DSI0_I2C0_SCL                  116  /*!< MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */
+#define SC_P_MIPI_DSI0_I2C0_SDA                  117  /*!< MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */
+#define SC_P_MIPI_DSI0_GPIO0_00                  118  /*!< MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_DSI0_GPIO0_01                  119  /*!< MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_DSI1_I2C0_SCL                  120  /*!< MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */
+#define SC_P_MIPI_DSI1_I2C0_SDA                  121  /*!< MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */
+#define SC_P_MIPI_DSI1_GPIO0_00                  122  /*!< MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */
+#define SC_P_MIPI_DSI1_GPIO0_01                  123  /*!< MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO   124  /*!<  */
+#define SC_P_JTAG_TRST_B                         125  /*!< SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SCL                        126  /*!< SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
+#define SC_P_PMIC_I2C_SDA                        127  /*!< SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
+#define SC_P_PMIC_INT_B                          128  /*!< SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00                        129  /*!< SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
+#define SC_P_SCU_GPIO0_01                        130  /*!< SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
+#define SC_P_SCU_PMIC_STANDBY                    131  /*!< SCU.DSC.PMIC_STANDBY */
+#define SC_P_SCU_BOOT_MODE0                      132  /*!< SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE1                      133  /*!< SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE2                      134  /*!< SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */
+#define SC_P_SCU_BOOT_MODE3                      135  /*!< SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
+#define SC_P_CSI_D00                             136  /*!< CI_PI.D02, ADMA.SAI0.RXC */
+#define SC_P_CSI_D01                             137  /*!< CI_PI.D03, ADMA.SAI0.RXD */
+#define SC_P_CSI_D02                             138  /*!< CI_PI.D04, ADMA.SAI0.RXFS */
+#define SC_P_CSI_D03                             139  /*!< CI_PI.D05, ADMA.SAI2.RXC */
+#define SC_P_CSI_D04                             140  /*!< CI_PI.D06, ADMA.SAI2.RXD */
+#define SC_P_CSI_D05                             141  /*!< CI_PI.D07, ADMA.SAI2.RXFS */
+#define SC_P_CSI_D06                             142  /*!< CI_PI.D08, ADMA.SAI3.RXC */
+#define SC_P_CSI_D07                             143  /*!< CI_PI.D09, ADMA.SAI3.RXD */
+#define SC_P_CSI_HSYNC                           144  /*!< CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */
+#define SC_P_CSI_VSYNC                           145  /*!< CI_PI.VSYNC, CI_PI.D01 */
+#define SC_P_CSI_PCLK                            146  /*!< CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
+#define SC_P_CSI_MCLK                            147  /*!< CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
+#define SC_P_CSI_EN                              148  /*!< CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
+#define SC_P_CSI_RESET                           149  /*!< CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD       150  /*!<  */
+#define SC_P_MIPI_CSI0_MCLK_OUT                  151  /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */
+#define SC_P_MIPI_CSI0_I2C0_SCL                  152  /*!< MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */
+#define SC_P_MIPI_CSI0_I2C0_SDA                  153  /*!< MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */
+#define SC_P_MIPI_CSI0_GPIO0_01                  154  /*!< MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */
+#define SC_P_MIPI_CSI0_GPIO0_00                  155  /*!< MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */
+#define SC_P_QSPI0A_DATA0                        156  /*!< LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
+#define SC_P_QSPI0A_DATA1                        157  /*!< LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
+#define SC_P_QSPI0A_DATA2                        158  /*!< LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
+#define SC_P_QSPI0A_DATA3                        159  /*!< LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
+#define SC_P_QSPI0A_DQS                          160  /*!< LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
+#define SC_P_QSPI0A_SS0_B                        161  /*!< LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
+#define SC_P_QSPI0A_SS1_B                        162  /*!< LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */
+#define SC_P_QSPI0A_SCLK                         163  /*!< LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A        164  /*!<  */
+#define SC_P_QSPI0B_SCLK                         165  /*!< LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */
+#define SC_P_QSPI0B_DATA0                        166  /*!< LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */
+#define SC_P_QSPI0B_DATA1                        167  /*!< LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */
+#define SC_P_QSPI0B_DATA2                        168  /*!< LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */
+#define SC_P_QSPI0B_DATA3                        169  /*!< LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */
+#define SC_P_QSPI0B_DQS                          170  /*!< LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */
+#define SC_P_QSPI0B_SS0_B                        171  /*!< LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */
+#define SC_P_QSPI0B_SS1_B                        172  /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B        173  /*!<  */
+/*@}*/
+
+#endif /* SC_PADS_H */
+
diff --git a/arch/arm/include/asm/arch-imx8/sci/ipc.h b/arch/arm/include/asm/arch-imx8/sci/ipc.h
new file mode 100755
index 0000000000..3759ac4c45
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/ipc.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file for the IPC implementation.
+ */
+
+#ifndef SC_IPC_H
+#define SC_IPC_H
+
+/* Includes */
+
+#include <asm/arch/sci/types.h>
+
+/* Defines */
+
+/* Types */
+
+/* Functions */
+
+/*!
+ * This function opens an IPC channel.
+ *
+ * @param[out]    ipc         return pointer for ipc handle
+ * @param[in]     id          id of channel to open
+ *
+ * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_IPC
+ *         otherwise).
+ *
+ * The \a id parameter is implementation specific. Could be an MU
+ * address, pointer to a driver path, channel index, etc.
+ */
+sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id);
+
+/*!
+ * This function closes an IPC channel.
+ *
+ * @param[in]     ipc         id of channel to close
+ */
+void sc_ipc_close(sc_ipc_t ipc);
+
+/*!
+ * This function reads a message from an IPC channel.
+ *
+ * @param[in]     ipc         id of channel read from
+ * @param[out]    data        pointer to message buffer to read
+ *
+ * This function will block if no message is available to be read.
+ */
+void sc_ipc_read(sc_ipc_t ipc, void *data);
+
+/*!
+ * This function writes a message to an IPC channel.
+ *
+ * @param[in]     ipc         id of channel to write to
+ * @param[in]     data        pointer to message buffer to write
+ *
+ * This function will block if the outgoing buffer is full.
+ */
+void sc_ipc_write(sc_ipc_t ipc, void *data);
+
+#endif /* SC_IPC_H */
+
diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h
new file mode 100755
index 0000000000..afb891e2c5
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file for the RPC implementation.
+ */
+
+#ifndef SC_RPC_H
+#define SC_RPC_H
+
+/* Includes */
+
+#include <asm/arch/sci/types.h>
+#include <asm/arch/sci/ipc.h>
+
+/* Defines */
+
+#define SC_RPC_VERSION          1U
+
+#define SC_RPC_MAX_MSG          8U
+
+#define RPC_VER(MSG)            ((MSG)->version)
+#define RPC_SIZE(MSG)           ((MSG)->size)
+#define RPC_SVC(MSG)            ((MSG)->svc)
+#define RPC_FUNC(MSG)           ((MSG)->func)
+#define RPC_R8(MSG)             ((MSG)->func)
+#define RPC_I32(MSG, IDX)       ((MSG)->DATA.i32[(IDX) / 4U])
+#define RPC_I16(MSG, IDX)       ((MSG)->DATA.i16[(IDX) / 2U])
+#define RPC_I8(MSG, IDX)        ((MSG)->DATA.i8[(IDX)])
+#define RPC_U32(MSG, IDX)       ((MSG)->DATA.u32[(IDX) / 4U])
+#define RPC_U16(MSG, IDX)       ((MSG)->DATA.u16[(IDX) / 2U])
+#define RPC_U8(MSG, IDX)        ((MSG)->DATA.u8[(IDX)])
+
+#define SC_RPC_SVC_UNKNOWN      0U
+#define SC_RPC_SVC_RETURN       1U
+#define SC_RPC_SVC_PM           2U
+#define SC_RPC_SVC_RM           3U
+#define SC_RPC_SVC_TIMER        5U
+#define SC_RPC_SVC_PAD          6U
+#define SC_RPC_SVC_MISC         7U
+#define SC_RPC_SVC_IRQ          8U
+#define SC_RPC_SVC_ABORT        9U
+
+#define SC_RPC_ASYNC_STATE_RD_START      0U
+#define SC_RPC_ASYNC_STATE_RD_ACTIVE     1U
+#define SC_RPC_ASYNC_STATE_RD_DONE       2U
+#define SC_RPC_ASYNC_STATE_WR_START      3U
+#define SC_RPC_ASYNC_STATE_WR_ACTIVE     4U
+#define SC_RPC_ASYNC_STATE_WR_DONE       5U
+
+#define SC_RPC_MU_GIR_SVC       0x1U
+#define SC_RPC_MU_GIR_DBG       0x8U
+
+/* Types */
+
+typedef uint8_t sc_rpc_svc_t;
+
+typedef struct sc_rpc_msg_s
+{
+    uint8_t version;
+    uint8_t size;
+    uint8_t svc;
+    uint8_t func;
+    union
+    {
+        int32_t i32[(SC_RPC_MAX_MSG - 1U)];
+        int16_t i16[(SC_RPC_MAX_MSG - 1U) * 2U];
+        int8_t i8[(SC_RPC_MAX_MSG - 1U) * 4U];
+        uint32_t u32[(SC_RPC_MAX_MSG - 1U)];
+        uint16_t u16[(SC_RPC_MAX_MSG - 1U) * 2U];
+        uint8_t u8[(SC_RPC_MAX_MSG - 1U) * 4U];
+    } DATA;
+} sc_rpc_msg_t;
+
+typedef uint8_t sc_rpc_async_state_t;
+
+typedef struct sc_rpc_async_msg_s
+{
+    sc_rpc_async_state_t state;
+    uint8_t wordIdx;
+    sc_rpc_msg_t msg;
+    uint32_t timeStamp;
+} sc_rpc_async_msg_t;
+
+/* Functions */
+
+/*!
+ * This is an internal function to send an RPC message over an IPC
+ * channel. It is called by client-side SCFW API function shims.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in,out] msg         handle to a message
+ * @param[in]     no_resp     response flag
+ *
+ * If \a no_resp is SC_FALSE then this function waits for a response
+ * and returns the result in \a msg.
+ */
+void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, sc_bool_t no_resp);
+
+/*!
+ * This is an internal function to dispath an RPC call that has
+ * arrived via IPC over an MU. It is called by server-side SCFW.
+ *
+ * @param[in]     mu          MU message arrived on
+ * @param[in,out] msg         handle to a message
+ *
+ * The function result is returned in \a msg.
+ */
+void sc_rpc_dispatch(sc_rsrc_t mu, sc_rpc_msg_t *msg);
+
+/*!
+ * This function translates an RPC message and forwards on to the
+ * normal RPC API.  It is used only by hypervisors.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in,out] msg         handle to a message
+ *
+ * This function decodes a message, calls macros to translate the
+ * resources, pads, addresses, partitions, memory regions, etc. and
+ * then forwards on to the hypervisors SCFW API.Return results are
+ * translated back abd placed back into the message to be returned
+ * to the original API.
+ */
+void sc_rpc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
+
+#endif /* SC_RPC_H */
+
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h
new file mode 100755
index 0000000000..1e266c39b4
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file containing the public API for the System Controller (SC)
+ * Interrupt (IRQ) function.
+ *
+ * @addtogroup IRQ_SVC (SVC) Interrupt Service
+ *
+ * Module for the Interrupt (IRQ) service.
+ *
+ * @{
+ */
+
+#ifndef SC_IRQ_API_H
+#define SC_IRQ_API_H
+
+/* Includes */
+
+#include <asm/arch/sci/types.h>
+
+/* Defines */
+
+#define SC_IRQ_NUM_GROUP    4U          /*!< Number of groups */
+
+/*!
+ * @name Defines for sc_irq_group_t
+ */
+/*@{*/
+#define SC_IRQ_GROUP_TEMP   0U   /*!< Temp interrupts */
+#define SC_IRQ_GROUP_WDOG   1U   /*!< Watchdog interrupts */
+#define SC_IRQ_GROUP_RTC    2U   /*!< RTC interrupts */
+#define SC_IRQ_GROUP_WAKE   3U   /*!< Wakeup interrupts */
+/*@}*/
+
+/*!
+ * @name Defines for sc_irq_temp_t
+ */
+/*@{*/
+#define SC_IRQ_TEMP_HIGH         (1U << 0U)    /*!< Temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU0_HIGH    (1U << 1U)    /*!< CPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU1_HIGH    (1U << 2U)    /*!< CPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU0_HIGH    (1U << 3U)    /*!< GPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU1_HIGH    (1U << 4U)    /*!< GPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC0_HIGH    (1U << 5U)    /*!< DRC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC1_HIGH    (1U << 6U)    /*!< DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_VPU_HIGH     (1U << 7U)    /*!< DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC0_HIGH   (1U << 8U)    /*!< PMIC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC1_HIGH   (1U << 9U)    /*!< PMIC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_LOW          (1U << 10U)   /*!< Temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU0_LOW     (1U << 11U)   /*!< CPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU1_LOW     (1U << 12U)   /*!< CPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU0_LOW     (1U << 13U)   /*!< GPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU1_LOW     (1U << 14U)   /*!< GPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC0_LOW     (1U << 15U)   /*!< DRC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC1_LOW     (1U << 16U)   /*!< DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_VPU_LOW      (1U << 17U)   /*!< DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC0_LOW    (1U << 18U)   /*!< PMIC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC1_LOW    (1U << 19U)   /*!< PMIC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC2_HIGH   (1U << 20U)   /*!< PMIC2 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC2_LOW    (1U << 21U)   /*!< PMIC2 temp alarm interrupt */
+/*@}*/
+
+/*!
+ * @name Defines for sc_irq_wdog_t
+ */
+/*@{*/
+#define SC_IRQ_WDOG              (1U << 0U     /*!< Watchdog interrupt */
+/*@}*/
+
+/*!
+ * @name Defines for sc_irq_rtc_t
+ */
+/*@{*/
+#define SC_IRQ_RTC               (1U << 0U)    /*!< RTC interrupt */
+/*@}*/
+
+/*!
+ * @name Defines for sc_irq_wake_t
+ */
+/*@{*/
+#define SC_IRQ_BUTTON            (1U << 0U)    /*!< Button interrupt */
+#define SC_IRQ_PAD               (1U << 1U)    /*!< Pad wakeup */
+/*@}*/
+
+/* Types */
+
+/*!
+ * This type is used to declare an interrupt group.
+ */
+typedef uint8_t sc_irq_group_t;
+
+/*!
+ * This type is used to declare a bit mask of temp interrupts.
+ */
+typedef uint8_t sc_irq_temp_t;
+
+/*!
+ * This type is used to declare a bit mask of watchdog interrupts.
+ */
+typedef uint8_t sc_irq_wdog_t;
+
+/*!
+ * This type is used to declare a bit mask of RTC interrupts.
+ */
+typedef uint8_t sc_irq_rtc_t;
+
+/*!
+ * This type is used to declare a bit mask of wakeup interrupts.
+ */
+typedef uint8_t sc_irq_wake_t;
+
+/* Functions */
+
+/*!
+ * This function enables/disables interrupts. If pending interrupts
+ * are unmasked, an interrupt will be triggered.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    MU channel
+ * @param[in]     group       group the interrupts are in
+ * @param[in]     mask        mask of interrupts to affect
+ * @param[in]     enable      state to change interrupts to
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if group invalid
+ */
+sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_irq_group_t group, uint32_t mask, sc_bool_t enable);
+
+/*!
+ * This function returns the current interrupt status (regardless if
+ * masked). Automatically clears pending interrupts.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    MU channel
+ * @param[in]     group       groups the interrupts are in
+ * @param[in]     status      status of interrupts
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if group invalid
+ *
+ * The returned \a status may show interrupts pending that are
+ * currently masked.
+ */
+sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_irq_group_t group, uint32_t *status);
+
+#endif /* SC_IRQ_API_H */
+
+/**@}*/
+
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
new file mode 100755
index 0000000000..210dd04c7c
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
@@ -0,0 +1,523 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file containing the public API for the System Controller (SC)
+ * Miscellaneous (MISC) function.
+ *
+ * @addtogroup MISC_SVC (SVC) Miscellaneous Service
+ *
+ * Module for the Miscellaneous (MISC) service.
+ *
+ * @{
+ */
+
+#ifndef SC_MISC_API_H
+#define SC_MISC_API_H
+
+/* Includes */
+
+#include <asm/arch/sci/types.h>
+#include <asm/arch/sci/svc/rm/api.h>
+
+/* Defines */
+
+/*!
+ * @name Defines for type widths
+ */
+/*@{*/
+#define SC_MISC_DMA_GRP_W       5U      /*!< Width of sc_misc_dma_group_t */
+/*@}*/
+
+/*! Max DMA channel priority group */
+#define SC_MISC_DMA_GRP_MAX     31U
+
+/*!
+ * @name Defines for sc_misc_boot_status_t
+ */
+/*@{*/
+#define SC_MISC_BOOT_STATUS_SUCCESS     0U   /*!< Success */
+#define SC_MISC_BOOT_STATUS_SECURITY    1U   /*!< Security violation */
+/*@}*/
+
+/*!
+ * @name Defines for sc_misc_seco_auth_cmd_t
+ */
+/*@{*/
+#define SC_MISC_SECO_AUTH_SECO_FW       0U   /*!< SECO Firmware */
+#define SC_MISC_SECO_AUTH_HDMI_TX_FW    1U   /*!< HDMI TX Firmware */
+#define SC_MISC_SECO_AUTH_HDMI_RX_FW    2U   /*!< HDMI RX Firmware */
+/*@}*/
+
+/*!
+ * @name Defines for sc_misc_temp_t
+ */
+/*@{*/
+#define SC_MISC_TEMP                    0U   /*!< Temp sensor */
+#define SC_MISC_TEMP_HIGH               1U   /*!< Temp high alarm */
+#define SC_MISC_TEMP_LOW                2U   /*!< Temp low alarm */
+/*@}*/
+
+/*!
+ * @name Defines for sc_misc_seco_auth_cmd_t
+ */
+/*@{*/
+#define SC_MISC_AUTH_CONTAINER          0U   /*!< Authenticate container */
+#define SC_MISC_VERIFY_IMAGE            1U   /*!< Verify image */
+#define SC_MISC_REL_CONTAINER           2U   /*!< Release container */
+/*@}*/
+
+/* Types */
+
+/*!
+ * This type is used to store a DMA channel priority group.
+ */
+typedef uint8_t sc_misc_dma_group_t;
+
+/*!
+ * This type is used report boot status.
+ */
+typedef uint8_t sc_misc_boot_status_t;
+
+/*!
+ * This type is used to issue SECO authenticate commands.
+ */
+typedef uint8_t sc_misc_seco_auth_cmd_t;
+
+/*!
+ * This type is used report boot status.
+ */
+typedef uint8_t sc_misc_temp_t;
+
+/* Functions */
+
+/*!
+ * @name Control Functions
+ * @{
+ */
+
+/*!
+ * This function sets a miscellaneous control value.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    resource the control is associated with
+ * @param[in]     ctrl        control to change
+ * @param[in]     val         value to apply to the control
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
+ *   of the owner
+ *
+ * Refer to the [Control List](@ref CONTROLS) for valid control values.
+ */
+sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_ctrl_t ctrl, uint32_t val);
+
+/*!
+ * This function gets a miscellaneous control value.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    resource the control is associated with
+ * @param[in]     ctrl        control to get
+ * @param[out]    val         pointer to return the control value
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
+ *   of the owner
+ *
+ * Refer to the [Control List](@ref CONTROLS) for valid control values.
+ */
+sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_ctrl_t ctrl, uint32_t *val);
+
+/* @} */
+
+/*!
+ * @name DMA Functions
+ * @{
+ */
+
+/*!
+ * This function configures the max DMA channel priority group for a
+ * partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to assign \a max
+ * @param[in]     max         max priority group (0-31)
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent
+ *   of the affected partition
+ *
+ * Valid \a max range is 0-31 with 0 being the lowest and 31 the highest.
+ * Default is the max priority group for the parent partition of \a pt.
+ */
+sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_misc_dma_group_t max);
+
+/*!
+ * This function configures the priority group for a DMA channel.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    DMA channel resource
+ * @param[in]     group       priority group (0-31)
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the owner or parent
+ *   of the owner of the DMA channel
+ *
+ * Valid \a group range is 0-31 with 0 being the lowest and 31 the highest.
+ * The max value of \a group is limited by the partition max set using
+ * sc_misc_set_max_dma_group().
+ */
+sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_misc_dma_group_t group);
+
+/* @} */
+
+/*!
+ * @name Security Functions
+ * @{
+ */
+
+/*!
+ * This function loads a SECO image.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     addr_src    address of image source
+ * @param[in]     addr_dst    address of image destination
+ * @param[in]     len         lenth of image to load
+ * @param[in]     fw          SC_TRUE = firmware load
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if word fuse index param out of range or invalid
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * This is used to load images via the SECO. Examples include SECO
+ * Firmware and IVT/CSF data used for authentication. These are usually
+ * loaded into SECO TCM. \a addr_src is in secure memory.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src,
+    sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw);
+
+/*!
+ * This function is used to authenticate a SECO image or command.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     cmd         authenticate command
+ * @param[in]     addr        address of/or metadata
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if word fuse index param out of range or invalid
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * This is used to authenticate a SECO image or issue a security
+ * command. \a addr often points to an container. It is also
+ * just data (or even unused) for some commands.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc,
+    sc_misc_seco_auth_cmd_t cmd, sc_faddr_t addr);
+
+/*!
+ * This function securely writes a group of fuse words.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     addr        address of message block
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * Note \a addr must be a pointer into secure RAM. The contents at
+ * this location are a signed fuse command message block.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_misc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr);
+
+/*!
+ * This function securely enables debug.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     addr        address of message block
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * Note \a addr must be a pointer into secure RAM. The contents at
+ * this location are a signed fuse command message block.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_misc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr);
+
+/*!
+ * This function updates the lifecycle of the device.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     lifecycle   new lifecycle
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t lifecycle);
+
+/*!
+ * This function securely reverses the lifecycle.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     addr        address of message block
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * Note \a addr must be a pointer into secure RAM. The contents at
+ * this location are a signed fuse command message block.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_misc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr);
+
+/*!
+ * This function is used to return the SECO FW build info.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    version     pointer to return build number
+ * @param[out]    commit      pointer to return commit ID (git SHA-1)
+ */
+void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version,
+    uint32_t *commit);
+
+/* @} */
+
+/*!
+ * @name Debug Functions
+ * @{
+ */
+
+/*!
+ * This function is used output a debug character from the SCU UART.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     ch          character to output
+ */
+void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch);
+
+/*!
+ * This function starts/stops emulation waveform capture.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     enable      flag to enable/disable capture
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_UNAVAILABLE if not running on emulation
+ */
+sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable);
+
+/*!
+ * This function is used to return the SCFW build info.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    build       pointer to return build number
+ * @param[out]    commit      pointer to return commit ID (git SHA-1)
+ */
+void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build,
+    uint32_t *commit);
+
+/*!
+ * This function is used to return the device's unique ID.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    id_l        pointer to return lower 32-bit of ID [31:0]
+ * @param[out]    id_h        pointer to return upper 32-bits of ID [63:32]
+ */
+void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l,
+    uint32_t *id_h);
+
+/* @} */
+
+/*!
+ * @name Other Functions
+ * @{
+ */
+
+/*!
+ * This function configures the ARI match value for PCIe/SATA resources.
+ *
+ * @param[in]     ipc          IPC handle
+ * @param[in]     resource     match resource
+ * @param[in]     resource_mst PCIe/SATA master to match
+ * @param[in]     ari          ARI to match
+ * @param[in]     enable       enable match or not
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the owner or parent
+ *   of the owner of the resource and translation
+ *
+ * For PCIe, the ARI is the 16-bit value that includes the bus number,
+ * device number, and function number. For SATA, this value includes the
+ * FISType and PM_Port.
+ */
+sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable);
+
+/*!
+ * This function reports boot status.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     status      boot status
+ *
+ * This is used by SW partitions to report status of boot. This is
+ * normally used to report a boot failure.
+ */
+void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
+
+/*!
+ * This function tells the SCFW that a CPU is done booting.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     cpu         CPU that is done booting
+ *
+ * This is called by early booting CPUs to report they are done with
+ * initialization. After starting early CPUs, the SCFW halts the
+ * booting process until they are done. During this time, early
+ * CPUs can call the SCFW with lower latency as the SCFW is idle.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the CPU owner
+ */
+sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu);
+
+/*!
+ * This function reads a given fuse word index.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     word        fuse word index
+ * @param[out]    val         fuse read value
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if word fuse index param out of range or invalid
+ * - SC_ERR_NOACCESS if read operation failed
+ * - SC_ERR_LOCKED if read operation is locked
+ */
+sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val);
+
+/*!
+ * This function writes a given fuse word index.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     word        fuse word index
+ * @param[in]     val         fuse write value
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if word fuse index param out of range or invalid
+ * - SC_ERR_NOACCESS if write operation failed
+ * - SC_ERR_LOCKED if write operation is locked
+ */
+sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val);
+
+/*!
+ * This function sets a temp sensor alarm.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    resource with sensor
+ * @param[in]     temp        alarm to set
+ * @param[in]     celsius     whole part of temp to set
+ * @param[in]     tenths      fractional part of temp to set
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * This function will enable the alarm interrupt if the temp requested is
+ * not the min/max temp. This enable automatically clears when the alarm
+ * occurs and this function has to be called again to re-enable.
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if parameters invalid
+ */
+sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_misc_temp_t temp, int16_t celsius, int8_t tenths);
+
+/*!
+ * This function gets a temp sensor value.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    resource with sensor
+ * @param[in]     temp        value to get (sensor or alarm)
+ * @param[out]    celsius     whole part of temp to get
+ * @param[out]    tenths      fractional part of temp to get
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if parameters invalid
+ */
+sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths);
+
+/*!
+ * This function returns the boot device.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    dev         pointer to return boot device
+ */
+void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev);
+
+/*!
+ * This function returns the current status of the ON/OFF button.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    status      pointer to return button status
+ */
+void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status);
+
+/* @} */
+
+#endif /* SC_MISC_API_H */
+
+/**@}*/
+
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
new file mode 100755
index 0000000000..76cb0dab9a
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
@@ -0,0 +1,568 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file containing the public API for the System Controller (SC)
+ * Pad Control (PAD) function.
+ *
+ * @addtogroup PAD_SVC (SVC) Pad Service
+ *
+ * Module for the Pad Control (PAD) service.
+ *
+ * @details
+ *
+ * Pad configuration is managed by SC firmware. The pad configuration
+ * features supported by the SC firmware include:
+ *
+ * - Configuring the mux, input/output connection, and low-power isolation
+     mode.
+ * - Configuring the technology-specific pad setting such as drive strength,
+ *   pullup/pulldown, etc.
+ * - Configuring compensation for pad groups with dual voltage capability.
+ *
+ * Pad functions fall into one of three categories. Generic functions are
+ * common to all SoCs and all process technologies. SoC functions are raw
+ * low-level functions. Technology-specific functions are specific to the
+ * process technology.
+ *
+ * The list of pads is SoC specific.  Refer to the SoC [Pad List](@ref PADS)
+ * for valid pad values. Note that all pads exist on a die but may or
+ * may not be brought out by the specific package.  Mapping of pads to
+ * package pins/balls is documented in the associated Data Sheet. Some pads
+ * may not be brought out because the part (die+package) is defeatured and
+ * some pads may connect to the substrate in the package.
+ *
+ * Some pads (SC_P_COMP_*) that can be specified are not individual pads
+ * but are in fact pad groups. These groups have additional configuration
+ * that can be done using the sc_pad_set_gp_28fdsoi_comp() function. More
+ * info on these can be found in the associated Reference Manual.
+ *
+ * Pads are managed as a resource by the Resource Manager (RM).  They have
+ * assigned owners and only the owners can configure the pads. Some of the
+ * pads are reserved for use by the SCFW itself and this can be overriden
+ * with the implementation of board_config_sc(). Additionally, pads may
+ * be assigned to various other partitions via the implementation of
+ * board_system_config().
+ *
+ * Note muxing two input pads to the same IP functional signal will
+ * result in undefined behavior.
+ * @{
+ */
+
+#ifndef SC_PAD_API_H
+#define SC_PAD_API_H
+
+/* Includes */
+
+#include <asm/arch/sci/types.h>
+#include <asm/arch/sci/svc/rm/api.h>
+
+/* Defines */
+
+/*!
+ * @name Defines for type widths
+ */
+/*@{*/
+#define SC_PAD_MUX_W            3U    /*!< Width of mux parameter */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pad_config_t
+ */
+/*@{*/
+#define SC_PAD_CONFIG_NORMAL    0U    /*!< Normal */
+#define SC_PAD_CONFIG_OD        1U    /*!< Open Drain */
+#define SC_PAD_CONFIG_OD_IN     2U    /*!< Open Drain and input */
+#define SC_PAD_CONFIG_OUT_IN    3U    /*!< Output and input */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pad_iso_t
+ */
+/*@{*/
+#define SC_PAD_ISO_OFF          0U    /*!< ISO latch is transparent */
+#define SC_PAD_ISO_EARLY        1U    /*!< Follow EARLY_ISO */
+#define SC_PAD_ISO_LATE         2U    /*!< Follow LATE_ISO */
+#define SC_PAD_ISO_ON           3U    /*!< ISO latched data is held */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pad_28fdsoi_dse_t
+ */
+/*@{*/
+#define SC_PAD_28FDSOI_DSE_18V_1MA   0U    /*!< Drive strength of 1mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_2MA   1U    /*!< Drive strength of 2mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_4MA   2U    /*!< Drive strength of 4mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_6MA   3U    /*!< Drive strength of 6mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_8MA   4U    /*!< Drive strength of 8mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_10MA  5U    /*!< Drive strength of 10mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_12MA  6U    /*!< Drive strength of 12mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_HS    7U    /*!< High-speed drive strength for 1.8v */
+#define SC_PAD_28FDSOI_DSE_33V_2MA   0U    /*!< Drive strength of 2mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_33V_4MA   1U    /*!< Drive strength of 4mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_33V_8MA   2U    /*!< Drive strength of 8mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_33V_12MA  3U    /*!< Drive strength of 12mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_DV_HIGH   0U    /*!< High drive strength for dual volt */
+#define SC_PAD_28FDSOI_DSE_DV_LOW    1U    /*!< Low drive strength for dual volt */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pad_28fdsoi_ps_t
+ */
+/*@{*/
+#define SC_PAD_28FDSOI_PS_KEEPER 0U    /*!< Bus-keeper (only valid for 1.8v) */
+#define SC_PAD_28FDSOI_PS_PU     1U    /*!< Pull-up */
+#define SC_PAD_28FDSOI_PS_PD     2U    /*!< Pull-down */
+#define SC_PAD_28FDSOI_PS_NONE   3U    /*!< No pull (disabled) */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pad_28fdsoi_pus_t
+ */
+/*@{*/
+#define SC_PAD_28FDSOI_PUS_30K_PD  0U    /*!< 30K pull-down */
+#define SC_PAD_28FDSOI_PUS_100K_PU 1U    /*!< 100K pull-up */
+#define SC_PAD_28FDSOI_PUS_3K_PU   2U    /*!< 3K pull-up */
+#define SC_PAD_28FDSOI_PUS_30K_PU  3U    /*!< 30K pull-up */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pad_wakeup_t
+ */
+/*@{*/
+#define SC_PAD_WAKEUP_OFF       0U    /*!< Off */
+#define SC_PAD_WAKEUP_CLEAR     1U    /*!< Clears pending flag */
+#define SC_PAD_WAKEUP_LOW_LVL   4U    /*!< Low level */
+#define SC_PAD_WAKEUP_FALL_EDGE 5U    /*!< Falling edge */
+#define SC_PAD_WAKEUP_RISE_EDGE 6U    /*!< Rising edge */
+#define SC_PAD_WAKEUP_HIGH_LVL  7U    /*!< High-level */
+/*@}*/
+
+/* Types */
+
+/*!
+ * This type is used to declare a pad config. It determines how the
+ * output data is driven, pull-up is controlled, and input signal is
+ * connected. Normal and OD are typical and only connect the input
+ * when the output is not driven.  The IN options are less common and
+ * force an input connection even when driving the output.
+ */
+typedef uint8_t sc_pad_config_t;
+
+/*!
+ * This type is used to declare a pad low-power isolation config.
+ * ISO_LATE is the most common setting. ISO_EARLY is only used when
+ * an output pad is directly determined by another input pad. The
+ * other two are only used when SW wants to directly contol isolation.
+ */
+typedef uint8_t sc_pad_iso_t;
+
+/*!
+ * This type is used to declare a drive strength. Note it is specific
+ * to 28FDSOI. Also note that valid values depend on the pad type.
+ */
+typedef uint8_t sc_pad_28fdsoi_dse_t;
+
+/*!
+ * This type is used to declare a pull select. Note it is specific
+ * to 28FDSOI.
+ */
+typedef uint8_t sc_pad_28fdsoi_ps_t;
+
+/*!
+ * This type is used to declare a pull-up select. Note it is specific
+ * to 28FDSOI HSIC pads.
+ */
+typedef uint8_t sc_pad_28fdsoi_pus_t;
+
+/*!
+ * This type is used to declare a wakeup mode of a pad.
+ */
+typedef uint8_t sc_pad_wakeup_t;
+
+/* Functions */
+
+/*!
+ * @name Generic Functions
+ * @{
+ */
+
+/*!
+ * This function configures the mux settings for a pad. This includes
+ * the signal mux, pad config, and low-power isolation mode.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to configure
+ * @param[in]     mux         mux setting
+ * @param[in]     config      pad config
+ * @param[in]     iso         low-power isolation mode
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
+ *
+ * Note muxing two input pads to the same IP functional signal will
+ * result in undefined behavior.
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad,
+    uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso);
+
+/*!
+ * This function gets the mux settings for a pad. This includes
+ * the signal mux, pad config, and low-power isolation mode.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to query
+ * @param[out]    mux         pointer to return mux setting
+ * @param[out]    config      pointer to return pad config
+ * @param[out]    iso         pointer to return low-power isolation mode
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad,
+    uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso);
+
+/*!
+ * This function configures the general purpose pad control. This
+ * is technology dependent and includes things like drive strength,
+ * slew rate, pull up/down, etc. Refer to the SoC Reference Manual
+ * for bit field details.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to configure
+ * @param[in]     ctrl        control value to set
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl);
+
+/*!
+ * This function gets the general purpose pad control. This
+ * is technology dependent and includes things like drive strength,
+ * slew rate, pull up/down, etc. Refer to the SoC Reference Manual
+ * for bit field details.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to query
+ * @param[out]    ctrl        pointer to return control value
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl);
+
+/*!
+ * This function configures the wakeup mode of the pad.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to configure
+ * @param[in]     wakeup      wakeup to set
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad,
+    sc_pad_wakeup_t wakeup);
+
+/*!
+ * This function gets the wakeup mode of a pad.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to query
+ * @param[out]    wakeup      pointer to return wakeup
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad,
+    sc_pad_wakeup_t *wakeup);
+
+/*!
+ * This function configures a pad.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to configure
+ * @param[in]     mux         mux setting
+ * @param[in]     config      pad config
+ * @param[in]     iso         low-power isolation mode
+ * @param[in]     ctrl        control value
+ * @param[in]     wakeup      wakeup to set
+ *
+ * @see sc_pad_set_mux().
+ * @see sc_pad_set_gp().
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Note muxing two input pads to the same IP functional signal will
+ * result in undefined behavior.
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux,
+    sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
+    sc_pad_wakeup_t wakeup);
+
+/*!
+ * This function gets a pad's config.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to query
+ * @param[out]    mux         pointer to return mux setting
+ * @param[out]    config      pointer to return pad config
+ * @param[out]    iso         pointer to return low-power isolation mode
+ * @param[out]    ctrl        pointer to return control value
+ * @param[out]    wakeup      pointer to return wakeup to set
+ *
+ * @see sc_pad_set_mux().
+ * @see sc_pad_set_gp().
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux,
+    sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl,
+    sc_pad_wakeup_t *wakeup);
+
+/* @} */
+
+/*!
+ * @name SoC Specific Functions
+ * @{
+ */
+
+/*!
+ * This function configures the settings for a pad. This setting is SoC
+ * specific.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to configure
+ * @param[in]     val         value to set
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val);
+
+/*!
+ * This function gets the settings for a pad. This setting is SoC
+ * specific.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to query
+ * @param[out]    val         pointer to return setting
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
+
+/* @} */
+
+/*!
+ * @name Technology Specific Functions
+ * @{
+ */
+
+/*!
+ * This function configures the pad control specific to 28FDSOI.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to configure
+ * @param[in]     dse         drive strength
+ * @param[in]     ps          pull select
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner,
+ * - SC_ERR_UNAVAILABLE if process not applicable
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
+    sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps);
+
+/*!
+ * This function gets the pad control specific to 28FDSOI.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to query
+ * @param[out]    dse         pointer to return drive strength
+ * @param[out]    ps          pointer to return pull select
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner,
+ * - SC_ERR_UNAVAILABLE if process not applicable
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
+    sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps);
+
+/*!
+ * This function configures the pad control specific to 28FDSOI.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to configure
+ * @param[in]     dse         drive strength
+ * @param[in]     hys         hysteresis
+ * @param[in]     pus         pull-up select
+ * @param[in]     pke         pull keeper enable
+ * @param[in]     pue         pull-up enable
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner,
+ * - SC_ERR_UNAVAILABLE if process not applicable
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
+    sc_pad_28fdsoi_dse_t dse, sc_bool_t hys, sc_pad_28fdsoi_pus_t pus,
+    sc_bool_t pke, sc_bool_t pue);
+
+/*!
+ * This function gets the pad control specific to 28FDSOI.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to query
+ * @param[out]    dse         pointer to return drive strength
+ * @param[out]    hys         pointer to return hysteresis
+ * @param[out]    pus         pointer to return pull-up select
+ * @param[out]    pke         pointer to return pull keeper enable
+ * @param[out]    pue         pointer to return pull-up enable
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner,
+ * - SC_ERR_UNAVAILABLE if process not applicable
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
+    sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys, sc_pad_28fdsoi_pus_t *pus,
+    sc_bool_t *pke, sc_bool_t *pue);
+
+/*!
+ * This function configures the compensation control specific to 28FDSOI.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to configure
+ * @param[in]     compen      compensation/freeze mode
+ * @param[in]     fastfrz     fast freeze
+ * @param[in]     rasrcp      compensation code for PMOS
+ * @param[in]     rasrcn      compensation code for NMOS
+ * @param[in]     nasrc_sel   NASRC read select
+ * @param[in]     psw_ovr     2.5v override
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner,
+ * - SC_ERR_UNAVAILABLE if process not applicable
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ *
+ * Note \a psw_ovr is only applicable to pads supporting 2.5 volt
+ * operation (e.g. some Ethernet pads).
+ */
+sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
+    uint8_t compen, sc_bool_t fastfrz, uint8_t rasrcp, uint8_t rasrcn,
+    sc_bool_t nasrc_sel, sc_bool_t psw_ovr);
+
+/*!
+ * This function gets the compensation control specific to 28FDSOI.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to query
+ * @param[out]    compen      pointer to return compensation/freeze mode
+ * @param[out]    fastfrz     pointer to return fast freeze
+ * @param[out]    rasrcp      pointer to return compensation code for PMOS
+ * @param[out]    rasrcn      pointer to return compensation code for NMOS
+ * @param[out]    nasrc_sel   pointer to return NASRC read select
+ * @param[out]    compok      pointer to return compensation status
+ * @param[out]    nasrc       pointer to return NASRCP/NASRCN
+ * @param[out]    psw_ovr     pointer to return the 2.5v override
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner,
+ * - SC_ERR_UNAVAILABLE if process not applicable
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
+    uint8_t *compen, sc_bool_t *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn,
+    sc_bool_t *nasrc_sel, sc_bool_t *compok, uint8_t *nasrc, sc_bool_t *psw_ovr);
+
+/* @} */
+
+#endif /* SC_PAD_API_H */
+
+/**@}*/
+
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h
new file mode 100755
index 0000000000..25d8f063e6
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h
@@ -0,0 +1,686 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file containing the public API for the System Controller (SC)
+ * Power Management (PM) function. This includes functions for power state
+ * control, clock control, reset control, and wake-up event control.
+ *
+ * @addtogroup PM_SVC (SVC) Power Management Service
+ *
+ * Module for the Power Management (PM) service.
+ *
+ * @{
+ */
+
+#ifndef SC_PM_API_H
+#define SC_PM_API_H
+
+/* Includes */
+
+#include <asm/arch/sci/types.h>
+#include <asm/arch/sci/svc/rm/api.h>
+
+/* Defines */
+
+/*!
+ * @name Defines for type widths
+ */
+/*@{*/
+#define SC_PM_POWER_MODE_W      2U      /*!< Width of sc_pm_power_mode_t */
+#define SC_PM_CLOCK_MODE_W      3U      /*!< Width of sc_pm_clock_mode_t */
+#define SC_PM_RESET_TYPE_W      2U      /*!< Width of sc_pm_reset_type_t */
+#define SC_PM_RESET_REASON_W    3U      /*!< Width of sc_pm_reset_reason_t */
+/*@}*/
+
+/*!
+ * @name Defines for clock indexes (sc_pm_clk_t)
+ */
+/*@{*/
+/*@}*/
+
+/*!
+ * @name Defines for ALL parameters
+ */
+/*@{*/
+#define SC_PM_CLK_ALL   UINT8_MAX       /*!< All clocks */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pm_power_mode_t
+ */
+/*@{*/
+#define SC_PM_PW_MODE_OFF       0U      /*!< Power off */
+#define SC_PM_PW_MODE_STBY      1U      /*!< Power in standby */
+#define SC_PM_PW_MODE_LP        2U      /*!< Power in low-power */
+#define SC_PM_PW_MODE_ON        3U      /*!< Power on */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pm_clk_t
+ */
+/*@{*/
+#define SC_PM_CLK_SLV_BUS       0U      /*!< Slave bus clock */
+#define SC_PM_CLK_MST_BUS       1U      /*!< Master bus clock */
+#define SC_PM_CLK_PER           2U      /*!< Peripheral clock */
+#define SC_PM_CLK_PHY           3U      /*!< Phy clock */
+#define SC_PM_CLK_MISC          4U      /*!< Misc clock */
+#define SC_PM_CLK_MISC0         0U      /*!< Misc 0 clock */
+#define SC_PM_CLK_MISC1         1U      /*!< Misc 1 clock */
+#define SC_PM_CLK_MISC2         2U      /*!< Misc 2 clock */
+#define SC_PM_CLK_MISC3         3U      /*!< Misc 3 clock */
+#define SC_PM_CLK_MISC4         4U      /*!< Misc 4 clock */
+#define SC_PM_CLK_CPU           2U      /*!< CPU clock */
+#define SC_PM_CLK_PLL           4U      /*!< PLL */
+#define SC_PM_CLK_BYPASS        4U      /*!< Bypass clock */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pm_clk_mode_t
+ */
+/*@{*/
+#define SC_PM_CLK_MODE_ROM_INIT        0U    /*!< Clock is initialized by ROM. */
+#define SC_PM_CLK_MODE_OFF             1U    /*!< Clock is disabled */
+#define SC_PM_CLK_MODE_ON              2U    /*!< Clock is enabled. */
+#define SC_PM_CLK_MODE_AUTOGATE_SW     3U    /*!< Clock is in SW autogate mode */
+#define SC_PM_CLK_MODE_AUTOGATE_HW     4U    /*!< Clock is in HW autogate mode */
+#define SC_PM_CLK_MODE_AUTOGATE_SW_HW  5U    /*!< Clock is in SW-HW autogate mode */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pm_clk_parent_t
+ */
+/*@{*/
+#define SC_PM_PARENT_XTAL              0U    /*!< Parent is XTAL. */
+#define SC_PM_PARENT_PLL0              1U    /*!< Parent is PLL0 */
+#define SC_PM_PARENT_PLL1              2U    /*!< Parent is PLL1 or PLL0/2 */
+#define SC_PM_PARENT_PLL2              3U    /*!< Parent in PLL2 or PLL0/4 */
+#define SC_PM_PARENT_BYPS              4U    /*!< Parent is a bypass clock. */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pm_reset_type_t
+ */
+/*@{*/
+#define SC_PM_RESET_TYPE_COLD          0U    /*!< Cold reset */
+#define SC_PM_RESET_TYPE_WARM          1U    /*!< Warm reset */
+#define SC_PM_RESET_TYPE_BOARD         2U    /*!< Board reset */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pm_reset_cause_t
+ */
+/*@{*/
+#define SC_PM_RESET_CAUSE_TEMP         0U    /*!< Reset due to temp panic alarm */
+#define SC_PM_RESET_CAUSE_FAULT        1U    /*!< Reset due to fault exception */
+#define SC_PM_RESET_CAUSE_IRQ          2U    /*!< Reset due to SCU reset IRQ */
+#define SC_PM_RESET_CAUSE_WDOG         3U    /*!< Reset due to SW WDOG */
+#define SC_PM_RESET_CAUSE_API          4U    /*!< Reset due to pm_reset() or monitor */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pm_reset_reason_t
+ */
+/*@{*/
+#define SC_PM_RESET_REASON_POR         0U    /*!< Power on reset */
+#define SC_PM_RESET_REASON_WARM        1U    /*!< Warm reset */
+#define SC_PM_RESET_REASON_SW          2U    /*!< Software reset */
+#define SC_PM_RESET_REASON_WDOG        3U    /*!< Watchdog reset */
+#define SC_PM_RESET_REASON_LOCKUP      4U    /*!< Lockup reset */
+#define SC_PM_RESET_REASON_TAMPER      5U    /*!< Tamper reset */
+#define SC_PM_RESET_REASON_TEMP        6U    /*!< Temp reset */
+#define SC_PM_RESET_REASON_LOW_VOLT    7U    /*!< Low voltage reset */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pm_sys_if_t
+ */
+/*@{*/
+#define SC_PM_SYS_IF_INTERCONNECT       0U   /*!< System interconnect */
+#define SC_PM_SYS_IF_MU                 1U   /*!< AP -> SCU message units */
+#define SC_PM_SYS_IF_OCMEM              2U   /*!< On-chip memory (ROM/OCRAM) */
+#define SC_PM_SYS_IF_DDR                3U   /*!< DDR memory */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pm_wake_src_t
+ */
+/*@{*/
+#define SC_PM_WAKE_SRC_NONE             0U   /*!< No wake source, used for self-kill */
+#define SC_PM_WAKE_SRC_SCU              1U   /*!< Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */
+#define SC_PM_WAKE_SRC_IRQSTEER         2U   /*!< Wakeup from IRQSTEER to resume CPU (GIC powered down) */
+#define SC_PM_WAKE_SRC_IRQSTEER_GIC     3U   /*!< Wakeup from IRQSTEER+GIC to wake CPU  (GIC clock gated) */
+#define SC_PM_WAKE_SRC_GIC              4U   /*!< Wakeup from GIC to wake CPU */
+/*@}*/
+
+/* Types */
+
+/*!
+ * This type is used to declare a power mode. Note resources only use
+ * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only
+ * as system power modes.
+ */
+typedef uint8_t sc_pm_power_mode_t;
+
+/*!
+ * This type is used to declare a clock.
+ */
+typedef uint8_t sc_pm_clk_t;
+
+/*!
+ * This type is used to declare a clock mode.
+ */
+typedef uint8_t sc_pm_clk_mode_t;
+
+/*!
+ * This type is used to declare the clock parent.
+ */
+typedef uint8_t sc_pm_clk_parent_t;
+
+/*!
+ * This type is used to declare clock rates.
+ */
+typedef uint32_t sc_pm_clock_rate_t;
+
+/*!
+ * This type is used to declare a desired reset type.
+ */
+typedef uint8_t sc_pm_reset_type_t;
+
+/*!
+ * This type is used to declare a desired reset type.
+ */
+typedef uint8_t sc_pm_reset_cause;
+
+/*!
+ * This type is used to declare a reason for a reset.
+ */
+typedef uint8_t sc_pm_reset_reason_t;
+
+/*!
+ * This type is used to specify a system-level interface to be power managed.
+ */
+typedef uint8_t sc_pm_sys_if_t;
+
+/*!
+ * This type is used to specify a wake source for CPU resources.
+ */
+typedef uint8_t sc_pm_wake_src_t;
+
+/* Functions */
+
+/*!
+ * @name Power Functions
+ * @{
+ */
+
+/*!
+ * This function sets the system power mode. Only the owner of the
+ * SC_R_SYSTEM resource can do this.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     mode        power mode to apply
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid mode,
+ * - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM
+ *
+ * @see sc_pm_set_sys_power_mode().
+ */
+sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode);
+
+/*!
+ * This function sets the power mode of a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition
+ * @param[in]     mode        power mode to apply
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid partition or mode,
+ * - SC_ERR_NOACCESS if caller's partition is not the owner or
+ *   parent of \a pt
+ *
+ * The power mode of the partitions is a max power any resource will
+ * be set to. Calling this will result in all resources owned
+ * by \a pt to have their power changed to the lower of \a mode or the
+ * individual resource mode set using sc_pm_set_resource_power_mode().
+ */
+sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_pm_power_mode_t mode);
+
+/*!
+ * This function gets the power mode of a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition
+ * @param[out]    mode        pointer to return power mode
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid partition
+ */
+sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_pm_power_mode_t *mode);
+
+/*!
+ * This function sets the power mode of a resource.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the resource
+ * @param[in]     mode        power mode to apply
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or mode,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner
+ *   or parent of the owner
+ *
+ * Resources must be at SC_PM_PW_MODE_LP mode or higher to access them,
+ * otherwise the master will get a bus error or hang.
+ *
+ * This function will record the individual resource power mode
+ * and change it if the requested mode is lower than or equal to the
+ * partition power mode set with sc_pm_set_partition_power_mode().
+ * In other words, the power mode of the resource will be the minimum
+ * of the resource power mode and the partition power mode.
+ *
+ * Note some resources are still not accessible even when powered up if bus
+ * transactions go through a fabric not powered up. Examples of this are
+ * resources in display and capture subsystems which require the display
+ * controller or the imaging subsytem to be powered up first.
+ *
+ * Not that resources are grouped into power domains by the underlying
+ * hardware. If any resource in the domain is on, the entire power domain
+ * will be on. Other power domains required to access the resource will
+ * also be turned on. Clocks required to access the peripheral will be
+ * turned on. Refer to the SoC RM for more info on power domains and access
+ * infrastructure (bus fabrics, clock domains, etc.).
+ */
+sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_power_mode_t mode);
+
+/*!
+ * This function gets the power mode of a resource.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the resource
+ * @param[out]    mode        pointer to return power mode
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Note only SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON are valid. The value
+ * returned does not reflect the power mode of the partition..
+ */
+sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_power_mode_t *mode);
+
+/*!
+ * This function requests the low power mode some of the resources
+ * can enter based on their state. This API is only valid for the
+ * following resources : SC_R_A53, SC_R_A53_0, SC_R_A53_1, SC_A53_2,
+ * SC_A53_3, SC_R_A72, SC_R_A72_0, SC_R_A72_1, SC_R_CC1, SC_R_A35,
+ * SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3.
+ * For all other resources it will return SC_ERR_PARAM.
+ * This function will set the low power mode the cores, cluster
+ * and cluster associated resources will enter when all the cores
+ * in a given cluster execute WFI
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the resource
+ * @param[in]     mode        power mode to apply
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ */
+sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_power_mode_t mode);
+
+/*!
+ * This function requests low-power mode entry for CPU/cluster
+ * resources. This API is only valid for the following resources:
+ * SC_R_A53, SC_R_A53_x, SC_R_A72, SC_R_A72_x, SC_R_A35, SC_R_A35_x,
+ * SC_R_CCI. For all other resources it will return SC_ERR_PARAM.
+ * For individual core resources, the specified power mode
+ * and wake source will be applied after the core has entered
+ * WFI.  For cluster resources, the specified power mode is
+ * applied after all cores in the cluster have entered low-power mode.
+ * For multicluster resources, the specified power mode is applied
+ * after all clusters have reached low-power mode.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the resource
+ * @param[in]     mode        power mode to apply
+ * @param[in]     wake_src    wake source for low-power exit
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ */
+sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src);
+
+/*!
+ * This function is used to set the resume address of a CPU.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the CPU resource
+ * @param[in]     address     64-bit resume address
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or address,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of the
+ *   resource (CPU) owner
+ */
+sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_faddr_t address);
+
+/*!
+ * This function is used to set parameters for CPU resume from
+ * low-power mode.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the CPU resource
+ * @param[in]     isPrimary   set SC_TRUE if primary wake CPU
+ * @param[in]     address     64-bit resume address
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or address,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of the
+ *   resource (CPU) owner
+ */
+sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_bool_t isPrimary, sc_faddr_t address);
+
+/*!
+ * This function requests the power mode configuration for system-level
+ * interfaces including messaging units, interconnect, and memories.  This API
+ * is only valid for the following resources : SC_R_A53, SC_R_A72, and
+ * SC_R_M4_x_PID_y.  For all other resources, it will return SC_ERR_PARAM.
+ * The requested power mode will be captured and applied to system-level
+ * resources as system conditions allow.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the resource
+ * @param[in]     sys_if      system-level interface to be configured
+ * @param[in]     hpm         high-power mode for the system interface
+ * @param[in]     lpm         low-power mode for the system interface
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ */
+sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm);
+
+/* @} */
+
+/*!
+ * @name Clock/PLL Functions
+ * @{
+ */
+
+/*!
+ * This function sets the rate of a resource's clock/PLL.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the resource
+ * @param[in]     clk         clock/PLL to affect
+ * @param[in,out] rate        pointer to rate to set,
+ *                            return actual rate
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or clock/PLL,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner
+ *   or parent of the owner,
+ * - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource,
+ * - SC_ERR_LOCKED if rate locked (usually because shared clock/PLL)
+ *
+ * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values.
+ */
+sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
+
+/*!
+ * This function gets the rate of a resource's clock/PLL.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the resource
+ * @param[in]     clk         clock/PLL to affect
+ * @param[out]    rate        pointer to return rate
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or clock/PLL,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner
+ *   or parent of the owner,
+ * - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource
+ *
+ * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values.
+ */
+sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
+
+/*!
+ * This function enables/disables a resource's clock.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the resource
+ * @param[in]     clk         clock to affect
+ * @param[in]     enable      enable if SC_TRUE; otherwise disabled
+ * @param[in]     autog       HW auto clock gating
+ *
+ * If \a resource is SC_R_ALL then all resources owned will be affected.
+ * No error will be returned.
+ *
+ * If \a clk is SC_PM_CLK_ALL, then an error will be returned if any
+ * of the available clocks returns an error.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or clock,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner
+ *   or parent of the owner,
+ * - SC_ERR_UNAVAILABLE if clock not applicable to this resource
+ *
+ * Refer to the [Clock List](@ref CLOCKS) for valid clock values.
+ */
+sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
+
+/*!
+ * This function sets the parent of a resource's clock.
+ * This function should only be called when the clock is disabled.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the resource
+ * @param[in]     clk         clock to affect
+ * @param[in]     parent      New parent of the clock.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or clock,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner
+ *   or parent of the owner,
+ * - SC_ERR_UNAVAILABLE if clock not applicable to this resource
+ * - SC_ERR_BUSY if clock is currently enabled.
+ * - SC_ERR_NOPOWER if resource not powered
+ *
+ * Refer to the [Clock List](@ref CLOCKS) for valid clock values.
+ */
+sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
+
+/*!
+ * This function gets the parent of a resource's clock.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the resource
+ * @param[in]     clk         clock to affect
+ * @param[out]     parent     pointer to return parent of clock.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or clock,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner
+ *   or parent of the owner,
+ * - SC_ERR_UNAVAILABLE if clock not applicable to this resource
+ *
+ * Refer to the [Clock List](@ref CLOCKS) for valid clock values.
+ */
+sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
+
+/* @} */
+
+/*!
+ * @name Reset Functions
+ * @{
+ */
+
+/*!
+ * This function is used to reset the system. Only the owner of the
+ * SC_R_SYSTEM resource can do this.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     type        reset type
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid type,
+ * - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM
+ *
+ * If this function returns, then the reset did not occur due to an
+ * invalid parameter.
+ */
+sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type);
+
+/*!
+ * This function gets a caller's reset reason.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    reason      pointer to return reset reason
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason);
+
+/*!
+ * This function is used to boot a partition.
+ *
+ * @param[in]     ipc          IPC handle
+ * @param[in]     pt           handle of partition to boot
+ * @param[in]     resource_cpu ID of the CPU resource to start
+ * @param[in]     boot_addr    64-bit boot address
+ * @param[in]     resource_mu  ID of the MU that must be powered
+ * @param[in]     resource_dev ID of the boot device that must be powered
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid partition, resource, or addr,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of the
+ *   partition to boot
+ */
+sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
+    sc_rsrc_t resource_mu, sc_rsrc_t resource_dev);
+
+/*!
+ * This function is used to reboot the caller's partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     type        reset type
+ *
+ * If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by
+ * the calling partition will be reset if possible. SC state (partitions,
+ * power, clocks, etc.) is reset. The boot SW of the booting CPU must be
+ * able to handle peripherals that that are not reset.
+ *
+ * If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset.
+ * SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW
+ * of the booting CPU must be able to handle peripherals and SC state that
+ * that are not reset.
+ *
+ * If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action.
+ *
+ * If this function returns, then the reset did not occur due to an
+ * invalid parameter.
+ */
+void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type);
+
+/*!
+ * This function is used to reboot a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to reboot
+ * @param[in]     type        reset type
+ *
+ * If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by
+ * the calling partition will be reset if possible. SC state (partitions,
+ * power, clocks, etc.) is reset. The boot SW of the booting CPU must be
+ * able to handle peripherals that that are not reset.
+ *
+ * If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset.
+ * SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW
+ * of the booting CPU must be able to handle peripherals and SC state that
+ * that are not reset.
+ *
+ * If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid partition or type
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
+ *
+ * Most peripherals owned by the partition will be reset if
+ * possible. SC state (partitions, power, clocks, etc.) is reset. The
+ * boot SW of the booting CPU must be able to handle peripherals that
+ * that are not reset.
+ */
+sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_pm_reset_type_t type);
+
+/*!
+ * This function is used to start/stop a CPU.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the CPU resource
+ * @param[in]     enable      start if SC_TRUE; otherwise stop
+ * @param[in]     address     64-bit boot address
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or address,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of the
+ *   resource (CPU) owner
+ */
+sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
+    sc_faddr_t address);
+
+/* @} */
+
+#endif /* SC_PM_API_H */
+
+/**@}*/
+
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h
new file mode 100755
index 0000000000..0de009a00e
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h
@@ -0,0 +1,759 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file containing the public API for the System Controller (SC)
+ * Resource Management (RM) function. This includes functions for
+ * partitioning resources, pads, and memory regions.
+ *
+ * @addtogroup RM_SVC (SVC) Resource Management Service
+ *
+ * Module for the Resource Management (RM) service.
+ *
+ * @includedoc rm/details.dox
+ *
+ * @{
+ */
+
+#ifndef SC_RM_API_H
+#define SC_RM_API_H
+
+/* Includes */
+
+#include <asm/arch/sci/types.h>
+
+/* Defines */
+
+/*!
+ * @name Defines for type widths
+ */
+/*@{*/
+#define SC_RM_PARTITION_W   5U      /*!< Width of sc_rm_pt_t */
+#define SC_RM_MEMREG_W      6U      /*!< Width of sc_rm_mr_t */
+#define SC_RM_DID_W         4U      /*!< Width of sc_rm_did_t */
+#define SC_RM_SID_W         6U      /*!< Width of sc_rm_sid_t */
+#define SC_RM_SPA_W         2U      /*!< Width of sc_rm_spa_t */
+#define SC_RM_PERM_W        3U      /*!< Width of sc_rm_perm_t */
+/*@}*/
+
+/*!
+ * @name Defines for ALL parameters
+ */
+/*@{*/
+#define SC_RM_PT_ALL        ((sc_rm_pt_t) UINT8_MAX)   /*!< All partitions */
+#define SC_RM_MR_ALL        ((sc_rm_mr_t) UINT8_MAX)   /*!< All memory regions */
+/*@}*/
+
+/*!
+ * @name Defines for sc_rm_spa_t
+ */
+/*@{*/
+#define SC_RM_SPA_PASSTHRU  0U   /*!< Pass through (attribute driven by master) */
+#define SC_RM_SPA_PASSSID   1U   /*!< Pass through and output on SID */
+#define SC_RM_SPA_ASSERT    2U   /*!< Assert (force to be secure/privileged) */
+#define SC_RM_SPA_NEGATE    3U   /*!< Negate (force to be non-secure/user) */
+/*@}*/
+
+/*!
+ * @name Defines for sc_rm_perm_t
+ */
+/*@{*/
+#define SC_RM_PERM_NONE         0U   /*!< No access */
+#define SC_RM_PERM_SEC_R        1U   /*!< Secure RO */
+#define SC_RM_PERM_SECPRIV_RW   2U   /*!< Secure privilege R/W */
+#define SC_RM_PERM_SEC_RW       3U   /*!< Secure R/W */
+#define SC_RM_PERM_NSPRIV_R     4U   /*!< Secure R/W, non-secure privilege RO */
+#define SC_RM_PERM_NS_R         5U   /*!< Secure R/W, non-secure RO */
+#define SC_RM_PERM_NSPRIV_RW    6U   /*!< Secure R/W, non-secure privilege R/W */
+#define SC_RM_PERM_FULL         7U   /*!< Full access */
+/*@}*/
+
+/* Types */
+
+/*!
+ * This type is used to declare a resource partition.
+ */
+typedef uint8_t sc_rm_pt_t;
+
+/*!
+ * This type is used to declare a memory region.
+ */
+typedef uint8_t sc_rm_mr_t;
+
+/*!
+ * This type is used to declare a resource domain ID used by the
+ * isolation HW.
+ */
+typedef uint8_t sc_rm_did_t;
+
+/*!
+ * This type is used to declare an SMMU StreamID.
+ */
+typedef uint16_t sc_rm_sid_t;
+
+/*!
+ * This type is a used to declare master transaction attributes.
+ */
+typedef uint8_t sc_rm_spa_t;
+
+/*!
+ * This type is used to declare a resource/memory region access permission.
+ * Refer to the XRDC2 Block Guide for more information.
+ */
+typedef uint8_t sc_rm_perm_t;
+
+/* Functions */
+
+/*!
+ * @name Partition Functions
+ * @{
+ */
+
+/*!
+ * This function requests that the SC create a new resource partition.
+ *
+ * @param[in]     ipc          IPC handle
+ * @param[out]    pt           return handle for partition; used for subsequent function
+ *                             calls associated with this partition
+ * @param[in]     secure       boolean indicating if this partition should be secure; only
+ *                             valid if caller is secure
+ * @param[in]     isolated     boolean indicating if this partition should be HW isolated
+ *                             via XRDC; set SC_TRUE if new DID is desired
+ * @param[in]     restricted   boolean indicating if this partition should be restricted; set
+ *                             SC_TRUE if masters in this partition cannot create new partitions
+ * @param[in]     grant        boolean indicating if this partition should always grant
+ *                             access and control to the parent
+ * @param[in]     coherent     boolean indicating if this partition is coherent;
+ *                             set SC_TRUE if only this partition will contain both AP clusters
+ *                             and they will be coherent via the CCI
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_ERR_PARM if caller's partition is not secure but a new secure partition is requested,
+ * - SC_ERR_LOCKED if caller's partition is locked,
+ * - SC_ERR_UNAVAILABLE if partition table is full (no more allocation space)
+ *
+ * Marking as non-secure prevents subsequent functions from configuring masters in this
+ * partition to assert the secure signal. If restricted then the new partition is limited
+ * in what functions it can call, especially those associated with managing partitions.
+ *
+ * The grant option is usually used to isolate a bus master's traffic to specific
+ * memory without isolating the peripheral interface of the master or the API
+ * controls of that master.
+ */
+sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
+    sc_bool_t isolated, sc_bool_t restricted, sc_bool_t grant, sc_bool_t coherent);
+
+/*!
+ * This function makes a partition confidential.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition that is granting
+ * @param[in]     retro       retroactive
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if \a pt out of range,
+ * - SC_ERR_NOACCESS if caller's not allowed to change \a pt
+ * - SC_ERR_LOCKED if partition \a pt is locked
+ *
+ * Call to make a partition confidential. Confidential means only this
+ * partition should be able to grant access permissions to this partition.
+ *
+ * If retroactive, then all resources owned by other partitions will have
+ * access rights for this partition removed, even if locked.
+ */
+sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro);
+
+/*!
+ * This function frees a partition and assigns all resources to the caller.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to free
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if \a pt out of range or invalid,
+ * - SC_ERR_NOACCESS if \a pt is the SC partition,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
+ * - SC_ERR_LOCKED if \a pt or caller's partition is locked
+ *
+ * All resources, memory regions, and pads are assigned to the caller/parent.
+ * The partition watchdog is disabled (even if locked). DID is freed.
+ */
+sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt);
+
+/*!
+ * This function returns the DID of a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ *
+ * @return Returns the domain ID (DID) of the caller's partition.
+ *
+ * The DID is a SoC-specific internal ID used by the HW resource
+ * protection mechanism. It is only required by clients when using the
+ * SEMA42 module as the DID is sometimes connected to the master ID.
+ */
+sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc);
+
+/*!
+ * This function forces a partition to use a specific static DID.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to assign \a did
+ * @param[in]     did         static DID to assign
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if \a pt or \a did out of range,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
+ * - SC_ERR_LOCKED if \a pt is locked
+ *
+ * Assumes no assigned resources or memory regions yet! The number of static
+ * DID is fixed by the SC at boot.
+ */
+sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_rm_did_t did);
+
+/*!
+ * This function locks a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to lock
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if \a pt out of range,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt
+ *
+ * If a partition is locked it cannot be freed, have resources/pads assigned
+ * to/from it, memory regions created/assigned, DID changed, or parent changed.
+ */
+sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt);
+
+/*!
+ * This function gets the partition handle of the caller.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    pt          return handle for caller's partition
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt);
+
+/*!
+ * This function sets a new parent for a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition for which parent is to be
+ *                            changed
+ * @param[in]     pt_parent   handle of partition to set as parent
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
+ * - SC_ERR_LOCKED if either partition is locked
+ */
+sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_rm_pt_t pt_parent);
+
+/*!
+ * This function moves all movable resources/pads owned by a source partition
+ * to a destination partition. It can be used to more quickly set up a new
+ * partition if a majority of the caller's resources are to be moved to a
+ * new partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt_src      handle of partition from which resources should
+ *                            be moved from
+ * @param[in]     pt_dst      handle of partition to which resources should be
+ *                            moved to
+ * @param[in]     move_rsrc   boolean to indicate if resources should be moved
+ * @param[in]     move_pads   boolean to indicate if pads should be moved
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * By default, all resources are movable. This can be changed using the
+ * sc_rm_set_resource_movable() function. Note all masters defaulted to SMMU
+ * bypass.
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not \a pt_src or the
+ *   parent of \a pt_src,
+ * - SC_ERR_LOCKED if either partition is locked
+ */
+sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
+    sc_bool_t move_rsrc, sc_bool_t move_pads);
+
+/* @} */
+
+/*!
+ * @name Resource Functions
+ * @{
+ */
+
+/*!
+ * This function assigns ownership of a resource to a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to which resource should be
+ *                            assigned
+ * @param[in]     resource    resource to assign
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * This action resets the resource's master and peripheral attributes.
+ * Privilege attribute will be PASSTHRU, security attribute will be
+ * ASSERT if the partition si secure and NEGATE if it is not, and
+ * masters will defaulted to SMMU bypass. Access permissions will reset
+ * to SEC_RW for the owning partition only for secure partitions, FULL for
+ * non-secure. DEfault is no access by other partitions.
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
+ *   of the owner,
+ * - SC_ERR_LOCKED if the owning partition or \a pt is locked
+ */
+sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_rsrc_t resource);
+
+/*!
+ * This function flags resources as movable or not.
+ *
+ * @param[in]     ipc          IPC handle
+ * @param[in]     resource_fst first resource for which flag should be set
+ * @param[in]     resource_lst last resource for which flag should be set
+ * @param[in]     movable      movable flag (SC_TRUE is movable)
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if resources are out of range,
+ * - SC_ERR_NOACCESS if caller's partition is not a parent of a resource owner,
+ * - SC_ERR_LOCKED if the owning partition is locked
+ *
+ * This function is used to determine the set of resources that will be
+ * moved using the sc_rm_move_all() function. All resources are movable
+ * by default so this function is normally used to prevent a set of
+ * resources from moving.
+ */
+sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
+    sc_rsrc_t resource_lst, sc_bool_t movable);
+
+/*!
+ * This function flags all of a subsystem's resources as movable
+ * or not.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    resource to use to identify subsystem
+ * @param[in]     movable     movable flag (SC_TRUE is movable)
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if a function argument is out of range
+ *
+ * Note \a resource is used to find the associated subsystem. Only
+ * resources owned by the caller are set.
+ */
+sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_bool_t movable);
+
+/*!
+ * This function sets attributes for a resource which is a bus master (i.e.
+ * capable of DMA).
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    master resource for which attributes should apply
+ * @param[in]     sa          security attribute
+ * @param[in]     pa          privilege attribute
+ * @param[in]     smmu_bypass SMMU bypass mode
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not a parent of the resource owner,
+ * - SC_ERR_LOCKED if the owning partition is locked
+ *
+ * This function configures how the HW isolation will see bus transactions
+ * from the specified master. Note the security attribute will only be
+ * changed if the caller's partition is secure.
+ */
+sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_rm_spa_t sa, sc_rm_spa_t pa, sc_bool_t smmu_bypass);
+
+/*!
+ * This function sets the StreamID for a resource which is a bus master (i.e.
+ * capable of DMA).
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    master resource for which attributes should apply
+ * @param[in]     sid         StreamID
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
+ *   of the owner,
+ * - SC_ERR_LOCKED if the owning partition is locked
+ *
+ * This function configures the SID attribute associated with all bus transactions
+ * from this master. Note 0 is not a valid SID as it is reserved to indicate
+ * bypass.
+ */
+sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_rm_sid_t sid);
+
+/*!
+ * This function sets access permissions for a peripheral resource.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    peripheral resource for which permissions should apply
+ * @param[in]     pt          handle of partition \a perm should by applied for
+ * @param[in]     perm        permissions to apply to \a resource for \a pt
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
+ *   of the owner,
+ * - SC_ERR_LOCKED if the owning partition is locked
+ * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt
+ *
+ * This function configures how the HW isolation will restrict access to a
+ * peripheral based on the attributes of a transaction from bus master.
+ */
+sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_rm_pt_t pt, sc_rm_perm_t perm);
+
+/*!
+ * This function gets ownership status of a resource.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    resource to check
+ *
+ * @return Returns a boolean (SC_TRUE if caller's partition owns the resource).
+ *
+ * If \a resource is out of range then SC_FALSE is returned.
+ */
+sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
+
+/*!
+ * This function is used to test if a resource is a bus master.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    resource to check
+ *
+ * @return Returns a boolean (SC_TRUE if the resource is a bus master).
+ *
+ * If \a resource is out of range then SC_FALSE is returned.
+ */
+sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource);
+
+/*!
+ * This function is used to test if a resource is a peripheral.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    resource to check
+ *
+ * @return Returns a boolean (SC_TRUE if the resource is a peripheral).
+ *
+ * If \a resource is out of range then SC_FALSE is returned.
+ */
+sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource);
+
+/*!
+ * This function is used to obtain info about a resource.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    resource to inquire about
+ * @param[out]    sid         pointer to return StreamID
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if \a resource is out of range
+ */
+sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_rm_sid_t *sid);
+
+/* @} */
+
+/*!
+ * @name Memory Region Functions
+ * @{
+ */
+
+/*!
+ * This function requests that the SC create a new memory region.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    mr          return handle for region; used for
+ *                            subsequent function calls
+ *                            associated with this region
+ * @param[in]     addr_start  start address of region (physical)
+ * @param[in]     addr_end    end address of region (physical)
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if the new memory region is misaligned,
+ * - SC_ERR_LOCKED if caller's partition is locked,
+ * - SC_ERR_PARM if the new memory region spans multiple existing regions,
+ * - SC_ERR_NOACCESS if caller's partition does not own the memory containing
+ *   the new region,
+ * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation
+ *   space)
+ *
+ * The area covered by the memory region must currently be owned by the caller.
+ * By default, the new region will have access permission set to allow the
+ * caller to access.
+ */
+sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr,
+    sc_faddr_t addr_start, sc_faddr_t addr_end);
+
+/*!
+ * This function requests that the SC split a memory region.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     mr          handle of memory region to split
+ * @param[out]    mr_ret      return handle for new region; used for
+ *                            subsequent function calls
+ *                            associated with this region
+ * @param[in]     addr_start  start address of region (physical)
+ * @param[in]     addr_end    end address of region (physical)
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if the new memory region is not start/end part of mr,
+ * - SC_ERR_LOCKED if caller's partition is locked,
+ * - SC_ERR_PARM if the new memory region spans multiple existing regions,
+ * - SC_ERR_NOACCESS if caller's partition does not own the memory containing
+ *   the new region,
+ * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation
+ *   space)
+ *
+ * Note the new region must start or end on the split region.
+ */
+sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr,
+    sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end);
+
+/*!
+ * This function frees a memory region.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     mr          handle of memory region to free
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if \a mr out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not a parent of \a mr,
+ * - SC_ERR_LOCKED if the owning partition of \a mr is locked
+ */
+sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr);
+
+/*!
+ * Internal SC function to find a memory region.
+ *
+ * @see sc_rm_find_memreg().
+ */
+/*!
+ * This function finds a memory region.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    mr          return handle for region; used for
+ *                            subsequent function calls
+ *                            associated with this region
+ * @param[in]     addr_start  start address of region to search for
+ * @param[in]     addr_end    end address of region to search for
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_NOTFOUND if region not found,
+ *
+ * Searches only for regions owned by the caller. Finds first
+ * region containing the range specified.
+ */
+sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr,
+    sc_faddr_t addr_start, sc_faddr_t addr_end);
+
+/*!
+ * This function assigns ownership of a memory region.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to which memory region
+ *                            should be assigned
+ * @param[in]     mr          handle of memory region to assign
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the \a mr owner or parent
+ *   of the owner,
+ * - SC_ERR_LOCKED if the owning partition or \a pt is locked
+ */
+sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr);
+
+/*!
+ * This function sets access permissions for a memory region.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     mr          handle of memory region for which permissions
+ *                            should apply
+ * @param[in]     pt          handle of partition \a perm should by
+ *                            applied for
+ * @param[in]     perm        permissions to apply to \a mr for \a pt
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the region owner or parent
+ *   of the owner,
+ * - SC_ERR_LOCKED if the owning partition is locked
+ * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt
+ *
+ * This function configures how the HW isolation will restrict access to a
+ * memory region based on the attributes of a transaction from bus master.
+ */
+sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
+    sc_rm_pt_t pt, sc_rm_perm_t perm);
+
+/*!
+ * This function gets ownership status of a memory region.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     mr          handle of memory region to check
+ *
+ * @return Returns a boolean (SC_TRUE if caller's partition owns the
+ * memory region).
+ *
+ * If \a mr is out of range then SC_FALSE is returned.
+ */
+sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
+
+/*!
+ * This function is used to obtain info about a memory region.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     mr          handle of memory region to inquire about
+ * @param[out]    addr_start  pointer to return start address
+ * @param[out]    addr_end    pointer to return end address
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if \a mr is out of range
+ */
+sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr,
+    sc_faddr_t *addr_start, sc_faddr_t *addr_end);
+
+/* @} */
+
+/*!
+ * @name Pad Functions
+ * @{
+ */
+
+/*!
+ * This function assigns ownership of a pad to a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to which pad should
+ *                            be assigned
+ * @param[in]     pad         pad to assign
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_NOACCESS if caller's partition is restricted,
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner or parent
+ *   of the owner,
+ * - SC_ERR_LOCKED if the owning partition or \a pt is locked
+ */
+sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
+
+/*!
+ * This function flags pads as movable or not.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad_fst     first pad for which flag should be set
+ * @param[in]     pad_lst     last pad for which flag should be set
+ * @param[in]     movable     movable flag (SC_TRUE is movable)
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if pads are out of range,
+ * - SC_ERR_NOACCESS if caller's partition is not a parent of a pad owner,
+ * - SC_ERR_LOCKED if the owning partition is locked
+ *
+ * This function is used to determine the set of pads that will be
+ * moved using the sc_rm_move_all() function. All pads are movable
+ * by default so this function is normally used to prevent a set of
+ * pads from moving.
+ */
+sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
+    sc_pad_t pad_lst, sc_bool_t movable);
+
+/*!
+ * This function gets ownership status of a pad.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pad         pad to check
+ *
+ * @return Returns a boolean (SC_TRUE if caller's partition owns the pad).
+ *
+ * If \a pad is out of range then SC_FALSE is returned.
+ */
+sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad);
+
+/* @} */
+
+/*!
+ * @name Debug Functions
+ * @{
+ */
+
+/*!
+ * This function dumps the RM state for debug.
+ *
+ * @param[in]     ipc         IPC handle
+ */
+void sc_rm_dump(sc_ipc_t ipc);
+
+/* @} */
+
+#endif /* SC_RM_API_H */
+
+/**@}*/
+
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h
new file mode 100755
index 0000000000..631dab1531
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h
@@ -0,0 +1,306 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file containing the public API for the System Controller (SC)
+ * Timer function.
+ *
+ * @addtogroup TIMER_SVC (SVC) Timer Service
+ *
+ * Module for the Timer service. This includes support for the watchdog, RTC,
+ * and system counter. Note every resource partition has a watchdog it can
+ * use.
+ *
+ * @{
+ */
+
+#ifndef SC_TIMER_API_H
+#define SC_TIMER_API_H
+
+/* Includes */
+
+#include <asm/arch/sci/types.h>
+#include <asm/arch/sci/svc/rm/api.h>
+
+/* Defines */
+
+/*!
+ * @name Defines for type widths
+ */
+/*@{*/
+#define SC_TIMER_ACTION_W   3U      /*!< Width of sc_timer_wdog_action_t */
+/*@}*/
+
+/*!
+ * @name Defines for sc_timer_wdog_action_t
+ */
+/*@{*/
+#define SC_TIMER_WDOG_ACTION_PARTITION      0U   /*!< Reset partition */
+#define SC_TIMER_WDOG_ACTION_WARM           1U   /*!< Warm reset system */
+#define SC_TIMER_WDOG_ACTION_COLD           2U   /*!< Cold reset system */
+#define SC_TIMER_WDOG_ACTION_BOARD          3U   /*!< Reset board */
+#define SC_TIMER_WDOG_ACTION_IRQ            4U   /*!< Only generate IRQs */
+/*@}*/
+
+/* Types */
+
+/*!
+ * This type is used to configure the watchdog action.
+ */
+typedef uint8_t sc_timer_wdog_action_t;
+
+/*!
+ * This type is used to declare a watchdog time value in milliseconds.
+ */
+typedef uint32_t sc_timer_wdog_time_t;
+
+/* Functions */
+
+/*!
+ * @name Wathdog Functions
+ * @{
+ */
+
+/*!
+ * This function sets the watchdog timeout in milliseconds. If not
+ * set then the timeout defaults to the max. Once locked this value
+ * cannot be changed.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     timeout     timeout period for the watchdog
+ *
+ * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED
+ *         = locked).
+ */
+sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc,
+    sc_timer_wdog_time_t timeout);
+
+/*!
+ * This function sets the watchdog pre-timeout in milliseconds. If not
+ * set then the pre-timeout defaults to the max. Once locked this value
+ * cannot be changed.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pre_timeout pre-timeout period for the watchdog
+ *
+ * When the pre-timout expires an IRQ will be generated. Note this timeout
+ * clears when the IRQ is triggered. An IRQ is generated for the failing
+ * partition and all of its child partitions.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc,
+    sc_timer_wdog_time_t pre_timeout);
+
+/*!
+ * This function starts the watchdog.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     lock        boolean indicating the lock status
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * If \a lock is set then the watchdog cannot be stopped or the timeout
+ * period changed.
+ */
+sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock);
+
+/*!
+ * This function stops the watchdog if it is not locked.
+ *
+ * @param[in]     ipc         IPC handle
+ *
+ * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED
+ *         = locked).
+ */
+sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc);
+
+/*!
+ * This function pings (services, kicks) the watchdog resetting the time
+ * before expiration back to the timeout.
+ *
+ * @param[in]     ipc         IPC handle
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc);
+
+/*!
+ * This function gets the status of the watchdog. All arguments are
+ * in milliseconds.
+ *
+ * @param[in]     ipc             IPC handle
+ * @param[out]    timeout         pointer to return the timeout
+ * @param[out]    max_timeout     pointer to return the max timeout
+ * @param[out]    remaining_time  pointer to return the time remaining
+ *                                until trigger
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc,
+    sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout,
+    sc_timer_wdog_time_t *remaining_time);
+
+/*!
+ * This function gets the status of the watchdog of a partition. All
+ * arguments are in milliseconds.
+ *
+ * @param[in]     ipc             IPC handle
+ * @param[in]     pt              partition to query
+ * @param[out]    enb             pointer to return enable status
+ * @param[out]    timeout         pointer to return the timeout
+ * @param[out]    remaining_time  pointer to return the time remaining
+ *                                until trigger
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t *enb,
+    sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *remaining_time);
+
+/*!
+ * This function configures the action to be taken when a watchdog
+ * expires.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          partition to affect
+ * @param[in]     action      action to take
+ *
+ * Default action is inherited from the parent.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid parameters,
+ * - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner,
+ * - SC_ERR_LOCKED if the watchdog is locked
+ */
+sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc,
+    sc_rm_pt_t pt, sc_timer_wdog_action_t action);
+
+/* @} */
+
+/*!
+ * @name Real-Time Clock (RTC) Functions
+ * @{
+ */
+
+/*!
+ * This function sets the RTC time. Only the owner of the SC_R_SYSTEM
+ * resource can set the time.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     year        year (min 1970)
+ * @param[in]     mon         month (1-12)
+ * @param[in]     day         day of the month (1-31)
+ * @param[in]     hour        hour (0-23)
+ * @param[in]     min         minute (0-59)
+ * @param[in]     sec         second (0-59)
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid time/date parameters,
+ * - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner
+ */
+sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon,
+    uint8_t day, uint8_t hour, uint8_t min, uint8_t sec);
+
+/*!
+ * This function gets the RTC time.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    year        pointer to return year (min 1970)
+ * @param[out]    mon         pointer to return month (1-12)
+ * @param[out]    day         pointer to return day of the month (1-31)
+ * @param[out]    hour        pointer to return hour (0-23)
+ * @param[out]    min         pointer to return minute (0-59)
+ * @param[out]    sec         pointer to return second (0-59)
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon,
+    uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec);
+
+/*!
+ * This function gets the RTC time in seconds since 1/1/1970.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    sec         pointer to return second
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec);
+
+/*!
+ * This function sets the RTC alarm.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     year        year (min 1970)
+ * @param[in]     mon         month (1-12)
+ * @param[in]     day         day of the month (1-31)
+ * @param[in]     hour        hour (0-23)
+ * @param[in]     min         minute (0-59)
+ * @param[in]     sec         second (0-59)
+ *
+ * Note this alarm setting clears when the alarm is triggered.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid time/date parameters
+ */
+sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon,
+    uint8_t day, uint8_t hour, uint8_t min, uint8_t sec);
+
+/*!
+ * This function sets the RTC alarm.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     sec         period in seconds
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid time/date parameters
+ */
+sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec);
+
+/*!
+ * This function sets the RTC alarm.
+ *
+ * @param[in]     ipc         IPC handle
+ *
+ * Note this alarm setting clears when the alarm is triggered.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid time/date parameters
+ */
+sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc);
+
+/*!
+ * This function sets the RTC calibration value. Only the owner of the SC_R_SYSTEM
+ * resource can set the calibration.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     count       calbration count (-16 to 15)
+ *
+ * The calibration value is a 5-bit value including the sign bit, which is
+ * implemented in 2's complement. It is added or subtracted from the RTC on
+ * a perdiodic basis, once per 32768 cycles of the RTC clock.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count);
+
+/* @} */
+
+#endif /* SC_TIMER_API_H */
+
+/**@}*/
+
diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h b/arch/arm/include/asm/arch-imx8/sci/types.h
new file mode 100755
index 0000000000..e4c37a0480
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/types.h
@@ -0,0 +1,862 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file containing types used across multiple service APIs.
+ */
+
+#ifndef SC_TYPES_H
+#define SC_TYPES_H
+
+/* Includes */
+#include <linux/types.h>
+
+/* Defines */
+/*!
+ * This type is used to declare a handle for an IPC communication
+ * channel. Its meaning is specific to the IPC implementation.
+ */
+typedef uint64_t sc_ipc_t;
+
+/*!
+ * This type is used to declare an ID for an IPC communication
+ * channel. Its meaning is specific to the IPC implementation.
+ */
+typedef uint64_t sc_ipc_id_t;
+
+/*!
+ * @name Defines for common frequencies
+ */
+/*@{*/
+#define SC_32KHZ            32768U   /*!< 32KHz */
+#define SC_10MHZ         10000000U   /*!< 10MHz */
+#define SC_20MHZ         20000000U   /*!< 20MHz */
+#define SC_25MHZ         25000000U   /*!< 25MHz */
+#define SC_27MHZ         27000000U   /*!< 27MHz */
+#define SC_40MHZ         40000000U   /*!< 40MHz */
+#define SC_45MHZ         45000000U   /*!< 45MHz */
+#define SC_50MHZ         50000000U   /*!< 50MHz */
+#define SC_60MHZ         60000000U   /*!< 60MHz */
+#define SC_66MHZ         66666666U   /*!< 66MHz */
+#define SC_74MHZ         74250000U   /*!< 74.25MHz */
+#define SC_80MHZ         80000000U   /*!< 80MHz */
+#define SC_83MHZ         83333333U   /*!< 83MHz */
+#define SC_84MHZ         84375000U   /*!< 84.37MHz */
+#define SC_100MHZ       100000000U   /*!< 100MHz */
+#define SC_125MHZ       125000000U   /*!< 125MHz */
+#define SC_133MHZ       133333333U   /*!< 133MHz */
+#define SC_135MHZ       135000000U   /*!< 135MHz */
+#define SC_150MHZ       150000000U   /*!< 150MHz */
+#define SC_160MHZ       160000000U   /*!< 160MHz */
+#define SC_166MHZ       166666666U   /*!< 166MHz */
+#define SC_175MHZ       175000000U   /*!< 175MHz */
+#define SC_180MHZ       180000000U   /*!< 180MHz */
+#define SC_200MHZ       200000000U   /*!< 200MHz */
+#define SC_250MHZ       250000000U   /*!< 250MHz */
+#define SC_266MHZ       266666666U   /*!< 266MHz */
+#define SC_300MHZ       300000000U   /*!< 300MHz */
+#define SC_312MHZ       312500000U   /*!< 312.5MHZ */
+#define SC_320MHZ       320000000U   /*!< 320MHz */
+#define SC_325MHZ       325000000U   /*!< 325MHz */
+#define SC_333MHZ       333333333U   /*!< 333MHz */
+#define SC_350MHZ       350000000U   /*!< 350MHz */
+#define SC_372MHZ       372000000U   /*!< 372MHz */
+#define SC_375MHZ       375000000U   /*!< 375MHz */
+#define SC_400MHZ       400000000U   /*!< 400MHz */
+#define SC_500MHZ       500000000U   /*!< 500MHz */
+#define SC_594MHZ       594000000U   /*!< 594MHz */
+#define SC_625MHZ       625000000U   /*!< 625MHz */
+#define SC_640MHZ       640000000U   /*!< 640MHz */
+#define SC_650MHZ       650000000U   /*!< 650MHz */
+#define SC_667MHZ       666666667U   /*!< 667MHz */
+#define SC_675MHZ       675000000U   /*!< 675MHz */
+#define SC_700MHZ       700000000U   /*!< 700MHz */
+#define SC_720MHZ       720000000U   /*!< 720MHz */
+#define SC_750MHZ       750000000U   /*!< 750MHz */
+#define SC_800MHZ       800000000U   /*!< 800MHz */
+#define SC_850MHZ       850000000U   /*!< 850MHz */
+#define SC_900MHZ       900000000U   /*!< 900MHz */
+#define SC_1000MHZ     1000000000U   /*!< 1GHz */
+#define SC_1060MHZ     1060000000U   /*!< 1.06GHz */
+#define SC_1188MHZ     1188000000U   /*!< 1.188GHz */
+#define SC_1260MHZ     1260000000U   /*!< 1.26GHz */
+#define SC_1280MHZ     1280000000U   /*!< 1.28GHz */
+#define SC_1300MHZ     1300000000U   /*!< 1.3GHz */
+#define SC_1400MHZ     1400000000U   /*!< 1.4GHz */
+#define SC_1500MHZ     1500000000U   /*!< 1.5GHz */
+#define SC_1600MHZ     1600000000U   /*!< 1.6GHz */
+#define SC_1800MHZ     1800000000U   /*!< 1.8GHz */
+#define SC_2000MHZ     2000000000U   /*!< 2.0GHz */
+#define SC_2112MHZ     2112000000U   /*!< 2.12GHz */
+/*@}*/
+
+/*!
+ * @name Defines for 24M related frequencies
+ */
+/*@{*/
+#define SC_8MHZ           8000000U   /*!< 8MHz */
+#define SC_12MHZ         12000000U   /*!< 12MHz */
+#define SC_19MHZ         19800000U   /*!< 19.8MHz */
+#define SC_24MHZ         24000000U   /*!< 24MHz */
+#define SC_48MHZ         48000000U   /*!< 48MHz */
+#define SC_120MHZ       120000000U   /*!< 120MHz */
+#define SC_132MHZ       132000000U   /*!< 132MHz */
+#define SC_144MHZ       144000000U   /*!< 144MHz */
+#define SC_192MHZ       192000000U   /*!< 192MHz */
+#define SC_211MHZ       211200000U   /*!< 211.2MHz */
+#define SC_240MHZ       240000000U   /*!< 240MHz */
+#define SC_264MHZ       264000000U   /*!< 264MHz */
+#define SC_352MHZ       352000000U   /*!< 352MHz */
+#define SC_360MHZ       360000000U   /*!< 360MHz */
+#define SC_384MHZ       384000000U   /*!< 384MHz */
+#define SC_396MHZ       396000000U   /*!< 396MHz */
+#define SC_432MHZ       432000000U   /*!< 432MHz */
+#define SC_480MHZ       480000000U   /*!< 480MHz */
+#define SC_600MHZ       600000000U   /*!< 600MHz */
+#define SC_744MHZ       744000000U   /*!< 744MHz */
+#define SC_792MHZ       792000000U   /*!< 792MHz */
+#define SC_864MHZ       864000000U   /*!< 864MHz */
+#define SC_960MHZ       960000000U   /*!< 960MHz */
+#define SC_1056MHZ     1056000000U   /*!< 1056MHz */
+#define SC_1104MHZ     1104000000U   /*!< 1104MHz */
+#define SC_1200MHZ     1200000000U   /*!< 1.2GHz */
+#define SC_1464MHZ     1464000000U   /*!< 1.464GHz */
+#define SC_2400MHZ     2400000000U   /*!< 2.4GHz */
+/*@}*/
+
+/*!
+ * @name Defines for A/V related frequencies
+ */
+/*@{*/
+#define SC_62MHZ         62937500U   /*!< 62.9375MHz */
+#define SC_755MHZ       755250000U   /*!< 755.25MHz */
+/*@}*/
+
+/*!
+ * @name Defines for type widths
+ */
+/*@{*/
+#define SC_FADDR_W      36U          /*!< Width of sc_faddr_t */
+#define SC_BOOL_W       1U           /*!< Width of sc_bool_t */
+#define SC_ERR_W        4U           /*!< Width of sc_err_t */
+#define SC_RSRC_W       10U          /*!< Width of sc_rsrc_t */
+#define SC_CTRL_W       6U           /*!< Width of sc_ctrl_t */
+/*@}*/
+
+/*!
+ * @name Defines for sc_bool_t
+ */
+/*@{*/
+#define SC_FALSE        ((sc_bool_t) 0U)    /*!< True */
+#define SC_TRUE         ((sc_bool_t) 1U)    /*!< False */
+/*@}*/
+
+/*!
+ * @name Defines for sc_err_t.
+ */
+/*@{*/
+#define SC_ERR_NONE         0U      /*!< Success */
+#define SC_ERR_VERSION      1U      /*!< Incompatible API version */
+#define SC_ERR_CONFIG       2U      /*!< Configuration error */
+#define SC_ERR_PARM         3U      /*!< Bad parameter */
+#define SC_ERR_NOACCESS     4U      /*!< Permission error (no access) */
+#define SC_ERR_LOCKED       5U      /*!< Permission error (locked) */
+#define SC_ERR_UNAVAILABLE  6U      /*!< Unavailable (out of resources) */
+#define SC_ERR_NOTFOUND     7U      /*!< Not found */
+#define SC_ERR_NOPOWER      8U      /*!< No power */
+#define SC_ERR_IPC          9U      /*!< Generic IPC error */
+#define SC_ERR_BUSY         10U     /*!< Resource is currently busy/active */
+#define SC_ERR_FAIL         11U     /*!< General I/O failure */
+#define SC_ERR_LAST         12U
+/*@}*/
+
+/*!
+ * @name Defines for sc_rsrc_t.
+ */
+/*@{*/
+#define SC_R_A53                  0U
+#define SC_R_A53_0                1U
+#define SC_R_A53_1                2U
+#define SC_R_A53_2                3U
+#define SC_R_A53_3                4U
+#define SC_R_A72                  5U
+#define SC_R_A72_0                6U
+#define SC_R_A72_1                7U
+#define SC_R_A72_2                8U
+#define SC_R_A72_3                9U
+#define SC_R_CCI                  10U
+#define SC_R_DB                   11U
+#define SC_R_DRC_0                12U
+#define SC_R_DRC_1                13U
+#define SC_R_GIC_SMMU             14U
+#define SC_R_IRQSTR_M4_0          15U
+#define SC_R_IRQSTR_M4_1          16U
+#define SC_R_SMMU                 17U
+#define SC_R_GIC                  18U
+#define SC_R_DC_0_BLIT0           19U
+#define SC_R_DC_0_BLIT1           20U
+#define SC_R_DC_0_BLIT2           21U
+#define SC_R_DC_0_BLIT_OUT        22U
+#define SC_R_DC_0_CAPTURE0        23U
+#define SC_R_DC_0_CAPTURE1        24U
+#define SC_R_DC_0_WARP            25U
+#define SC_R_DC_0_INTEGRAL0       26U
+#define SC_R_DC_0_INTEGRAL1       27U
+#define SC_R_DC_0_VIDEO0          28U
+#define SC_R_DC_0_VIDEO1          29U
+#define SC_R_DC_0_FRAC0           30U
+#define SC_R_DC_0_FRAC1           31U
+#define SC_R_DC_0                 32U
+#define SC_R_GPU_2_PID0           33U
+#define SC_R_DC_0_PLL_0           34U
+#define SC_R_DC_0_PLL_1           35U
+#define SC_R_DC_1_BLIT0           36U
+#define SC_R_DC_1_BLIT1           37U
+#define SC_R_DC_1_BLIT2           38U
+#define SC_R_DC_1_BLIT_OUT        39U
+#define SC_R_DC_1_CAPTURE0        40U
+#define SC_R_DC_1_CAPTURE1        41U
+#define SC_R_DC_1_WARP            42U
+#define SC_R_DC_1_INTEGRAL0       43U
+#define SC_R_DC_1_INTEGRAL1       44U
+#define SC_R_DC_1_VIDEO0          45U
+#define SC_R_DC_1_VIDEO1          46U
+#define SC_R_DC_1_FRAC0           47U
+#define SC_R_DC_1_FRAC1           48U
+#define SC_R_DC_1                 49U
+#define SC_R_GPU_3_PID0           50U
+#define SC_R_DC_1_PLL_0           51U
+#define SC_R_DC_1_PLL_1           52U
+#define SC_R_SPI_0                53U
+#define SC_R_SPI_1                54U
+#define SC_R_SPI_2                55U
+#define SC_R_SPI_3                56U
+#define SC_R_UART_0               57U
+#define SC_R_UART_1               58U
+#define SC_R_UART_2               59U
+#define SC_R_UART_3               60U
+#define SC_R_UART_4               61U
+#define SC_R_EMVSIM_0             62U
+#define SC_R_EMVSIM_1             63U
+#define SC_R_DMA_0_CH0            64U
+#define SC_R_DMA_0_CH1            65U
+#define SC_R_DMA_0_CH2            66U
+#define SC_R_DMA_0_CH3            67U
+#define SC_R_DMA_0_CH4            68U
+#define SC_R_DMA_0_CH5            69U
+#define SC_R_DMA_0_CH6            70U
+#define SC_R_DMA_0_CH7            71U
+#define SC_R_DMA_0_CH8            72U
+#define SC_R_DMA_0_CH9            73U
+#define SC_R_DMA_0_CH10           74U
+#define SC_R_DMA_0_CH11           75U
+#define SC_R_DMA_0_CH12           76U
+#define SC_R_DMA_0_CH13           77U
+#define SC_R_DMA_0_CH14           78U
+#define SC_R_DMA_0_CH15           79U
+#define SC_R_DMA_0_CH16           80U
+#define SC_R_DMA_0_CH17           81U
+#define SC_R_DMA_0_CH18           82U
+#define SC_R_DMA_0_CH19           83U
+#define SC_R_DMA_0_CH20           84U
+#define SC_R_DMA_0_CH21           85U
+#define SC_R_DMA_0_CH22           86U
+#define SC_R_DMA_0_CH23           87U
+#define SC_R_DMA_0_CH24           88U
+#define SC_R_DMA_0_CH25           89U
+#define SC_R_DMA_0_CH26           90U
+#define SC_R_DMA_0_CH27           91U
+#define SC_R_DMA_0_CH28           92U
+#define SC_R_DMA_0_CH29           93U
+#define SC_R_DMA_0_CH30           94U
+#define SC_R_DMA_0_CH31           95U
+#define SC_R_I2C_0                96U
+#define SC_R_I2C_1                97U
+#define SC_R_I2C_2                98U
+#define SC_R_I2C_3                99U
+#define SC_R_I2C_4                100U
+#define SC_R_ADC_0                101U
+#define SC_R_ADC_1                102U
+#define SC_R_FTM_0                103U
+#define SC_R_FTM_1                104U
+#define SC_R_CAN_0                105U
+#define SC_R_CAN_1                106U
+#define SC_R_CAN_2                107U
+#define SC_R_DMA_1_CH0            108U
+#define SC_R_DMA_1_CH1            109U
+#define SC_R_DMA_1_CH2            110U
+#define SC_R_DMA_1_CH3            111U
+#define SC_R_DMA_1_CH4            112U
+#define SC_R_DMA_1_CH5            113U
+#define SC_R_DMA_1_CH6            114U
+#define SC_R_DMA_1_CH7            115U
+#define SC_R_DMA_1_CH8            116U
+#define SC_R_DMA_1_CH9            117U
+#define SC_R_DMA_1_CH10           118U
+#define SC_R_DMA_1_CH11           119U
+#define SC_R_DMA_1_CH12           120U
+#define SC_R_DMA_1_CH13           121U
+#define SC_R_DMA_1_CH14           122U
+#define SC_R_DMA_1_CH15           123U
+#define SC_R_DMA_1_CH16           124U
+#define SC_R_DMA_1_CH17           125U
+#define SC_R_DMA_1_CH18           126U
+#define SC_R_DMA_1_CH19           127U
+#define SC_R_DMA_1_CH20           128U
+#define SC_R_DMA_1_CH21           129U
+#define SC_R_DMA_1_CH22           130U
+#define SC_R_DMA_1_CH23           131U
+#define SC_R_DMA_1_CH24           132U
+#define SC_R_DMA_1_CH25           133U
+#define SC_R_DMA_1_CH26           134U
+#define SC_R_DMA_1_CH27           135U
+#define SC_R_DMA_1_CH28           136U
+#define SC_R_DMA_1_CH29           137U
+#define SC_R_DMA_1_CH30           138U
+#define SC_R_DMA_1_CH31           139U
+#define SC_R_UNUSED1              140U
+#define SC_R_UNUSED2              141U
+#define SC_R_UNUSED3              142U
+#define SC_R_UNUSED4              143U
+#define SC_R_GPU_0_PID0           144U
+#define SC_R_GPU_0_PID1           145U
+#define SC_R_GPU_0_PID2           146U
+#define SC_R_GPU_0_PID3           147U
+#define SC_R_GPU_1_PID0           148U
+#define SC_R_GPU_1_PID1           149U
+#define SC_R_GPU_1_PID2           150U
+#define SC_R_GPU_1_PID3           151U
+#define SC_R_PCIE_A               152U
+#define SC_R_SERDES_0             153U
+#define SC_R_MATCH_0              154U
+#define SC_R_MATCH_1              155U
+#define SC_R_MATCH_2              156U
+#define SC_R_MATCH_3              157U
+#define SC_R_MATCH_4              158U
+#define SC_R_MATCH_5              159U
+#define SC_R_MATCH_6              160U
+#define SC_R_MATCH_7              161U
+#define SC_R_MATCH_8              162U
+#define SC_R_MATCH_9              163U
+#define SC_R_MATCH_10             164U
+#define SC_R_MATCH_11             165U
+#define SC_R_MATCH_12             166U
+#define SC_R_MATCH_13             167U
+#define SC_R_MATCH_14             168U
+#define SC_R_PCIE_B               169U
+#define SC_R_SATA_0               170U
+#define SC_R_SERDES_1             171U
+#define SC_R_HSIO_GPIO            172U
+#define SC_R_MATCH_15             173U
+#define SC_R_MATCH_16             174U
+#define SC_R_MATCH_17             175U
+#define SC_R_MATCH_18             176U
+#define SC_R_MATCH_19             177U
+#define SC_R_MATCH_20             178U
+#define SC_R_MATCH_21             179U
+#define SC_R_MATCH_22             180U
+#define SC_R_MATCH_23             181U
+#define SC_R_MATCH_24             182U
+#define SC_R_MATCH_25             183U
+#define SC_R_MATCH_26             184U
+#define SC_R_MATCH_27             185U
+#define SC_R_MATCH_28             186U
+#define SC_R_LCD_0                187U
+#define SC_R_LCD_0_PWM_0          188U
+#define SC_R_LCD_0_I2C_0          189U
+#define SC_R_LCD_0_I2C_1          190U
+#define SC_R_PWM_0                191U
+#define SC_R_PWM_1                192U
+#define SC_R_PWM_2                193U
+#define SC_R_PWM_3                194U
+#define SC_R_PWM_4                195U
+#define SC_R_PWM_5                196U
+#define SC_R_PWM_6                197U
+#define SC_R_PWM_7                198U
+#define SC_R_GPIO_0               199U
+#define SC_R_GPIO_1               200U
+#define SC_R_GPIO_2               201U
+#define SC_R_GPIO_3               202U
+#define SC_R_GPIO_4               203U
+#define SC_R_GPIO_5               204U
+#define SC_R_GPIO_6               205U
+#define SC_R_GPIO_7               206U
+#define SC_R_GPT_0                207U
+#define SC_R_GPT_1                208U
+#define SC_R_GPT_2                209U
+#define SC_R_GPT_3                210U
+#define SC_R_GPT_4                211U
+#define SC_R_KPP                  212U
+#define SC_R_MU_0A                213U
+#define SC_R_MU_1A                214U
+#define SC_R_MU_2A                215U
+#define SC_R_MU_3A                216U
+#define SC_R_MU_4A                217U
+#define SC_R_MU_5A                218U
+#define SC_R_MU_6A                219U
+#define SC_R_MU_7A                220U
+#define SC_R_MU_8A                221U
+#define SC_R_MU_9A                222U
+#define SC_R_MU_10A               223U
+#define SC_R_MU_11A               224U
+#define SC_R_MU_12A               225U
+#define SC_R_MU_13A               226U
+#define SC_R_MU_5B                227U
+#define SC_R_MU_6B                228U
+#define SC_R_MU_7B                229U
+#define SC_R_MU_8B                230U
+#define SC_R_MU_9B                231U
+#define SC_R_MU_10B               232U
+#define SC_R_MU_11B               233U
+#define SC_R_MU_12B               234U
+#define SC_R_MU_13B               235U
+#define SC_R_ROM_0                236U
+#define SC_R_FSPI_0               237U
+#define SC_R_FSPI_1               238U
+#define SC_R_IEE                  239U
+#define SC_R_IEE_R0               240U
+#define SC_R_IEE_R1               241U
+#define SC_R_IEE_R2               242U
+#define SC_R_IEE_R3               243U
+#define SC_R_IEE_R4               244U
+#define SC_R_IEE_R5               245U
+#define SC_R_IEE_R6               246U
+#define SC_R_IEE_R7               247U
+#define SC_R_SDHC_0               248U
+#define SC_R_SDHC_1               249U
+#define SC_R_SDHC_2               250U
+#define SC_R_ENET_0               251U
+#define SC_R_ENET_1               252U
+#define SC_R_MLB_0                253U
+#define SC_R_DMA_2_CH0            254U
+#define SC_R_DMA_2_CH1            255U
+#define SC_R_DMA_2_CH2            256U
+#define SC_R_DMA_2_CH3            257U
+#define SC_R_DMA_2_CH4            258U
+#define SC_R_USB_0                259U
+#define SC_R_USB_1                260U
+#define SC_R_USB_0_PHY            261U
+#define SC_R_USB_2                262U
+#define SC_R_USB_2_PHY            263U
+#define SC_R_DTCP                 264U
+#define SC_R_NAND                 265U
+#define SC_R_LVDS_0               266U
+#define SC_R_LVDS_0_PWM_0         267U
+#define SC_R_LVDS_0_I2C_0         268U
+#define SC_R_LVDS_0_I2C_1         269U
+#define SC_R_LVDS_1               270U
+#define SC_R_LVDS_1_PWM_0         271U
+#define SC_R_LVDS_1_I2C_0         272U
+#define SC_R_LVDS_1_I2C_1         273U
+#define SC_R_LVDS_2               274U
+#define SC_R_LVDS_2_PWM_0         275U
+#define SC_R_LVDS_2_I2C_0         276U
+#define SC_R_LVDS_2_I2C_1         277U
+#define SC_R_M4_0_PID0            278U
+#define SC_R_M4_0_PID1            279U
+#define SC_R_M4_0_PID2            280U
+#define SC_R_M4_0_PID3            281U
+#define SC_R_M4_0_PID4            282U
+#define SC_R_M4_0_RGPIO           283U
+#define SC_R_M4_0_SEMA42          284U
+#define SC_R_M4_0_TPM             285U
+#define SC_R_M4_0_PIT             286U
+#define SC_R_M4_0_UART            287U
+#define SC_R_M4_0_I2C             288U
+#define SC_R_M4_0_INTMUX          289U
+#define SC_R_M4_0_SIM             290U
+#define SC_R_M4_0_WDOG            291U
+#define SC_R_M4_0_MU_0B           292U
+#define SC_R_M4_0_MU_0A0          293U
+#define SC_R_M4_0_MU_0A1          294U
+#define SC_R_M4_0_MU_0A2          295U
+#define SC_R_M4_0_MU_0A3          296U
+#define SC_R_M4_0_MU_1A           297U
+#define SC_R_M4_1_PID0            298U
+#define SC_R_M4_1_PID1            299U
+#define SC_R_M4_1_PID2            300U
+#define SC_R_M4_1_PID3            301U
+#define SC_R_M4_1_PID4            302U
+#define SC_R_M4_1_RGPIO           303U
+#define SC_R_M4_1_SEMA42          304U
+#define SC_R_M4_1_TPM             305U
+#define SC_R_M4_1_PIT             306U
+#define SC_R_M4_1_UART            307U
+#define SC_R_M4_1_I2C             308U
+#define SC_R_M4_1_INTMUX          309U
+#define SC_R_M4_1_SIM             310U
+#define SC_R_M4_1_WDOG            311U
+#define SC_R_M4_1_MU_0B           312U
+#define SC_R_M4_1_MU_0A0          313U
+#define SC_R_M4_1_MU_0A1          314U
+#define SC_R_M4_1_MU_0A2          315U
+#define SC_R_M4_1_MU_0A3          316U
+#define SC_R_M4_1_MU_1A           317U
+#define SC_R_SAI_0                318U
+#define SC_R_SAI_1                319U
+#define SC_R_SAI_2                320U
+#define SC_R_IRQSTR_SCU2          321U
+#define SC_R_IRQSTR_DSP           322U
+#define SC_R_UNUSED5              323U
+#define SC_R_OCRAM                324U
+#define SC_R_AUDIO_PLL_0          325U
+#define SC_R_PI_0                 326U
+#define SC_R_PI_0_PWM_0           327U
+#define SC_R_PI_0_PWM_1           328U
+#define SC_R_PI_0_I2C_0           329U
+#define SC_R_PI_0_PLL             330U
+#define SC_R_PI_1                 331U
+#define SC_R_PI_1_PWM_0           332U
+#define SC_R_PI_1_PWM_1           333U
+#define SC_R_PI_1_I2C_0           334U
+#define SC_R_PI_1_PLL             335U
+#define SC_R_SC_PID0              336U
+#define SC_R_SC_PID1              337U
+#define SC_R_SC_PID2              338U
+#define SC_R_SC_PID3              339U
+#define SC_R_SC_PID4              340U
+#define SC_R_SC_SEMA42            341U
+#define SC_R_SC_TPM               342U
+#define SC_R_SC_PIT               343U
+#define SC_R_SC_UART              344U
+#define SC_R_SC_I2C               345U
+#define SC_R_SC_MU_0B             346U
+#define SC_R_SC_MU_0A0            347U
+#define SC_R_SC_MU_0A1            348U
+#define SC_R_SC_MU_0A2            349U
+#define SC_R_SC_MU_0A3            350U
+#define SC_R_SC_MU_1A             351U
+#define SC_R_SYSCNT_RD            352U
+#define SC_R_SYSCNT_CMP           353U
+#define SC_R_DEBUG                354U
+#define SC_R_SYSTEM               355U
+#define SC_R_SNVS                 356U
+#define SC_R_OTP                  357U
+#define SC_R_VPU_PID0             358U
+#define SC_R_VPU_PID1             359U
+#define SC_R_VPU_PID2             360U
+#define SC_R_VPU_PID3             361U
+#define SC_R_VPU_PID4             362U
+#define SC_R_VPU_PID5             363U
+#define SC_R_VPU_PID6             364U
+#define SC_R_VPU_PID7             365U
+#define SC_R_VPU_UART             366U
+#define SC_R_VPUCORE              367U
+#define SC_R_VPUCORE_0            368U
+#define SC_R_VPUCORE_1            369U
+#define SC_R_VPUCORE_2            370U
+#define SC_R_VPUCORE_3            371U
+#define SC_R_DMA_4_CH0            372U
+#define SC_R_DMA_4_CH1            373U
+#define SC_R_DMA_4_CH2            374U
+#define SC_R_DMA_4_CH3            375U
+#define SC_R_DMA_4_CH4            376U
+#define SC_R_ISI_CH0              377U
+#define SC_R_ISI_CH1              378U
+#define SC_R_ISI_CH2              379U
+#define SC_R_ISI_CH3              380U
+#define SC_R_ISI_CH4              381U
+#define SC_R_ISI_CH5              382U
+#define SC_R_ISI_CH6              383U
+#define SC_R_ISI_CH7              384U
+#define SC_R_MJPEG_DEC_S0         385U
+#define SC_R_MJPEG_DEC_S1         386U
+#define SC_R_MJPEG_DEC_S2         387U
+#define SC_R_MJPEG_DEC_S3         388U
+#define SC_R_MJPEG_ENC_S0         389U
+#define SC_R_MJPEG_ENC_S1         390U
+#define SC_R_MJPEG_ENC_S2         391U
+#define SC_R_MJPEG_ENC_S3         392U
+#define SC_R_MIPI_0               393U
+#define SC_R_MIPI_0_PWM_0         394U
+#define SC_R_MIPI_0_I2C_0         395U
+#define SC_R_MIPI_0_I2C_1         396U
+#define SC_R_MIPI_1               397U
+#define SC_R_MIPI_1_PWM_0         398U
+#define SC_R_MIPI_1_I2C_0         399U
+#define SC_R_MIPI_1_I2C_1         400U
+#define SC_R_CSI_0                401U
+#define SC_R_CSI_0_PWM_0          402U
+#define SC_R_CSI_0_I2C_0          403U
+#define SC_R_CSI_1                404U
+#define SC_R_CSI_1_PWM_0          405U
+#define SC_R_CSI_1_I2C_0          406U
+#define SC_R_HDMI                 407U
+#define SC_R_HDMI_I2S             408U
+#define SC_R_HDMI_I2C_0           409U
+#define SC_R_HDMI_PLL_0           410U
+#define SC_R_HDMI_RX              411U
+#define SC_R_HDMI_RX_BYPASS       412U
+#define SC_R_HDMI_RX_I2C_0        413U
+#define SC_R_ASRC_0               414U
+#define SC_R_ESAI_0               415U
+#define SC_R_SPDIF_0              416U
+#define SC_R_SPDIF_1              417U
+#define SC_R_SAI_3                418U
+#define SC_R_SAI_4                419U
+#define SC_R_SAI_5                420U
+#define SC_R_GPT_5                421U
+#define SC_R_GPT_6                422U
+#define SC_R_GPT_7                423U
+#define SC_R_GPT_8                424U
+#define SC_R_GPT_9                425U
+#define SC_R_GPT_10               426U
+#define SC_R_DMA_2_CH5            427U
+#define SC_R_DMA_2_CH6            428U
+#define SC_R_DMA_2_CH7            429U
+#define SC_R_DMA_2_CH8            430U
+#define SC_R_DMA_2_CH9            431U
+#define SC_R_DMA_2_CH10           432U
+#define SC_R_DMA_2_CH11           433U
+#define SC_R_DMA_2_CH12           434U
+#define SC_R_DMA_2_CH13           435U
+#define SC_R_DMA_2_CH14           436U
+#define SC_R_DMA_2_CH15           437U
+#define SC_R_DMA_2_CH16           438U
+#define SC_R_DMA_2_CH17           439U
+#define SC_R_DMA_2_CH18           440U
+#define SC_R_DMA_2_CH19           441U
+#define SC_R_DMA_2_CH20           442U
+#define SC_R_DMA_2_CH21           443U
+#define SC_R_DMA_2_CH22           444U
+#define SC_R_DMA_2_CH23           445U
+#define SC_R_DMA_2_CH24           446U
+#define SC_R_DMA_2_CH25           447U
+#define SC_R_DMA_2_CH26           448U
+#define SC_R_DMA_2_CH27           449U
+#define SC_R_DMA_2_CH28           450U
+#define SC_R_DMA_2_CH29           451U
+#define SC_R_DMA_2_CH30           452U
+#define SC_R_DMA_2_CH31           453U
+#define SC_R_ASRC_1               454U
+#define SC_R_ESAI_1               455U
+#define SC_R_SAI_6                456U
+#define SC_R_SAI_7                457U
+#define SC_R_AMIX                 458U
+#define SC_R_MQS_0                459U
+#define SC_R_DMA_3_CH0            460U
+#define SC_R_DMA_3_CH1            461U
+#define SC_R_DMA_3_CH2            462U
+#define SC_R_DMA_3_CH3            463U
+#define SC_R_DMA_3_CH4            464U
+#define SC_R_DMA_3_CH5            465U
+#define SC_R_DMA_3_CH6            466U
+#define SC_R_DMA_3_CH7            467U
+#define SC_R_DMA_3_CH8            468U
+#define SC_R_DMA_3_CH9            469U
+#define SC_R_DMA_3_CH10           470U
+#define SC_R_DMA_3_CH11           471U
+#define SC_R_DMA_3_CH12           472U
+#define SC_R_DMA_3_CH13           473U
+#define SC_R_DMA_3_CH14           474U
+#define SC_R_DMA_3_CH15           475U
+#define SC_R_DMA_3_CH16           476U
+#define SC_R_DMA_3_CH17           477U
+#define SC_R_DMA_3_CH18           478U
+#define SC_R_DMA_3_CH19           479U
+#define SC_R_DMA_3_CH20           480U
+#define SC_R_DMA_3_CH21           481U
+#define SC_R_DMA_3_CH22           482U
+#define SC_R_DMA_3_CH23           483U
+#define SC_R_DMA_3_CH24           484U
+#define SC_R_DMA_3_CH25           485U
+#define SC_R_DMA_3_CH26           486U
+#define SC_R_DMA_3_CH27           487U
+#define SC_R_DMA_3_CH28           488U
+#define SC_R_DMA_3_CH29           489U
+#define SC_R_DMA_3_CH30           490U
+#define SC_R_DMA_3_CH31           491U
+#define SC_R_AUDIO_PLL_1          492U
+#define SC_R_AUDIO_CLK_0          493U
+#define SC_R_AUDIO_CLK_1          494U
+#define SC_R_MCLK_OUT_0           495U
+#define SC_R_MCLK_OUT_1           496U
+#define SC_R_PMIC_0               497U
+#define SC_R_PMIC_1               498U
+#define SC_R_SECO                 499U
+#define SC_R_CAAM_JR1             500U
+#define SC_R_CAAM_JR2             501U
+#define SC_R_CAAM_JR3             502U
+#define SC_R_SECO_MU_2            503U
+#define SC_R_SECO_MU_3            504U
+#define SC_R_SECO_MU_4            505U
+#define SC_R_HDMI_RX_PWM_0        506U
+#define SC_R_A35                  507U
+#define SC_R_A35_0                508U
+#define SC_R_A35_1                509U
+#define SC_R_A35_2                510U
+#define SC_R_A35_3                511U
+#define SC_R_DSP                  512U
+#define SC_R_DSP_RAM              513U
+#define SC_R_CAAM_JR1_OUT         514U
+#define SC_R_CAAM_JR2_OUT         515U
+#define SC_R_CAAM_JR3_OUT         516U
+#define SC_R_VPU_DEC_0            517U
+#define SC_R_VPU_ENC_0            518U
+#define SC_R_CAAM_JR0             519U
+#define SC_R_CAAM_JR0_OUT         520U
+#define SC_R_PMIC_2               521U
+#define SC_R_DBLOGIC              522U
+#define SC_R_HDMI_PLL_1           523U
+#define SC_R_BOARD_R0             524U
+#define SC_R_BOARD_R1             525U
+#define SC_R_BOARD_R2             526U
+#define SC_R_BOARD_R3             527U
+#define SC_R_BOARD_R4             528U
+#define SC_R_BOARD_R5             529U
+#define SC_R_BOARD_R6             530U
+#define SC_R_BOARD_R7             531U
+#define SC_R_MJPEG_DEC_MP         532U
+#define SC_R_MJPEG_ENC_MP         533U
+#define SC_R_VPU_TS_0             534U
+#define SC_R_VPU_MU_0             535U
+#define SC_R_VPU_MU_1             536U
+#define SC_R_VPU_MU_2             537U
+#define SC_R_VPU_MU_3             538U
+#define SC_R_VPU_ENC_1            539U
+#define SC_R_VPU                  540U
+#define SC_R_LAST                 541U
+#define SC_R_ALL                  ((sc_rsrc_t) UINT16_MAX)  /*!< All resources */
+/*@}*/
+
+/* NOTE - please add by replacing some of the UNUSED from above! */
+
+/*!
+ * Defnes for sc_ctrl_t.
+ */
+#define SC_C_TEMP                       0U
+#define SC_C_TEMP_HI                    1U
+#define SC_C_TEMP_LOW                   2U
+#define SC_C_PXL_LINK_MST1_ADDR         3U
+#define SC_C_PXL_LINK_MST2_ADDR         4U
+#define SC_C_PXL_LINK_MST_ENB           5U
+#define SC_C_PXL_LINK_MST1_ENB          6U
+#define SC_C_PXL_LINK_MST2_ENB          7U
+#define SC_C_PXL_LINK_SLV1_ADDR         8U
+#define SC_C_PXL_LINK_SLV2_ADDR         9U
+#define SC_C_PXL_LINK_MST_VLD           10U
+#define SC_C_PXL_LINK_MST1_VLD          11U
+#define SC_C_PXL_LINK_MST2_VLD          12U
+#define SC_C_SINGLE_MODE                13U
+#define SC_C_ID                         14U
+#define SC_C_PXL_CLK_POLARITY           15U
+#define SC_C_LINESTATE                  16U
+#define SC_C_PCIE_G_RST                 17U
+#define SC_C_PCIE_BUTTON_RST            18U
+#define SC_C_PCIE_PERST                 19U
+#define SC_C_PHY_RESET                  20U
+#define SC_C_PXL_LINK_RATE_CORRECTION   21U
+#define SC_C_PANIC                      22U
+#define SC_C_PRIORITY_GROUP             23U
+#define SC_C_TXCLK                      24U
+#define SC_C_CLKDIV                     25U
+#define SC_C_DISABLE_50                 26U
+#define SC_C_DISABLE_125                27U
+#define SC_C_SEL_125                    28U
+#define SC_C_MODE                       29U
+#define SC_C_SYNC_CTRL0                 30U
+#define SC_C_KACHUNK_CNT                31U
+#define SC_C_KACHUNK_SEL                32U
+#define SC_C_SYNC_CTRL1                 33U
+#define SC_C_DPI_RESET                  34U
+#define SC_C_MIPI_RESET                 35U
+#define SC_C_DUAL_MODE                  36U
+#define SC_C_VOLTAGE                    37U
+#define SC_C_PXL_LINK_SEL               38U
+#define SC_C_OFS_SEL                    39U
+#define SC_C_OFS_AUDIO                  40U
+#define SC_C_OFS_PERIPH                 41U
+#define SC_C_OFS_IRQ                    42U
+#define SC_C_RST0                       43U
+#define SC_C_RST1                       44U
+#define SC_C_SEL0                       45U
+#define SC_C_LAST                       46U
+
+#define SC_P_ALL        ((sc_pad_t) UINT16_MAX)   /*!< All pads */
+
+/* Types */
+
+/*!
+ * This type is used to store a boolean
+ */
+typedef uint8_t sc_bool_t;
+
+/*!
+ * This type is used to store a system (full-size) address.
+ */
+typedef uint64_t sc_faddr_t;
+
+/*!
+ * This type is used to indicate error response for most functions.
+ */
+typedef uint8_t sc_err_t;
+
+/*!
+ * This type is used to indicate a resource. Resources include peripherals
+ * and bus masters (but not memory regions). Note items from list should
+ * never be changed or removed (only added to at the end of the list).
+ */
+typedef uint16_t sc_rsrc_t;
+
+/*!
+ * This type is used to indicate a control.
+ */
+typedef uint8_t sc_ctrl_t;
+
+/*!
+ * This type is used to indicate a pad. Valid values are SoC specific.
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+typedef uint16_t sc_pad_t;
+
+/* Extra documentation of standard types */
+
+#ifdef DOXYGEN
+    /*!
+     * Type used to declare an 8-bit integer.
+     */
+    typedef __INT8_TYPE__ int8_t;
+
+    /*!
+     * Type used to declare a 16-bit integer.
+     */
+    typedef __INT16_TYPE__ int16_t;
+
+    /*!
+     * Type used to declare a 32-bit integer.
+     */
+    typedef __INT32_TYPE__ int32_t;
+
+    /*!
+     * Type used to declare a 64-bit integer.
+     */
+    typedef __INT64_TYPE__ int64_t;
+
+    /*!
+     * Type used to declare an 8-bit unsigned integer.
+     */
+    typedef __UINT8_TYPE__ uint8_t;
+
+    /*!
+     * Type used to declare a 16-bit unsigned integer.
+     */
+    typedef __UINT16_TYPE__ uint16_t;
+
+    /*!
+     * Type used to declare a 32-bit unsigned integer.
+     */
+    typedef __UINT32_TYPE__ uint32_t;
+
+    /*!
+     * Type used to declare a 64-bit unsigned integer.
+     */
+    typedef __UINT64_TYPE__ uint64_t;
+#endif
+
+#endif /* SC_TYPES_H */
+
diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile
new file mode 100644
index 0000000000..cfb7e34653
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += sci/svc/misc/rpc_clnt.o
+obj-y += sci/svc/pad/rpc_clnt.o
+obj-y += sci/svc/pm/rpc_clnt.o
+obj-y += sci/svc/rm/rpc_clnt.o
+obj-y += sci/svc/timer/rpc_clnt.o
diff --git a/arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h b/arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h
new file mode 100644
index 0000000000..ca0653d4da
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/sci/svc/irq/rpc.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file for the IRQ RPC implementation.
+ *
+ * @addtogroup IRQ_SVC
+ * @{
+ */
+
+#ifndef SC_IRQ_RPC_H
+#define SC_IRQ_RPC_H
+
+/* Includes */
+
+/* Defines */
+
+/*!
+ * @name Defines for RPC IRQ function calls
+ */
+/*@{*/
+#define IRQ_FUNC_UNKNOWN 0 /*!< Unknown function */
+#define IRQ_FUNC_ENABLE 1U /*!< Index for irq_enable() RPC call */
+#define IRQ_FUNC_STATUS 2U /*!< Index for irq_status() RPC call */
+/*@}*/
+
+/* Types */
+
+/* Functions */
+
+/*!
+ * This function dispatches an incoming IRQ RPC request.
+ *
+ * @param[in]     caller_pt   caller partition
+ * @param[in]     msg         pointer to RPC message
+ */
+void irq_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
+
+/*!
+ * This function translates and dispatches an IRQ RPC request.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     msg         pointer to RPC message
+ */
+void irq_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
+
+#endif /* SC_IRQ_RPC_H */
+
+/**@}*/
+
diff --git a/arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c b/arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c
new file mode 100644
index 0000000000..8ecff72e21
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/sci/svc/irq/rpc_clnt.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * File containing client-side RPC functions for the IRQ service. These
+ * functions are ported to clients that communicate to the SC.
+ *
+ * @addtogroup IRQ_SVC
+ * @{
+ */
+
+/* Includes */
+
+#include <asm/arch/sci/types.h>
+#include <asm/arch/sci/svc/rm/api.h>
+#include <asm/arch/sci/svc/irq/api.h>
+#include <asm/arch/sci/rpc.h>
+#include "rpc.h"
+
+/* Local Defines */
+
+/* Local Types */
+
+/* Local Functions */
+
+sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_irq_group_t group, uint32_t mask, sc_bool_t enable)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_IRQ;
+    RPC_FUNC(&msg) = (uint8_t) IRQ_FUNC_ENABLE;
+    RPC_U32(&msg, 0U) = (uint32_t) mask;
+    RPC_U16(&msg, 4U) = (uint16_t) resource;
+    RPC_U8(&msg, 6U) = (uint8_t) group;
+    RPC_U8(&msg, 7U) = (uint8_t) enable;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_irq_group_t group, uint32_t *status)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_IRQ;
+    RPC_FUNC(&msg) = (uint8_t) IRQ_FUNC_STATUS;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U8(&msg, 2U) = (uint8_t) group;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (status != NULL)
+    {
+        *status = RPC_U32(&msg, 0U);
+    }
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+/**@}*/
+
diff --git a/arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h b/arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h
new file mode 100644
index 0000000000..fee681d889
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/sci/svc/misc/rpc.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file for the MISC RPC implementation.
+ *
+ * @addtogroup MISC_SVC
+ * @{
+ */
+
+#ifndef SC_MISC_RPC_H
+#define SC_MISC_RPC_H
+
+/* Includes */
+
+/* Defines */
+
+/*!
+ * @name Defines for RPC MISC function calls
+ */
+/*@{*/
+#define MISC_FUNC_UNKNOWN 0 /*!< Unknown function */
+#define MISC_FUNC_SET_CONTROL 1U /*!< Index for misc_set_control() RPC call */
+#define MISC_FUNC_GET_CONTROL 2U /*!< Index for misc_get_control() RPC call */
+#define MISC_FUNC_SET_MAX_DMA_GROUP 4U /*!< Index for misc_set_max_dma_group() RPC call */
+#define MISC_FUNC_SET_DMA_GROUP 5U /*!< Index for misc_set_dma_group() RPC call */
+#define MISC_FUNC_SECO_IMAGE_LOAD 8U /*!< Index for misc_seco_image_load() RPC call */
+#define MISC_FUNC_SECO_AUTHENTICATE 9U /*!< Index for misc_seco_authenticate() RPC call */
+#define MISC_FUNC_SECO_FUSE_WRITE 20U /*!< Index for misc_seco_fuse_write() RPC call */
+#define MISC_FUNC_SECO_ENABLE_DEBUG 21U /*!< Index for misc_seco_enable_debug() RPC call */
+#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U /*!< Index for misc_seco_forward_lifecycle() RPC call */
+#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U /*!< Index for misc_seco_return_lifecycle() RPC call */
+#define MISC_FUNC_SECO_BUILD_INFO 24U /*!< Index for misc_seco_build_info() RPC call */
+#define MISC_FUNC_DEBUG_OUT 10U /*!< Index for misc_debug_out() RPC call */
+#define MISC_FUNC_WAVEFORM_CAPTURE 6U /*!< Index for misc_waveform_capture() RPC call */
+#define MISC_FUNC_BUILD_INFO 15U /*!< Index for misc_build_info() RPC call */
+#define MISC_FUNC_UNIQUE_ID 19U /*!< Index for misc_unique_id() RPC call */
+#define MISC_FUNC_SET_ARI 3U /*!< Index for misc_set_ari() RPC call */
+#define MISC_FUNC_BOOT_STATUS 7U /*!< Index for misc_boot_status() RPC call */
+#define MISC_FUNC_BOOT_DONE 14U /*!< Index for misc_boot_done() RPC call */
+#define MISC_FUNC_OTP_FUSE_READ 11U /*!< Index for misc_otp_fuse_read() RPC call */
+#define MISC_FUNC_OTP_FUSE_WRITE 17U /*!< Index for misc_otp_fuse_write() RPC call */
+#define MISC_FUNC_SET_TEMP 12U /*!< Index for misc_set_temp() RPC call */
+#define MISC_FUNC_GET_TEMP 13U /*!< Index for misc_get_temp() RPC call */
+#define MISC_FUNC_GET_BOOT_DEV 16U /*!< Index for misc_get_boot_dev() RPC call */
+#define MISC_FUNC_GET_BUTTON_STATUS 18U /*!< Index for misc_get_button_status() RPC call */
+/*@}*/
+
+/* Types */
+
+/* Functions */
+
+/*!
+ * This function dispatches an incoming MISC RPC request.
+ *
+ * @param[in]     caller_pt   caller partition
+ * @param[in]     msg         pointer to RPC message
+ */
+void misc_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
+
+/*!
+ * This function translates and dispatches an MISC RPC request.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     msg         pointer to RPC message
+ */
+void misc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
+
+#endif /* SC_MISC_RPC_H */
+
+/**@}*/
+
diff --git a/arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c b/arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c
new file mode 100644
index 0000000000..b4a9741986
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/sci/svc/misc/rpc_clnt.c
@@ -0,0 +1,515 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * File containing client-side RPC functions for the MISC service. These
+ * functions are ported to clients that communicate to the SC.
+ *
+ * @addtogroup MISC_SVC
+ * @{
+ */
+
+/* Includes */
+
+#include <asm/arch/sci/types.h>
+#include <asm/arch/sci/svc/rm/api.h>
+#include <asm/arch/sci/svc/misc/api.h>
+#include <asm/arch/sci/rpc.h>
+#include "rpc.h"
+
+/* Local Defines */
+
+/* Local Types */
+
+/* Local Functions */
+
+sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_ctrl_t ctrl, uint32_t val)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_CONTROL;
+    RPC_U32(&msg, 0U) = (uint32_t) ctrl;
+    RPC_U32(&msg, 4U) = (uint32_t) val;
+    RPC_U16(&msg, 8U) = (uint16_t) resource;
+    RPC_SIZE(&msg) = 4U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_ctrl_t ctrl, uint32_t *val)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_CONTROL;
+    RPC_U32(&msg, 0U) = (uint32_t) ctrl;
+    RPC_U16(&msg, 4U) = (uint16_t) resource;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (val != NULL)
+    {
+        *val = RPC_U32(&msg, 0U);
+    }
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_misc_dma_group_t max)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_MAX_DMA_GROUP;
+    RPC_U8(&msg, 0U) = (uint8_t) pt;
+    RPC_U8(&msg, 1U) = (uint8_t) max;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_misc_dma_group_t group)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_DMA_GROUP;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U8(&msg, 2U) = (uint8_t) group;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src,
+    sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_IMAGE_LOAD;
+    RPC_U32(&msg, 0U) = (uint32_t) (addr_src >> 32U);
+    RPC_U32(&msg, 4U) = (uint32_t) addr_src;
+    RPC_U32(&msg, 8U) = (uint32_t) (addr_dst >> 32U);
+    RPC_U32(&msg, 12U) = (uint32_t) addr_dst;
+    RPC_U32(&msg, 16U) = (uint32_t) len;
+    RPC_U8(&msg, 20U) = (uint8_t) fw;
+    RPC_SIZE(&msg) = 7U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc,
+    sc_misc_seco_auth_cmd_t cmd, sc_faddr_t addr)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_AUTHENTICATE;
+    RPC_U32(&msg, 0U) = (uint32_t) (addr >> 32U);
+    RPC_U32(&msg, 4U) = (uint32_t) addr;
+    RPC_U8(&msg, 8U) = (uint8_t) cmd;
+    RPC_SIZE(&msg) = 4U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_FUSE_WRITE;
+    RPC_U32(&msg, 0U) = (uint32_t) (addr >> 32U);
+    RPC_U32(&msg, 4U) = (uint32_t) addr;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_ENABLE_DEBUG;
+    RPC_U32(&msg, 0U) = (uint32_t) (addr >> 32U);
+    RPC_U32(&msg, 4U) = (uint32_t) addr;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t lifecycle)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_FORWARD_LIFECYCLE;
+    RPC_U32(&msg, 0U) = (uint32_t) lifecycle;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_RETURN_LIFECYCLE;
+    RPC_U32(&msg, 0U) = (uint32_t) (addr >> 32U);
+    RPC_U32(&msg, 4U) = (uint32_t) addr;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version,
+    uint32_t *commit)
+{
+    sc_rpc_msg_t msg;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_BUILD_INFO;
+    RPC_SIZE(&msg) = 1U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (version != NULL)
+    {
+        *version = RPC_U32(&msg, 0U);
+    }
+
+    if (commit != NULL)
+    {
+        *commit = RPC_U32(&msg, 4U);
+    }
+
+    return;
+}
+
+void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch)
+{
+    sc_rpc_msg_t msg;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_DEBUG_OUT;
+    RPC_U8(&msg, 0U) = (uint8_t) ch;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    return;
+}
+
+sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_WAVEFORM_CAPTURE;
+    RPC_U8(&msg, 0U) = (uint8_t) enable;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build,
+    uint32_t *commit)
+{
+    sc_rpc_msg_t msg;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_BUILD_INFO;
+    RPC_SIZE(&msg) = 1U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (build != NULL)
+    {
+        *build = RPC_U32(&msg, 0U);
+    }
+
+    if (commit != NULL)
+    {
+        *commit = RPC_U32(&msg, 4U);
+    }
+
+    return;
+}
+
+void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l,
+    uint32_t *id_h)
+{
+    sc_rpc_msg_t msg;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_UNIQUE_ID;
+    RPC_SIZE(&msg) = 1U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (id_l != NULL)
+    {
+        *id_l = RPC_U32(&msg, 0U);
+    }
+
+    if (id_h != NULL)
+    {
+        *id_h = RPC_U32(&msg, 4U);
+    }
+
+    return;
+}
+
+sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_ARI;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U16(&msg, 2U) = (uint16_t) resource_mst;
+    RPC_U16(&msg, 4U) = (uint16_t) ari;
+    RPC_U8(&msg, 6U) = (uint8_t) enable;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status)
+{
+    sc_rpc_msg_t msg;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_BOOT_STATUS;
+    RPC_U8(&msg, 0U) = (uint8_t) status;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_TRUE);
+
+    return;
+}
+
+sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_BOOT_DONE;
+    RPC_U16(&msg, 0U) = (uint16_t) cpu;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_OTP_FUSE_READ;
+    RPC_U32(&msg, 0U) = (uint32_t) word;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (val != NULL)
+    {
+        *val = RPC_U32(&msg, 0U);
+    }
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_OTP_FUSE_WRITE;
+    RPC_U32(&msg, 0U) = (uint32_t) word;
+    RPC_U32(&msg, 4U) = (uint32_t) val;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_misc_temp_t temp, int16_t celsius, int8_t tenths)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_TEMP;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_I16(&msg, 2U) = (int16_t) celsius;
+    RPC_U8(&msg, 4U) = (uint8_t) temp;
+    RPC_I8(&msg, 5U) = (int8_t) tenths;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_TEMP;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U8(&msg, 2U) = (uint8_t) temp;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (celsius != NULL)
+    {
+        *celsius = RPC_I16(&msg, 0U);
+    }
+
+    result = RPC_R8(&msg);
+    if (tenths != NULL)
+    {
+        *tenths = RPC_I8(&msg, 2U);
+    }
+
+    return (sc_err_t) result;
+}
+
+void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev)
+{
+    sc_rpc_msg_t msg;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_BOOT_DEV;
+    RPC_SIZE(&msg) = 1U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (dev != NULL)
+    {
+        *dev = RPC_U16(&msg, 0U);
+    }
+
+    return;
+}
+
+void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status)
+{
+    sc_rpc_msg_t msg;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+    RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_BUTTON_STATUS;
+    RPC_SIZE(&msg) = 1U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (status != NULL)
+    {
+        *status = RPC_U8(&msg, 0U);
+    }
+
+    return;
+}
+
+/**@}*/
+
diff --git a/arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h b/arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h
new file mode 100644
index 0000000000..b658dcc23d
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/sci/svc/pad/rpc.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file for the PAD RPC implementation.
+ *
+ * @addtogroup PAD_SVC
+ * @{
+ */
+
+#ifndef SC_PAD_RPC_H
+#define SC_PAD_RPC_H
+
+/* Includes */
+
+/* Defines */
+
+/*!
+ * @name Defines for RPC PAD function calls
+ */
+/*@{*/
+#define PAD_FUNC_UNKNOWN 0 /*!< Unknown function */
+#define PAD_FUNC_SET_MUX 1U /*!< Index for pad_set_mux() RPC call */
+#define PAD_FUNC_GET_MUX 6U /*!< Index for pad_get_mux() RPC call */
+#define PAD_FUNC_SET_GP 2U /*!< Index for pad_set_gp() RPC call */
+#define PAD_FUNC_GET_GP 7U /*!< Index for pad_get_gp() RPC call */
+#define PAD_FUNC_SET_WAKEUP 4U /*!< Index for pad_set_wakeup() RPC call */
+#define PAD_FUNC_GET_WAKEUP 9U /*!< Index for pad_get_wakeup() RPC call */
+#define PAD_FUNC_SET_ALL 5U /*!< Index for pad_set_all() RPC call */
+#define PAD_FUNC_GET_ALL 10U /*!< Index for pad_get_all() RPC call */
+#define PAD_FUNC_SET 15U /*!< Index for pad_set() RPC call */
+#define PAD_FUNC_GET 16U /*!< Index for pad_get() RPC call */
+#define PAD_FUNC_SET_GP_28FDSOI 11U /*!< Index for pad_set_gp_28fdsoi() RPC call */
+#define PAD_FUNC_GET_GP_28FDSOI 12U /*!< Index for pad_get_gp_28fdsoi() RPC call */
+#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U /*!< Index for pad_set_gp_28fdsoi_hsic() RPC call */
+#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U /*!< Index for pad_get_gp_28fdsoi_hsic() RPC call */
+#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U /*!< Index for pad_set_gp_28fdsoi_comp() RPC call */
+#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U /*!< Index for pad_get_gp_28fdsoi_comp() RPC call */
+/*@}*/
+
+/* Types */
+
+/* Functions */
+
+/*!
+ * This function dispatches an incoming PAD RPC request.
+ *
+ * @param[in]     caller_pt   caller partition
+ * @param[in]     msg         pointer to RPC message
+ */
+void pad_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
+
+/*!
+ * This function translates and dispatches an PAD RPC request.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     msg         pointer to RPC message
+ */
+void pad_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
+
+#endif /* SC_PAD_RPC_H */
+
+/**@}*/
+
diff --git a/arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c b/arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c
new file mode 100644
index 0000000000..4a93c1a48e
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/sci/svc/pad/rpc_clnt.c
@@ -0,0 +1,475 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * File containing client-side RPC functions for the PAD service. These
+ * functions are ported to clients that communicate to the SC.
+ *
+ * @addtogroup PAD_SVC
+ * @{
+ */
+
+/* Includes */
+
+#include <asm/arch/sci/types.h>
+#include <asm/arch/sci/svc/rm/api.h>
+#include <asm/arch/sci/svc/pad/api.h>
+#include <asm/arch/sci/rpc.h>
+#include "rpc.h"
+
+/* Local Defines */
+
+/* Local Types */
+
+/* Local Functions */
+
+sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad,
+    uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_MUX;
+    RPC_U16(&msg, 0U) = (uint16_t) pad;
+    RPC_U8(&msg, 2U) = (uint8_t) mux;
+    RPC_U8(&msg, 3U) = (uint8_t) config;
+    RPC_U8(&msg, 4U) = (uint8_t) iso;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad,
+    uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_MUX;
+    RPC_U16(&msg, 0U) = (uint16_t) pad;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    if (mux != NULL)
+    {
+        *mux = RPC_U8(&msg, 0U);
+    }
+
+    if (config != NULL)
+    {
+        *config = RPC_U8(&msg, 1U);
+    }
+
+    if (iso != NULL)
+    {
+        *iso = RPC_U8(&msg, 2U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP;
+    RPC_U32(&msg, 0U) = (uint32_t) ctrl;
+    RPC_U16(&msg, 4U) = (uint16_t) pad;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP;
+    RPC_U16(&msg, 0U) = (uint16_t) pad;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (ctrl != NULL)
+    {
+        *ctrl = RPC_U32(&msg, 0U);
+    }
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad,
+    sc_pad_wakeup_t wakeup)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_WAKEUP;
+    RPC_U16(&msg, 0U) = (uint16_t) pad;
+    RPC_U8(&msg, 2U) = (uint8_t) wakeup;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad,
+    sc_pad_wakeup_t *wakeup)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_WAKEUP;
+    RPC_U16(&msg, 0U) = (uint16_t) pad;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    if (wakeup != NULL)
+    {
+        *wakeup = RPC_U8(&msg, 0U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux,
+    sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
+    sc_pad_wakeup_t wakeup)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_ALL;
+    RPC_U32(&msg, 0U) = (uint32_t) ctrl;
+    RPC_U16(&msg, 4U) = (uint16_t) pad;
+    RPC_U8(&msg, 6U) = (uint8_t) mux;
+    RPC_U8(&msg, 7U) = (uint8_t) config;
+    RPC_U8(&msg, 8U) = (uint8_t) iso;
+    RPC_U8(&msg, 9U) = (uint8_t) wakeup;
+    RPC_SIZE(&msg) = 4U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux,
+    sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl,
+    sc_pad_wakeup_t *wakeup)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_ALL;
+    RPC_U16(&msg, 0U) = (uint16_t) pad;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (ctrl != NULL)
+    {
+        *ctrl = RPC_U32(&msg, 0U);
+    }
+
+    result = RPC_R8(&msg);
+    if (mux != NULL)
+    {
+        *mux = RPC_U8(&msg, 4U);
+    }
+
+    if (config != NULL)
+    {
+        *config = RPC_U8(&msg, 5U);
+    }
+
+    if (iso != NULL)
+    {
+        *iso = RPC_U8(&msg, 6U);
+    }
+
+    if (wakeup != NULL)
+    {
+        *wakeup = RPC_U8(&msg, 7U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET;
+    RPC_U32(&msg, 0U) = (uint32_t) val;
+    RPC_U16(&msg, 4U) = (uint16_t) pad;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET;
+    RPC_U16(&msg, 0U) = (uint16_t) pad;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (val != NULL)
+    {
+        *val = RPC_U32(&msg, 0U);
+    }
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
+    sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP_28FDSOI;
+    RPC_U16(&msg, 0U) = (uint16_t) pad;
+    RPC_U8(&msg, 2U) = (uint8_t) dse;
+    RPC_U8(&msg, 3U) = (uint8_t) ps;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
+    sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP_28FDSOI;
+    RPC_U16(&msg, 0U) = (uint16_t) pad;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    if (dse != NULL)
+    {
+        *dse = RPC_U8(&msg, 0U);
+    }
+
+    if (ps != NULL)
+    {
+        *ps = RPC_U8(&msg, 1U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
+    sc_pad_28fdsoi_dse_t dse, sc_bool_t hys, sc_pad_28fdsoi_pus_t pus,
+    sc_bool_t pke, sc_bool_t pue)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP_28FDSOI_HSIC;
+    RPC_U16(&msg, 0U) = (uint16_t) pad;
+    RPC_U8(&msg, 2U) = (uint8_t) dse;
+    RPC_U8(&msg, 3U) = (uint8_t) pus;
+    RPC_U8(&msg, 4U) = (uint8_t) hys;
+    RPC_U8(&msg, 5U) = (uint8_t) pke;
+    RPC_U8(&msg, 6U) = (uint8_t) pue;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
+    sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys, sc_pad_28fdsoi_pus_t *pus,
+    sc_bool_t *pke, sc_bool_t *pue)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP_28FDSOI_HSIC;
+    RPC_U16(&msg, 0U) = (uint16_t) pad;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    if (dse != NULL)
+    {
+        *dse = RPC_U8(&msg, 0U);
+    }
+
+    if (pus != NULL)
+    {
+        *pus = RPC_U8(&msg, 1U);
+    }
+
+    if (hys != NULL)
+    {
+        *hys = RPC_U8(&msg, 2U);
+    }
+
+    if (pke != NULL)
+    {
+        *pke = RPC_U8(&msg, 3U);
+    }
+
+    if (pue != NULL)
+    {
+        *pue = RPC_U8(&msg, 4U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
+    uint8_t compen, sc_bool_t fastfrz, uint8_t rasrcp, uint8_t rasrcn,
+    sc_bool_t nasrc_sel, sc_bool_t psw_ovr)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP_28FDSOI_COMP;
+    RPC_U16(&msg, 0U) = (uint16_t) pad;
+    RPC_U8(&msg, 2U) = (uint8_t) compen;
+    RPC_U8(&msg, 3U) = (uint8_t) rasrcp;
+    RPC_U8(&msg, 4U) = (uint8_t) rasrcn;
+    RPC_U8(&msg, 5U) = (uint8_t) fastfrz;
+    RPC_U8(&msg, 6U) = (uint8_t) nasrc_sel;
+    RPC_U8(&msg, 7U) = (uint8_t) psw_ovr;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
+    uint8_t *compen, sc_bool_t *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn,
+    sc_bool_t *nasrc_sel, sc_bool_t *compok, uint8_t *nasrc, sc_bool_t *psw_ovr)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP_28FDSOI_COMP;
+    RPC_U16(&msg, 0U) = (uint16_t) pad;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    if (compen != NULL)
+    {
+        *compen = RPC_U8(&msg, 0U);
+    }
+
+    if (rasrcp != NULL)
+    {
+        *rasrcp = RPC_U8(&msg, 1U);
+    }
+
+    if (rasrcn != NULL)
+    {
+        *rasrcn = RPC_U8(&msg, 2U);
+    }
+
+    if (nasrc != NULL)
+    {
+        *nasrc = RPC_U8(&msg, 3U);
+    }
+
+    if (fastfrz != NULL)
+    {
+        *fastfrz = RPC_U8(&msg, 4U);
+    }
+
+    if (nasrc_sel != NULL)
+    {
+        *nasrc_sel = RPC_U8(&msg, 5U);
+    }
+
+    if (compok != NULL)
+    {
+        *compok = RPC_U8(&msg, 6U);
+    }
+
+    if (psw_ovr != NULL)
+    {
+        *psw_ovr = RPC_U8(&msg, 7U);
+    }
+
+    return (sc_err_t) result;
+}
+
+/**@}*/
+
diff --git a/arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h b/arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h
new file mode 100644
index 0000000000..49046c2ca7
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/sci/svc/pm/rpc.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file for the PM RPC implementation.
+ *
+ * @addtogroup PM_SVC
+ * @{
+ */
+
+#ifndef SC_PM_RPC_H
+#define SC_PM_RPC_H
+
+/* Includes */
+
+/* Defines */
+
+/*!
+ * @name Defines for RPC PM function calls
+ */
+/*@{*/
+#define PM_FUNC_UNKNOWN 0 /*!< Unknown function */
+#define PM_FUNC_SET_SYS_POWER_MODE 19U /*!< Index for pm_set_sys_power_mode() RPC call */
+#define PM_FUNC_SET_PARTITION_POWER_MODE 1U /*!< Index for pm_set_partition_power_mode() RPC call */
+#define PM_FUNC_GET_SYS_POWER_MODE 2U /*!< Index for pm_get_sys_power_mode() RPC call */
+#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U /*!< Index for pm_set_resource_power_mode() RPC call */
+#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U /*!< Index for pm_get_resource_power_mode() RPC call */
+#define PM_FUNC_REQ_LOW_POWER_MODE 16U /*!< Index for pm_req_low_power_mode() RPC call */
+#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U /*!< Index for pm_req_cpu_low_power_mode() RPC call */
+#define PM_FUNC_SET_CPU_RESUME_ADDR 17U /*!< Index for pm_set_cpu_resume_addr() RPC call */
+#define PM_FUNC_SET_CPU_RESUME 21U /*!< Index for pm_set_cpu_resume() RPC call */
+#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U /*!< Index for pm_req_sys_if_power_mode() RPC call */
+#define PM_FUNC_SET_CLOCK_RATE 5U /*!< Index for pm_set_clock_rate() RPC call */
+#define PM_FUNC_GET_CLOCK_RATE 6U /*!< Index for pm_get_clock_rate() RPC call */
+#define PM_FUNC_CLOCK_ENABLE 7U /*!< Index for pm_clock_enable() RPC call */
+#define PM_FUNC_SET_CLOCK_PARENT 14U /*!< Index for pm_set_clock_parent() RPC call */
+#define PM_FUNC_GET_CLOCK_PARENT 15U /*!< Index for pm_get_clock_parent() RPC call */
+#define PM_FUNC_RESET 13U /*!< Index for pm_reset() RPC call */
+#define PM_FUNC_RESET_REASON 10U /*!< Index for pm_reset_reason() RPC call */
+#define PM_FUNC_BOOT 8U /*!< Index for pm_boot() RPC call */
+#define PM_FUNC_REBOOT 9U /*!< Index for pm_reboot() RPC call */
+#define PM_FUNC_REBOOT_PARTITION 12U /*!< Index for pm_reboot_partition() RPC call */
+#define PM_FUNC_CPU_START 11U /*!< Index for pm_cpu_start() RPC call */
+/*@}*/
+
+/* Types */
+
+/* Functions */
+
+/*!
+ * This function dispatches an incoming PM RPC request.
+ *
+ * @param[in]     caller_pt   caller partition
+ * @param[in]     msg         pointer to RPC message
+ */
+void pm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
+
+/*!
+ * This function translates and dispatches an PM RPC request.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     msg         pointer to RPC message
+ */
+void pm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
+
+#endif /* SC_PM_RPC_H */
+
+/**@}*/
+
diff --git a/arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c b/arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c
new file mode 100644
index 0000000000..6cad000354
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/sci/svc/pm/rpc_clnt.c
@@ -0,0 +1,460 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * File containing client-side RPC functions for the PM service. These
+ * functions are ported to clients that communicate to the SC.
+ *
+ * @addtogroup PM_SVC
+ * @{
+ */
+
+/* Includes */
+
+#include <asm/arch/sci/types.h>
+#include <asm/arch/sci/svc/rm/api.h>
+#include <asm/arch/sci/svc/pm/api.h>
+#include <asm/arch/sci/rpc.h>
+#include "rpc.h"
+
+/* Local Defines */
+
+/* Local Types */
+
+/* Local Functions */
+
+sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_SYS_POWER_MODE;
+    RPC_U8(&msg, 0U) = (uint8_t) mode;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_pm_power_mode_t mode)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_PARTITION_POWER_MODE;
+    RPC_U8(&msg, 0U) = (uint8_t) pt;
+    RPC_U8(&msg, 1U) = (uint8_t) mode;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_pm_power_mode_t *mode)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_GET_SYS_POWER_MODE;
+    RPC_U8(&msg, 0U) = (uint8_t) pt;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    if (mode != NULL)
+    {
+        *mode = RPC_U8(&msg, 0U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_power_mode_t mode)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_RESOURCE_POWER_MODE;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U8(&msg, 2U) = (uint8_t) mode;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_power_mode_t *mode)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_GET_RESOURCE_POWER_MODE;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    if (mode != NULL)
+    {
+        *mode = RPC_U8(&msg, 0U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_power_mode_t mode)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REQ_LOW_POWER_MODE;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U8(&msg, 2U) = (uint8_t) mode;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REQ_CPU_LOW_POWER_MODE;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U8(&msg, 2U) = (uint8_t) mode;
+    RPC_U8(&msg, 3U) = (uint8_t) wake_src;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_faddr_t address)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_CPU_RESUME_ADDR;
+    RPC_U32(&msg, 0U) = (uint32_t) (address >> 32U);
+    RPC_U32(&msg, 4U) = (uint32_t) address;
+    RPC_U16(&msg, 8U) = (uint16_t) resource;
+    RPC_SIZE(&msg) = 4U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_bool_t isPrimary, sc_faddr_t address)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_CPU_RESUME;
+    RPC_U32(&msg, 0U) = (uint32_t) (address >> 32U);
+    RPC_U32(&msg, 4U) = (uint32_t) address;
+    RPC_U16(&msg, 8U) = (uint16_t) resource;
+    RPC_U8(&msg, 10U) = (uint8_t) isPrimary;
+    RPC_SIZE(&msg) = 4U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REQ_SYS_IF_POWER_MODE;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U8(&msg, 2U) = (uint8_t) sys_if;
+    RPC_U8(&msg, 3U) = (uint8_t) hpm;
+    RPC_U8(&msg, 4U) = (uint8_t) lpm;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_CLOCK_RATE;
+    RPC_U32(&msg, 0U) = *(uint32_t*) rate;
+    RPC_U16(&msg, 4U) = (uint16_t) resource;
+    RPC_U8(&msg, 6U) = (uint8_t) clk;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    *rate = RPC_U32(&msg, 0U);
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_GET_CLOCK_RATE;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U8(&msg, 2U) = (uint8_t) clk;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (rate != NULL)
+    {
+        *rate = RPC_U32(&msg, 0U);
+    }
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_CLOCK_ENABLE;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U8(&msg, 2U) = (uint8_t) clk;
+    RPC_U8(&msg, 3U) = (uint8_t) enable;
+    RPC_U8(&msg, 4U) = (uint8_t) autog;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_pm_clk_parent_t parent)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_CLOCK_PARENT;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U8(&msg, 2U) = (uint8_t) clk;
+    RPC_U8(&msg, 3U) = (uint8_t) parent;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_pm_clk_parent_t *parent)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_GET_CLOCK_PARENT;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U8(&msg, 2U) = (uint8_t) clk;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    if (parent != NULL)
+    {
+        *parent = RPC_U8(&msg, 0U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_RESET;
+    RPC_U8(&msg, 0U) = (uint8_t) type;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_RESET_REASON;
+    RPC_SIZE(&msg) = 1U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    if (reason != NULL)
+    {
+        *reason = RPC_U8(&msg, 0U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
+    sc_rsrc_t resource_mu, sc_rsrc_t resource_dev)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_BOOT;
+    RPC_U32(&msg, 0U) = (uint32_t) (boot_addr >> 32U);
+    RPC_U32(&msg, 4U) = (uint32_t) boot_addr;
+    RPC_U16(&msg, 8U) = (uint16_t) resource_cpu;
+    RPC_U16(&msg, 10U) = (uint16_t) resource_mu;
+    RPC_U16(&msg, 12U) = (uint16_t) resource_dev;
+    RPC_U8(&msg, 14U) = (uint8_t) pt;
+    RPC_SIZE(&msg) = 5U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
+{
+    sc_rpc_msg_t msg;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REBOOT;
+    RPC_U8(&msg, 0U) = (uint8_t) type;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_TRUE);
+
+    return;
+}
+
+sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_pm_reset_type_t type)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REBOOT_PARTITION;
+    RPC_U8(&msg, 0U) = (uint8_t) pt;
+    RPC_U8(&msg, 1U) = (uint8_t) type;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
+    sc_faddr_t address)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = (uint8_t) PM_FUNC_CPU_START;
+    RPC_U32(&msg, 0U) = (uint32_t) (address >> 32U);
+    RPC_U32(&msg, 4U) = (uint32_t) address;
+    RPC_U16(&msg, 8U) = (uint16_t) resource;
+    RPC_U8(&msg, 10U) = (uint8_t) enable;
+    RPC_SIZE(&msg) = 4U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+/**@}*/
+
diff --git a/arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h b/arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h
new file mode 100644
index 0000000000..196615e937
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/sci/svc/rm/rpc.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file for the RM RPC implementation.
+ *
+ * @addtogroup RM_SVC
+ * @{
+ */
+
+#ifndef SC_RM_RPC_H
+#define SC_RM_RPC_H
+
+/* Includes */
+
+/* Defines */
+
+/*!
+ * @name Defines for RPC RM function calls
+ */
+/*@{*/
+#define RM_FUNC_UNKNOWN 0 /*!< Unknown function */
+#define RM_FUNC_PARTITION_ALLOC 1U /*!< Index for rm_partition_alloc() RPC call */
+#define RM_FUNC_SET_CONFIDENTIAL 31U /*!< Index for rm_set_confidential() RPC call */
+#define RM_FUNC_PARTITION_FREE 2U /*!< Index for rm_partition_free() RPC call */
+#define RM_FUNC_GET_DID 26U /*!< Index for rm_get_did() RPC call */
+#define RM_FUNC_PARTITION_STATIC 3U /*!< Index for rm_partition_static() RPC call */
+#define RM_FUNC_PARTITION_LOCK 4U /*!< Index for rm_partition_lock() RPC call */
+#define RM_FUNC_GET_PARTITION 5U /*!< Index for rm_get_partition() RPC call */
+#define RM_FUNC_SET_PARENT 6U /*!< Index for rm_set_parent() RPC call */
+#define RM_FUNC_MOVE_ALL 7U /*!< Index for rm_move_all() RPC call */
+#define RM_FUNC_ASSIGN_RESOURCE 8U /*!< Index for rm_assign_resource() RPC call */
+#define RM_FUNC_SET_RESOURCE_MOVABLE 9U /*!< Index for rm_set_resource_movable() RPC call */
+#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U /*!< Index for rm_set_subsys_rsrc_movable() RPC call */
+#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U /*!< Index for rm_set_master_attributes() RPC call */
+#define RM_FUNC_SET_MASTER_SID 11U /*!< Index for rm_set_master_sid() RPC call */
+#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U /*!< Index for rm_set_peripheral_permissions() RPC call */
+#define RM_FUNC_IS_RESOURCE_OWNED 13U /*!< Index for rm_is_resource_owned() RPC call */
+#define RM_FUNC_IS_RESOURCE_MASTER 14U /*!< Index for rm_is_resource_master() RPC call */
+#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U /*!< Index for rm_is_resource_peripheral() RPC call */
+#define RM_FUNC_GET_RESOURCE_INFO 16U /*!< Index for rm_get_resource_info() RPC call */
+#define RM_FUNC_MEMREG_ALLOC 17U /*!< Index for rm_memreg_alloc() RPC call */
+#define RM_FUNC_MEMREG_SPLIT 29U /*!< Index for rm_memreg_split() RPC call */
+#define RM_FUNC_MEMREG_FREE 18U /*!< Index for rm_memreg_free() RPC call */
+#define RM_FUNC_FIND_MEMREG 30U /*!< Index for rm_find_memreg() RPC call */
+#define RM_FUNC_ASSIGN_MEMREG 19U /*!< Index for rm_assign_memreg() RPC call */
+#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U /*!< Index for rm_set_memreg_permissions() RPC call */
+#define RM_FUNC_IS_MEMREG_OWNED 21U /*!< Index for rm_is_memreg_owned() RPC call */
+#define RM_FUNC_GET_MEMREG_INFO 22U /*!< Index for rm_get_memreg_info() RPC call */
+#define RM_FUNC_ASSIGN_PAD 23U /*!< Index for rm_assign_pad() RPC call */
+#define RM_FUNC_SET_PAD_MOVABLE 24U /*!< Index for rm_set_pad_movable() RPC call */
+#define RM_FUNC_IS_PAD_OWNED 25U /*!< Index for rm_is_pad_owned() RPC call */
+#define RM_FUNC_DUMP 27U /*!< Index for rm_dump() RPC call */
+/*@}*/
+
+/* Types */
+
+/* Functions */
+
+/*!
+ * This function dispatches an incoming RM RPC request.
+ *
+ * @param[in]     caller_pt   caller partition
+ * @param[in]     msg         pointer to RPC message
+ */
+void rm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
+
+/*!
+ * This function translates and dispatches an RM RPC request.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     msg         pointer to RPC message
+ */
+void rm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
+
+#endif /* SC_RM_RPC_H */
+
+/**@}*/
+
diff --git a/arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c b/arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c
new file mode 100644
index 0000000000..d1475cf643
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/sci/svc/rm/rpc_clnt.c
@@ -0,0 +1,645 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * File containing client-side RPC functions for the RM service. These
+ * functions are ported to clients that communicate to the SC.
+ *
+ * @addtogroup RM_SVC
+ * @{
+ */
+
+/* Includes */
+
+#include <asm/arch/sci/types.h>
+#include <asm/arch/sci/svc/rm/api.h>
+#include <asm/arch/sci/rpc.h>
+#include "rpc.h"
+
+/* Local Defines */
+
+/* Local Types */
+
+/* Local Functions */
+
+sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
+    sc_bool_t isolated, sc_bool_t restricted, sc_bool_t grant, sc_bool_t coherent)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_ALLOC;
+    RPC_U8(&msg, 0U) = (uint8_t) secure;
+    RPC_U8(&msg, 1U) = (uint8_t) isolated;
+    RPC_U8(&msg, 2U) = (uint8_t) restricted;
+    RPC_U8(&msg, 3U) = (uint8_t) grant;
+    RPC_U8(&msg, 4U) = (uint8_t) coherent;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    if (pt != NULL)
+    {
+        *pt = RPC_U8(&msg, 0U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_CONFIDENTIAL;
+    RPC_U8(&msg, 0U) = (uint8_t) pt;
+    RPC_U8(&msg, 1U) = (uint8_t) retro;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_FREE;
+    RPC_U8(&msg, 0U) = (uint8_t) pt;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_DID;
+    RPC_SIZE(&msg) = 1U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_rm_did_t) result;
+}
+
+sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_rm_did_t did)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_STATIC;
+    RPC_U8(&msg, 0U) = (uint8_t) pt;
+    RPC_U8(&msg, 1U) = (uint8_t) did;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_LOCK;
+    RPC_U8(&msg, 0U) = (uint8_t) pt;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_PARTITION;
+    RPC_SIZE(&msg) = 1U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    if (pt != NULL)
+    {
+        *pt = RPC_U8(&msg, 0U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_rm_pt_t pt_parent)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_PARENT;
+    RPC_U8(&msg, 0U) = (uint8_t) pt;
+    RPC_U8(&msg, 1U) = (uint8_t) pt_parent;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
+    sc_bool_t move_rsrc, sc_bool_t move_pads)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MOVE_ALL;
+    RPC_U8(&msg, 0U) = (uint8_t) pt_src;
+    RPC_U8(&msg, 1U) = (uint8_t) pt_dst;
+    RPC_U8(&msg, 2U) = (uint8_t) move_rsrc;
+    RPC_U8(&msg, 3U) = (uint8_t) move_pads;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_rsrc_t resource)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_ASSIGN_RESOURCE;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U8(&msg, 2U) = (uint8_t) pt;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
+    sc_rsrc_t resource_lst, sc_bool_t movable)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_RESOURCE_MOVABLE;
+    RPC_U16(&msg, 0U) = (uint16_t) resource_fst;
+    RPC_U16(&msg, 2U) = (uint16_t) resource_lst;
+    RPC_U8(&msg, 4U) = (uint8_t) movable;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_bool_t movable)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_SUBSYS_RSRC_MOVABLE;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U8(&msg, 2U) = (uint8_t) movable;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_rm_spa_t sa, sc_rm_spa_t pa, sc_bool_t smmu_bypass)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_MASTER_ATTRIBUTES;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U8(&msg, 2U) = (uint8_t) sa;
+    RPC_U8(&msg, 3U) = (uint8_t) pa;
+    RPC_U8(&msg, 4U) = (uint8_t) smmu_bypass;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_rm_sid_t sid)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_MASTER_SID;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U16(&msg, 2U) = (uint16_t) sid;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_rm_pt_t pt, sc_rm_perm_t perm)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_PERIPHERAL_PERMISSIONS;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_U8(&msg, 2U) = (uint8_t) pt;
+    RPC_U8(&msg, 3U) = (uint8_t) perm;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_RESOURCE_OWNED;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_bool_t) result;
+}
+
+sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_RESOURCE_MASTER;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_bool_t) result;
+}
+
+sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_RESOURCE_PERIPHERAL;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_bool_t) result;
+}
+
+sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_rm_sid_t *sid)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_RESOURCE_INFO;
+    RPC_U16(&msg, 0U) = (uint16_t) resource;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (sid != NULL)
+    {
+        *sid = RPC_U16(&msg, 0U);
+    }
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr,
+    sc_faddr_t addr_start, sc_faddr_t addr_end)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MEMREG_ALLOC;
+    RPC_U32(&msg, 0U) = (uint32_t) (addr_start >> 32U);
+    RPC_U32(&msg, 4U) = (uint32_t) addr_start;
+    RPC_U32(&msg, 8U) = (uint32_t) (addr_end >> 32U);
+    RPC_U32(&msg, 12U) = (uint32_t) addr_end;
+    RPC_SIZE(&msg) = 5U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    if (mr != NULL)
+    {
+        *mr = RPC_U8(&msg, 0U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr,
+    sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MEMREG_SPLIT;
+    RPC_U32(&msg, 0U) = (uint32_t) (addr_start >> 32U);
+    RPC_U32(&msg, 4U) = (uint32_t) addr_start;
+    RPC_U32(&msg, 8U) = (uint32_t) (addr_end >> 32U);
+    RPC_U32(&msg, 12U) = (uint32_t) addr_end;
+    RPC_U8(&msg, 16U) = (uint8_t) mr;
+    RPC_SIZE(&msg) = 6U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    if (mr_ret != NULL)
+    {
+        *mr_ret = RPC_U8(&msg, 0U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MEMREG_FREE;
+    RPC_U8(&msg, 0U) = (uint8_t) mr;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr,
+    sc_faddr_t addr_start, sc_faddr_t addr_end)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_FIND_MEMREG;
+    RPC_U32(&msg, 0U) = (uint32_t) (addr_start >> 32U);
+    RPC_U32(&msg, 4U) = (uint32_t) addr_start;
+    RPC_U32(&msg, 8U) = (uint32_t) (addr_end >> 32U);
+    RPC_U32(&msg, 12U) = (uint32_t) addr_end;
+    RPC_SIZE(&msg) = 5U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    if (mr != NULL)
+    {
+        *mr = RPC_U8(&msg, 0U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_ASSIGN_MEMREG;
+    RPC_U8(&msg, 0U) = (uint8_t) pt;
+    RPC_U8(&msg, 1U) = (uint8_t) mr;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
+    sc_rm_pt_t pt, sc_rm_perm_t perm)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_MEMREG_PERMISSIONS;
+    RPC_U8(&msg, 0U) = (uint8_t) mr;
+    RPC_U8(&msg, 1U) = (uint8_t) pt;
+    RPC_U8(&msg, 2U) = (uint8_t) perm;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_MEMREG_OWNED;
+    RPC_U8(&msg, 0U) = (uint8_t) mr;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_bool_t) result;
+}
+
+sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr,
+    sc_faddr_t *addr_start, sc_faddr_t *addr_end)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_MEMREG_INFO;
+    RPC_U8(&msg, 0U) = (uint8_t) mr;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (addr_start != NULL)
+    {
+        *addr_start = ((uint64_t) RPC_U32(&msg, 0U) << 32U) | RPC_U32(&msg, 4U);
+    }
+
+    if (addr_end != NULL)
+    {
+        *addr_end = ((uint64_t) RPC_U32(&msg, 8U) << 32U) | RPC_U32(&msg, 12U);
+    }
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_ASSIGN_PAD;
+    RPC_U16(&msg, 0U) = (uint16_t) pad;
+    RPC_U8(&msg, 2U) = (uint8_t) pt;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
+    sc_pad_t pad_lst, sc_bool_t movable)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_PAD_MOVABLE;
+    RPC_U16(&msg, 0U) = (uint16_t) pad_fst;
+    RPC_U16(&msg, 2U) = (uint16_t) pad_lst;
+    RPC_U8(&msg, 4U) = (uint8_t) movable;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_PAD_OWNED;
+    RPC_U8(&msg, 0U) = (uint8_t) pad;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_bool_t) result;
+}
+
+void sc_rm_dump(sc_ipc_t ipc)
+{
+    sc_rpc_msg_t msg;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+    RPC_FUNC(&msg) = (uint8_t) RM_FUNC_DUMP;
+    RPC_SIZE(&msg) = 1U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    return;
+}
+
+/**@}*/
+
diff --git a/arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h b/arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h
new file mode 100644
index 0000000000..0c498e97f0
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/sci/svc/timer/rpc.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file for the TIMER RPC implementation.
+ *
+ * @addtogroup TIMER_SVC
+ * @{
+ */
+
+#ifndef SC_TIMER_RPC_H
+#define SC_TIMER_RPC_H
+
+/* Includes */
+
+/* Defines */
+
+/*!
+ * @name Defines for RPC TIMER function calls
+ */
+/*@{*/
+#define TIMER_FUNC_UNKNOWN 0 /*!< Unknown function */
+#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /*!< Index for timer_set_wdog_timeout() RPC call */
+#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /*!< Index for timer_set_wdog_pre_timeout() RPC call */
+#define TIMER_FUNC_START_WDOG 2U /*!< Index for timer_start_wdog() RPC call */
+#define TIMER_FUNC_STOP_WDOG 3U /*!< Index for timer_stop_wdog() RPC call */
+#define TIMER_FUNC_PING_WDOG 4U /*!< Index for timer_ping_wdog() RPC call */
+#define TIMER_FUNC_GET_WDOG_STATUS 5U /*!< Index for timer_get_wdog_status() RPC call */
+#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /*!< Index for timer_pt_get_wdog_status() RPC call */
+#define TIMER_FUNC_SET_WDOG_ACTION 10U /*!< Index for timer_set_wdog_action() RPC call */
+#define TIMER_FUNC_SET_RTC_TIME 6U /*!< Index for timer_set_rtc_time() RPC call */
+#define TIMER_FUNC_GET_RTC_TIME 7U /*!< Index for timer_get_rtc_time() RPC call */
+#define TIMER_FUNC_GET_RTC_SEC1970 9U /*!< Index for timer_get_rtc_sec1970() RPC call */
+#define TIMER_FUNC_SET_RTC_ALARM 8U /*!< Index for timer_set_rtc_alarm() RPC call */
+#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /*!< Index for timer_set_rtc_periodic_alarm() RPC call */
+#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /*!< Index for timer_cancel_rtc_alarm() RPC call */
+#define TIMER_FUNC_SET_RTC_CALB 11U /*!< Index for timer_set_rtc_calb() RPC call */
+/*@}*/
+
+/* Types */
+
+/* Functions */
+
+/*!
+ * This function dispatches an incoming TIMER RPC request.
+ *
+ * @param[in]     caller_pt   caller partition
+ * @param[in]     msg         pointer to RPC message
+ */
+void timer_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
+
+/*!
+ * This function translates and dispatches an TIMER RPC request.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     msg         pointer to RPC message
+ */
+void timer_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
+
+#endif /* SC_TIMER_RPC_H */
+
+/**@}*/
+
diff --git a/arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c b/arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c
new file mode 100644
index 0000000000..abdf433b5c
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/sci/svc/timer/rpc_clnt.c
@@ -0,0 +1,365 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * File containing client-side RPC functions for the TIMER service. These
+ * functions are ported to clients that communicate to the SC.
+ *
+ * @addtogroup TIMER_SVC
+ * @{
+ */
+
+/* Includes */
+
+#include <asm/arch/sci/types.h>
+#include <asm/arch/sci/svc/rm/api.h>
+#include <asm/arch/sci/svc/timer/api.h>
+#include <asm/arch/sci/rpc.h>
+#include "rpc.h"
+
+/* Local Defines */
+
+/* Local Types */
+
+/* Local Functions */
+
+sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc,
+    sc_timer_wdog_time_t timeout)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+    RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_WDOG_TIMEOUT;
+    RPC_U32(&msg, 0U) = (uint32_t) timeout;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc,
+    sc_timer_wdog_time_t pre_timeout)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+    RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_WDOG_PRE_TIMEOUT;
+    RPC_U32(&msg, 0U) = (uint32_t) pre_timeout;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+    RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_START_WDOG;
+    RPC_U8(&msg, 0U) = (uint8_t) lock;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+    RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_STOP_WDOG;
+    RPC_SIZE(&msg) = 1U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+    RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_PING_WDOG;
+    RPC_SIZE(&msg) = 1U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc,
+    sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout,
+    sc_timer_wdog_time_t *remaining_time)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+    RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_GET_WDOG_STATUS;
+    RPC_SIZE(&msg) = 1U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (timeout != NULL)
+    {
+        *timeout = RPC_U32(&msg, 0U);
+    }
+
+    if (max_timeout != NULL)
+    {
+        *max_timeout = RPC_U32(&msg, 4U);
+    }
+
+    if (remaining_time != NULL)
+    {
+        *remaining_time = RPC_U32(&msg, 8U);
+    }
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t *enb,
+    sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *remaining_time)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+    RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_PT_GET_WDOG_STATUS;
+    RPC_U8(&msg, 0U) = (uint8_t) pt;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (timeout != NULL)
+    {
+        *timeout = RPC_U32(&msg, 0U);
+    }
+
+    if (remaining_time != NULL)
+    {
+        *remaining_time = RPC_U32(&msg, 4U);
+    }
+
+    result = RPC_R8(&msg);
+    if (enb != NULL)
+    {
+        *enb = RPC_U8(&msg, 8U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc,
+    sc_rm_pt_t pt, sc_timer_wdog_action_t action)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+    RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_WDOG_ACTION;
+    RPC_U8(&msg, 0U) = (uint8_t) pt;
+    RPC_U8(&msg, 1U) = (uint8_t) action;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon,
+    uint8_t day, uint8_t hour, uint8_t min, uint8_t sec)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+    RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_RTC_TIME;
+    RPC_U16(&msg, 0U) = (uint16_t) year;
+    RPC_U8(&msg, 2U) = (uint8_t) mon;
+    RPC_U8(&msg, 3U) = (uint8_t) day;
+    RPC_U8(&msg, 4U) = (uint8_t) hour;
+    RPC_U8(&msg, 5U) = (uint8_t) min;
+    RPC_U8(&msg, 6U) = (uint8_t) sec;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon,
+    uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+    RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_GET_RTC_TIME;
+    RPC_SIZE(&msg) = 1U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (year != NULL)
+    {
+        *year = RPC_U16(&msg, 0U);
+    }
+
+    result = RPC_R8(&msg);
+    if (mon != NULL)
+    {
+        *mon = RPC_U8(&msg, 2U);
+    }
+
+    if (day != NULL)
+    {
+        *day = RPC_U8(&msg, 3U);
+    }
+
+    if (hour != NULL)
+    {
+        *hour = RPC_U8(&msg, 4U);
+    }
+
+    if (min != NULL)
+    {
+        *min = RPC_U8(&msg, 5U);
+    }
+
+    if (sec != NULL)
+    {
+        *sec = RPC_U8(&msg, 6U);
+    }
+
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+    RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_GET_RTC_SEC1970;
+    RPC_SIZE(&msg) = 1U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (sec != NULL)
+    {
+        *sec = RPC_U32(&msg, 0U);
+    }
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon,
+    uint8_t day, uint8_t hour, uint8_t min, uint8_t sec)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+    RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_RTC_ALARM;
+    RPC_U16(&msg, 0U) = (uint16_t) year;
+    RPC_U8(&msg, 2U) = (uint8_t) mon;
+    RPC_U8(&msg, 3U) = (uint8_t) day;
+    RPC_U8(&msg, 4U) = (uint8_t) hour;
+    RPC_U8(&msg, 5U) = (uint8_t) min;
+    RPC_U8(&msg, 6U) = (uint8_t) sec;
+    RPC_SIZE(&msg) = 3U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+    RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_RTC_PERIODIC_ALARM;
+    RPC_U32(&msg, 0U) = (uint32_t) sec;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+    RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_CANCEL_RTC_ALARM;
+    RPC_SIZE(&msg) = 1U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+    RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_RTC_CALB;
+    RPC_I8(&msg, 0U) = (int8_t) count;
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+/**@}*/
+
diff --git a/include/dt-bindings/pinctrl/pads-imx8qm.h b/include/dt-bindings/pinctrl/pads-imx8qm.h
new file mode 100644
index 0000000000..ba75ecb7a5
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pads-imx8qm.h
@@ -0,0 +1,975 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file used to configure SoC pad list.
+ */
+
+#ifndef SC_PADS_H
+#define SC_PADS_H
+
+/* Includes */
+
+/* Defines */
+
+/*!
+ * @name Pad Definitions
+ */
+/*@{*/
+#define SC_P_SIM0_CLK                            0    /*!< DMA.SIM0.CLK, LSIO.GPIO0.IO00 */
+#define SC_P_SIM0_RST                            1    /*!< DMA.SIM0.RST, LSIO.GPIO0.IO01 */
+#define SC_P_SIM0_IO                             2    /*!< DMA.SIM0.IO, LSIO.GPIO0.IO02 */
+#define SC_P_SIM0_PD                             3    /*!< DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */
+#define SC_P_SIM0_POWER_EN                       4    /*!< DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */
+#define SC_P_SIM0_GPIO0_00                       5    /*!< DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM           6    /*!<  */
+#define SC_P_M40_I2C0_SCL                        7    /*!< M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */
+#define SC_P_M40_I2C0_SDA                        8    /*!< M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */
+#define SC_P_M40_GPIO0_00                        9    /*!< M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */
+#define SC_P_M40_GPIO0_01                        10   /*!< M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */
+#define SC_P_M41_I2C0_SCL                        11   /*!< M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */
+#define SC_P_M41_I2C0_SDA                        12   /*!< M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */
+#define SC_P_M41_GPIO0_00                        13   /*!< M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */
+#define SC_P_M41_GPIO0_01                        14   /*!< M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */
+#define SC_P_GPT0_CLK                            15   /*!< LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */
+#define SC_P_GPT0_CAPTURE                        16   /*!< LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */
+#define SC_P_GPT0_COMPARE                        17   /*!< LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */
+#define SC_P_GPT1_CLK                            18   /*!< LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
+#define SC_P_GPT1_CAPTURE                        19   /*!< LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */
+#define SC_P_GPT1_COMPARE                        20   /*!< LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
+#define SC_P_UART0_RX                            21   /*!< DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */
+#define SC_P_UART0_TX                            22   /*!< DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */
+#define SC_P_UART0_RTS_B                         23   /*!< DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */
+#define SC_P_UART0_CTS_B                         24   /*!< DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */
+#define SC_P_UART1_TX                            25   /*!< DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */
+#define SC_P_UART1_RX                            26   /*!< DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */
+#define SC_P_UART1_RTS_B                         27   /*!< DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */
+#define SC_P_UART1_CTS_B                         28   /*!< DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH        29   /*!<  */
+#define SC_P_SCU_PMIC_MEMC_ON                    30   /*!< SCU.GPIO0.IOXX_PMIC_MEMC_ON */
+#define SC_P_SCU_WDOG_OUT                        31   /*!< SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SDA                        32   /*!< SCU.PMIC_I2C.SDA */
+#define SC_P_PMIC_I2C_SCL                        33   /*!< SCU.PMIC_I2C.SCL */
+#define SC_P_PMIC_EARLY_WARNING                  34   /*!< SCU.PMIC_EARLY_WARNING */
+#define SC_P_PMIC_INT_B                          35   /*!< SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00                        36   /*!< SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */
+#define SC_P_SCU_GPIO0_01                        37   /*!< SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */
+#define SC_P_SCU_GPIO0_02                        38   /*!< SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */
+#define SC_P_SCU_GPIO0_03                        39   /*!< SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */
+#define SC_P_SCU_GPIO0_04                        40   /*!< SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */
+#define SC_P_SCU_GPIO0_05                        41   /*!< SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */
+#define SC_P_SCU_GPIO0_06                        42   /*!< SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */
+#define SC_P_SCU_GPIO0_07                        43   /*!< SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */
+#define SC_P_SCU_BOOT_MODE0                      44   /*!< SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE1                      45   /*!< SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE2                      46   /*!< SCU.DSC.BOOT_MODE2 */
+#define SC_P_SCU_BOOT_MODE3                      47   /*!< SCU.DSC.BOOT_MODE3 */
+#define SC_P_SCU_BOOT_MODE4                      48   /*!< SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
+#define SC_P_SCU_BOOT_MODE5                      49   /*!< SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
+#define SC_P_LVDS0_GPIO00                        50   /*!< LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
+#define SC_P_LVDS0_GPIO01                        51   /*!< LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
+#define SC_P_LVDS0_I2C0_SCL                      52   /*!< LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
+#define SC_P_LVDS0_I2C0_SDA                      53   /*!< LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
+#define SC_P_LVDS0_I2C1_SCL                      54   /*!< LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
+#define SC_P_LVDS0_I2C1_SDA                      55   /*!< LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
+#define SC_P_LVDS1_GPIO00                        56   /*!< LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
+#define SC_P_LVDS1_GPIO01                        57   /*!< LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
+#define SC_P_LVDS1_I2C0_SCL                      58   /*!< LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
+#define SC_P_LVDS1_I2C0_SDA                      59   /*!< LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
+#define SC_P_LVDS1_I2C1_SCL                      60   /*!< LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
+#define SC_P_LVDS1_I2C1_SDA                      61   /*!< LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO      62   /*!<  */
+#define SC_P_MIPI_DSI0_I2C0_SCL                  63   /*!< MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
+#define SC_P_MIPI_DSI0_I2C0_SDA                  64   /*!< MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
+#define SC_P_MIPI_DSI0_GPIO0_00                  65   /*!< MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */
+#define SC_P_MIPI_DSI0_GPIO0_01                  66   /*!< MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
+#define SC_P_MIPI_DSI1_I2C0_SCL                  67   /*!< MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
+#define SC_P_MIPI_DSI1_I2C0_SDA                  68   /*!< MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
+#define SC_P_MIPI_DSI1_GPIO0_00                  69   /*!< MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */
+#define SC_P_MIPI_DSI1_GPIO0_01                  70   /*!< MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO   71   /*!<  */
+#define SC_P_MIPI_CSI0_MCLK_OUT                  72   /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
+#define SC_P_MIPI_CSI0_I2C0_SCL                  73   /*!< MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */
+#define SC_P_MIPI_CSI0_I2C0_SDA                  74   /*!< MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */
+#define SC_P_MIPI_CSI0_GPIO0_00                  75   /*!< MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_CSI0_GPIO0_01                  76   /*!< MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_CSI1_MCLK_OUT                  77   /*!< MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
+#define SC_P_MIPI_CSI1_GPIO0_00                  78   /*!< MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
+#define SC_P_MIPI_CSI1_GPIO0_01                  79   /*!< MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
+#define SC_P_MIPI_CSI1_I2C0_SCL                  80   /*!< MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
+#define SC_P_MIPI_CSI1_I2C0_SDA                  81   /*!< MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
+#define SC_P_HDMI_TX0_TS_SCL                     82   /*!< HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
+#define SC_P_HDMI_TX0_TS_SDA                     83   /*!< HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
+#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO          84   /*!<  */
+#define SC_P_ESAI1_FSR                           85   /*!< AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
+#define SC_P_ESAI1_FST                           86   /*!< AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */
+#define SC_P_ESAI1_SCKR                          87   /*!< AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
+#define SC_P_ESAI1_SCKT                          88   /*!< AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */
+#define SC_P_ESAI1_TX0                           89   /*!< AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */
+#define SC_P_ESAI1_TX1                           90   /*!< AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */
+#define SC_P_ESAI1_TX2_RX3                       91   /*!< AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */
+#define SC_P_ESAI1_TX3_RX2                       92   /*!< AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */
+#define SC_P_ESAI1_TX4_RX1                       93   /*!< AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */
+#define SC_P_ESAI1_TX5_RX0                       94   /*!< AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */
+#define SC_P_SPDIF0_RX                           95   /*!< AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */
+#define SC_P_SPDIF0_TX                           96   /*!< AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */
+#define SC_P_SPDIF0_EXT_CLK                      97   /*!< AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */
+#define SC_P_SPI3_SCK                            98   /*!< DMA.SPI3.SCK, LSIO.GPIO2.IO17 */
+#define SC_P_SPI3_SDO                            99   /*!< DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */
+#define SC_P_SPI3_SDI                            100  /*!< DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */
+#define SC_P_SPI3_CS0                            101  /*!< DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */
+#define SC_P_SPI3_CS1                            102  /*!< DMA.SPI3.CS1, LSIO.GPIO2.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB       103  /*!<  */
+#define SC_P_ESAI0_FSR                           104  /*!< AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */
+#define SC_P_ESAI0_FST                           105  /*!< AUD.ESAI0.FST, LSIO.GPIO2.IO23 */
+#define SC_P_ESAI0_SCKR                          106  /*!< AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */
+#define SC_P_ESAI0_SCKT                          107  /*!< AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */
+#define SC_P_ESAI0_TX0                           108  /*!< AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */
+#define SC_P_ESAI0_TX1                           109  /*!< AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */
+#define SC_P_ESAI0_TX2_RX3                       110  /*!< AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */
+#define SC_P_ESAI0_TX3_RX2                       111  /*!< AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */
+#define SC_P_ESAI0_TX4_RX1                       112  /*!< AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */
+#define SC_P_ESAI0_TX5_RX0                       113  /*!< AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */
+#define SC_P_MCLK_IN0                            114  /*!< AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */
+#define SC_P_MCLK_OUT0                           115  /*!< AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC       116  /*!<  */
+#define SC_P_SPI0_SCK                            117  /*!< DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */
+#define SC_P_SPI0_SDO                            118  /*!< DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */
+#define SC_P_SPI0_SDI                            119  /*!< DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */
+#define SC_P_SPI0_CS0                            120  /*!< DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */
+#define SC_P_SPI0_CS1                            121  /*!< DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */
+#define SC_P_SPI2_SCK                            122  /*!< DMA.SPI2.SCK, LSIO.GPIO3.IO07 */
+#define SC_P_SPI2_SDO                            123  /*!< DMA.SPI2.SDO, LSIO.GPIO3.IO08 */
+#define SC_P_SPI2_SDI                            124  /*!< DMA.SPI2.SDI, LSIO.GPIO3.IO09 */
+#define SC_P_SPI2_CS0                            125  /*!< DMA.SPI2.CS0, LSIO.GPIO3.IO10 */
+#define SC_P_SPI2_CS1                            126  /*!< DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */
+#define SC_P_SAI1_RXC                            127  /*!< AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */
+#define SC_P_SAI1_RXD                            128  /*!< AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */
+#define SC_P_SAI1_RXFS                           129  /*!< AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */
+#define SC_P_SAI1_TXC                            130  /*!< AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */
+#define SC_P_SAI1_TXD                            131  /*!< AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */
+#define SC_P_SAI1_TXFS                           132  /*!< AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT       133  /*!<  */
+#define SC_P_ADC_IN7                             134  /*!< DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */
+#define SC_P_ADC_IN6                             135  /*!< DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */
+#define SC_P_ADC_IN5                             136  /*!< DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */
+#define SC_P_ADC_IN4                             137  /*!< DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */
+#define SC_P_ADC_IN3                             138  /*!< DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */
+#define SC_P_ADC_IN2                             139  /*!< DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */
+#define SC_P_ADC_IN1                             140  /*!< DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */
+#define SC_P_ADC_IN0                             141  /*!< DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */
+#define SC_P_MLB_SIG                             142  /*!< CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */
+#define SC_P_MLB_CLK                             143  /*!< CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */
+#define SC_P_MLB_DATA                            144  /*!< CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT       145  /*!<  */
+#define SC_P_FLEXCAN0_RX                         146  /*!< DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */
+#define SC_P_FLEXCAN0_TX                         147  /*!< DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */
+#define SC_P_FLEXCAN1_RX                         148  /*!< DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */
+#define SC_P_FLEXCAN1_TX                         149  /*!< DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */
+#define SC_P_FLEXCAN2_RX                         150  /*!< DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */
+#define SC_P_FLEXCAN2_TX                         151  /*!< DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR       152  /*!<  */
+#define SC_P_USB_SS3_TC0                         153  /*!< DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */
+#define SC_P_USB_SS3_TC1                         154  /*!< DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
+#define SC_P_USB_SS3_TC2                         155  /*!< DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */
+#define SC_P_USB_SS3_TC3                         156  /*!< DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO            157  /*!<  */
+#define SC_P_USDHC1_RESET_B                      158  /*!< CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */
+#define SC_P_USDHC1_VSELECT                      159  /*!< CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */
+#define SC_P_USDHC2_RESET_B                      160  /*!< CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */
+#define SC_P_USDHC2_VSELECT                      161  /*!< CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */
+#define SC_P_USDHC2_WP                           162  /*!< CONN.USDHC2.WP, LSIO.GPIO4.IO11 */
+#define SC_P_USDHC2_CD_B                         163  /*!< CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP       164  /*!<  */
+#define SC_P_ENET0_MDIO                          165  /*!< CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */
+#define SC_P_ENET0_MDC                           166  /*!< CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */
+#define SC_P_ENET0_REFCLK_125M_25M               167  /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */
+#define SC_P_ENET1_REFCLK_125M_25M               168  /*!< CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */
+#define SC_P_ENET1_MDIO                          169  /*!< CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */
+#define SC_P_ENET1_MDC                           170  /*!< CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT        171  /*!<  */
+#define SC_P_QSPI1A_SS0_B                        172  /*!< LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */
+#define SC_P_QSPI1A_SS1_B                        173  /*!< LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */
+#define SC_P_QSPI1A_SCLK                         174  /*!< LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */
+#define SC_P_QSPI1A_DQS                          175  /*!< LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */
+#define SC_P_QSPI1A_DATA3                        176  /*!< LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */
+#define SC_P_QSPI1A_DATA2                        177  /*!< LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */
+#define SC_P_QSPI1A_DATA1                        178  /*!< LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */
+#define SC_P_QSPI1A_DATA0                        179  /*!< LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1         180  /*!<  */
+#define SC_P_QSPI0A_DATA0                        181  /*!< LSIO.QSPI0A.DATA0 */
+#define SC_P_QSPI0A_DATA1                        182  /*!< LSIO.QSPI0A.DATA1 */
+#define SC_P_QSPI0A_DATA2                        183  /*!< LSIO.QSPI0A.DATA2 */
+#define SC_P_QSPI0A_DATA3                        184  /*!< LSIO.QSPI0A.DATA3 */
+#define SC_P_QSPI0A_DQS                          185  /*!< LSIO.QSPI0A.DQS */
+#define SC_P_QSPI0A_SS0_B                        186  /*!< LSIO.QSPI0A.SS0_B */
+#define SC_P_QSPI0A_SS1_B                        187  /*!< LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */
+#define SC_P_QSPI0A_SCLK                         188  /*!< LSIO.QSPI0A.SCLK */
+#define SC_P_QSPI0B_SCLK                         189  /*!< LSIO.QSPI0B.SCLK */
+#define SC_P_QSPI0B_DATA0                        190  /*!< LSIO.QSPI0B.DATA0 */
+#define SC_P_QSPI0B_DATA1                        191  /*!< LSIO.QSPI0B.DATA1 */
+#define SC_P_QSPI0B_DATA2                        192  /*!< LSIO.QSPI0B.DATA2 */
+#define SC_P_QSPI0B_DATA3                        193  /*!< LSIO.QSPI0B.DATA3 */
+#define SC_P_QSPI0B_DQS                          194  /*!< LSIO.QSPI0B.DQS */
+#define SC_P_QSPI0B_SS0_B                        195  /*!< LSIO.QSPI0B.SS0_B */
+#define SC_P_QSPI0B_SS1_B                        196  /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0         197  /*!<  */
+#define SC_P_PCIE_CTRL0_CLKREQ_B                 198  /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */
+#define SC_P_PCIE_CTRL0_WAKE_B                   199  /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */
+#define SC_P_PCIE_CTRL0_PERST_B                  200  /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */
+#define SC_P_PCIE_CTRL1_CLKREQ_B                 201  /*!< HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */
+#define SC_P_PCIE_CTRL1_WAKE_B                   202  /*!< HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */
+#define SC_P_PCIE_CTRL1_PERST_B                  203  /*!< HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP       204  /*!<  */
+#define SC_P_USB_HSIC0_DATA                      205  /*!< CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */
+#define SC_P_USB_HSIC0_STROBE                    206  /*!< CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */
+#define SC_P_CALIBRATION_0_HSIC                  207  /*!<  */
+#define SC_P_CALIBRATION_1_HSIC                  208  /*!<  */
+#define SC_P_EMMC0_CLK                           209  /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B */
+#define SC_P_EMMC0_CMD                           210  /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */
+#define SC_P_EMMC0_DATA0                         211  /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */
+#define SC_P_EMMC0_DATA1                         212  /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */
+#define SC_P_EMMC0_DATA2                         213  /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */
+#define SC_P_EMMC0_DATA3                         214  /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */
+#define SC_P_EMMC0_DATA4                         215  /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */
+#define SC_P_EMMC0_DATA5                         216  /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */
+#define SC_P_EMMC0_DATA6                         217  /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */
+#define SC_P_EMMC0_DATA7                         218  /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */
+#define SC_P_EMMC0_STROBE                        219  /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */
+#define SC_P_EMMC0_RESET_B                       220  /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX        221  /*!<  */
+#define SC_P_USDHC1_CLK                          222  /*!< CONN.USDHC1.CLK, AUD.MQS.R */
+#define SC_P_USDHC1_CMD                          223  /*!< CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */
+#define SC_P_USDHC1_DATA0                        224  /*!< CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */
+#define SC_P_USDHC1_DATA1                        225  /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */
+#define SC_P_CTL_NAND_RE_P_N                     226  /*!<  */
+#define SC_P_USDHC1_DATA2                        227  /*!< CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
+#define SC_P_USDHC1_DATA3                        228  /*!< CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
+#define SC_P_CTL_NAND_DQS_P_N                    229  /*!<  */
+#define SC_P_USDHC1_DATA4                        230  /*!< CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */
+#define SC_P_USDHC1_DATA5                        231  /*!< CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */
+#define SC_P_USDHC1_DATA6                        232  /*!< CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
+#define SC_P_USDHC1_DATA7                        233  /*!< CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */
+#define SC_P_USDHC1_STROBE                       234  /*!< CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2         235  /*!<  */
+#define SC_P_USDHC2_CLK                          236  /*!< CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */
+#define SC_P_USDHC2_CMD                          237  /*!< CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */
+#define SC_P_USDHC2_DATA0                        238  /*!< CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */
+#define SC_P_USDHC2_DATA1                        239  /*!< CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */
+#define SC_P_USDHC2_DATA2                        240  /*!< CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */
+#define SC_P_USDHC2_DATA3                        241  /*!< CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3         242  /*!<  */
+#define SC_P_ENET0_RGMII_TXC                     243  /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */
+#define SC_P_ENET0_RGMII_TX_CTL                  244  /*!< CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */
+#define SC_P_ENET0_RGMII_TXD0                    245  /*!< CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */
+#define SC_P_ENET0_RGMII_TXD1                    246  /*!< CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */
+#define SC_P_ENET0_RGMII_TXD2                    247  /*!< CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */
+#define SC_P_ENET0_RGMII_TXD3                    248  /*!< CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */
+#define SC_P_ENET0_RGMII_RXC                     249  /*!< CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */
+#define SC_P_ENET0_RGMII_RX_CTL                  250  /*!< CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */
+#define SC_P_ENET0_RGMII_RXD0                    251  /*!< CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */
+#define SC_P_ENET0_RGMII_RXD1                    252  /*!< CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */
+#define SC_P_ENET0_RGMII_RXD2                    253  /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */
+#define SC_P_ENET0_RGMII_RXD3                    254  /*!< CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB    255  /*!<  */
+#define SC_P_ENET1_RGMII_TXC                     256  /*!< CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */
+#define SC_P_ENET1_RGMII_TX_CTL                  257  /*!< CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */
+#define SC_P_ENET1_RGMII_TXD0                    258  /*!< CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */
+#define SC_P_ENET1_RGMII_TXD1                    259  /*!< CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */
+#define SC_P_ENET1_RGMII_TXD2                    260  /*!< CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */
+#define SC_P_ENET1_RGMII_TXD3                    261  /*!< CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */
+#define SC_P_ENET1_RGMII_RXC                     262  /*!< CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */
+#define SC_P_ENET1_RGMII_RX_CTL                  263  /*!< CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */
+#define SC_P_ENET1_RGMII_RXD0                    264  /*!< CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
+#define SC_P_ENET1_RGMII_RXD1                    265  /*!< CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
+#define SC_P_ENET1_RGMII_RXD2                    266  /*!< CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
+#define SC_P_ENET1_RGMII_RXD3                    267  /*!< CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA    268  /*!<  */
+/*@}*/
+
+/*!
+ * @name Pad Mux Definitions
+ * format: name padid padmux
+ */
+/*@{*/
+#define SC_P_SIM0_CLK_DMA_SIM0_CLK                              SC_P_SIM0_CLK                      0
+#define SC_P_SIM0_CLK_LSIO_GPIO0_IO00                           SC_P_SIM0_CLK                      3
+#define SC_P_SIM0_RST_DMA_SIM0_RST                              SC_P_SIM0_RST                      0
+#define SC_P_SIM0_RST_LSIO_GPIO0_IO01                           SC_P_SIM0_RST                      3
+#define SC_P_SIM0_IO_DMA_SIM0_IO                                SC_P_SIM0_IO                       0
+#define SC_P_SIM0_IO_LSIO_GPIO0_IO02                            SC_P_SIM0_IO                       3
+#define SC_P_SIM0_PD_DMA_SIM0_PD                                SC_P_SIM0_PD                       0
+#define SC_P_SIM0_PD_DMA_I2C3_SCL                               SC_P_SIM0_PD                       1
+#define SC_P_SIM0_PD_LSIO_GPIO0_IO03                            SC_P_SIM0_PD                       3
+#define SC_P_SIM0_POWER_EN_DMA_SIM0_POWER_EN                    SC_P_SIM0_POWER_EN                 0
+#define SC_P_SIM0_POWER_EN_DMA_I2C3_SDA                         SC_P_SIM0_POWER_EN                 1
+#define SC_P_SIM0_POWER_EN_LSIO_GPIO0_IO04                      SC_P_SIM0_POWER_EN                 3
+#define SC_P_SIM0_GPIO0_00_DMA_SIM0_POWER_EN                    SC_P_SIM0_GPIO0_00                 0
+#define SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05                      SC_P_SIM0_GPIO0_00                 3
+#define SC_P_M40_I2C0_SCL_M40_I2C0_SCL                          SC_P_M40_I2C0_SCL                  0
+#define SC_P_M40_I2C0_SCL_M40_UART0_RX                          SC_P_M40_I2C0_SCL                  1
+#define SC_P_M40_I2C0_SCL_M40_GPIO0_IO02                        SC_P_M40_I2C0_SCL                  2
+#define SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06                       SC_P_M40_I2C0_SCL                  3
+#define SC_P_M40_I2C0_SDA_M40_I2C0_SDA                          SC_P_M40_I2C0_SDA                  0
+#define SC_P_M40_I2C0_SDA_M40_UART0_TX                          SC_P_M40_I2C0_SDA                  1
+#define SC_P_M40_I2C0_SDA_M40_GPIO0_IO03                        SC_P_M40_I2C0_SDA                  2
+#define SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07                       SC_P_M40_I2C0_SDA                  3
+#define SC_P_M40_GPIO0_00_M40_GPIO0_IO00                        SC_P_M40_GPIO0_00                  0
+#define SC_P_M40_GPIO0_00_M40_TPM0_CH0                          SC_P_M40_GPIO0_00                  1
+#define SC_P_M40_GPIO0_00_DMA_UART4_RX                          SC_P_M40_GPIO0_00                  2
+#define SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08                       SC_P_M40_GPIO0_00                  3
+#define SC_P_M40_GPIO0_01_M40_GPIO0_IO01                        SC_P_M40_GPIO0_01                  0
+#define SC_P_M40_GPIO0_01_M40_TPM0_CH1                          SC_P_M40_GPIO0_01                  1
+#define SC_P_M40_GPIO0_01_DMA_UART4_TX                          SC_P_M40_GPIO0_01                  2
+#define SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09                       SC_P_M40_GPIO0_01                  3
+#define SC_P_M41_I2C0_SCL_M41_I2C0_SCL                          SC_P_M41_I2C0_SCL                  0
+#define SC_P_M41_I2C0_SCL_M41_UART0_RX                          SC_P_M41_I2C0_SCL                  1
+#define SC_P_M41_I2C0_SCL_M41_GPIO0_IO02                        SC_P_M41_I2C0_SCL                  2
+#define SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10                       SC_P_M41_I2C0_SCL                  3
+#define SC_P_M41_I2C0_SDA_M41_I2C0_SDA                          SC_P_M41_I2C0_SDA                  0
+#define SC_P_M41_I2C0_SDA_M41_UART0_TX                          SC_P_M41_I2C0_SDA                  1
+#define SC_P_M41_I2C0_SDA_M41_GPIO0_IO03                        SC_P_M41_I2C0_SDA                  2
+#define SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11                       SC_P_M41_I2C0_SDA                  3
+#define SC_P_M41_GPIO0_00_M41_GPIO0_IO00                        SC_P_M41_GPIO0_00                  0
+#define SC_P_M41_GPIO0_00_M41_TPM0_CH0                          SC_P_M41_GPIO0_00                  1
+#define SC_P_M41_GPIO0_00_DMA_UART3_RX                          SC_P_M41_GPIO0_00                  2
+#define SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12                       SC_P_M41_GPIO0_00                  3
+#define SC_P_M41_GPIO0_01_M41_GPIO0_IO01                        SC_P_M41_GPIO0_01                  0
+#define SC_P_M41_GPIO0_01_M41_TPM0_CH1                          SC_P_M41_GPIO0_01                  1
+#define SC_P_M41_GPIO0_01_DMA_UART3_TX                          SC_P_M41_GPIO0_01                  2
+#define SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13                       SC_P_M41_GPIO0_01                  3
+#define SC_P_GPT0_CLK_LSIO_GPT0_CLK                             SC_P_GPT0_CLK                      0
+#define SC_P_GPT0_CLK_DMA_I2C1_SCL                              SC_P_GPT0_CLK                      1
+#define SC_P_GPT0_CLK_LSIO_KPP0_COL4                            SC_P_GPT0_CLK                      2
+#define SC_P_GPT0_CLK_LSIO_GPIO0_IO14                           SC_P_GPT0_CLK                      3
+#define SC_P_GPT0_CAPTURE_LSIO_GPT0_CAPTURE                     SC_P_GPT0_CAPTURE                  0
+#define SC_P_GPT0_CAPTURE_DMA_I2C1_SDA                          SC_P_GPT0_CAPTURE                  1
+#define SC_P_GPT0_CAPTURE_LSIO_KPP0_COL5                        SC_P_GPT0_CAPTURE                  2
+#define SC_P_GPT0_CAPTURE_LSIO_GPIO0_IO15                       SC_P_GPT0_CAPTURE                  3
+#define SC_P_GPT0_COMPARE_LSIO_GPT0_COMPARE                     SC_P_GPT0_COMPARE                  0
+#define SC_P_GPT0_COMPARE_LSIO_PWM3_OUT                         SC_P_GPT0_COMPARE                  1
+#define SC_P_GPT0_COMPARE_LSIO_KPP0_COL6                        SC_P_GPT0_COMPARE                  2
+#define SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16                       SC_P_GPT0_COMPARE                  3
+#define SC_P_GPT1_CLK_LSIO_GPT1_CLK                             SC_P_GPT1_CLK                      0
+#define SC_P_GPT1_CLK_DMA_I2C2_SCL                              SC_P_GPT1_CLK                      1
+#define SC_P_GPT1_CLK_LSIO_KPP0_COL7                            SC_P_GPT1_CLK                      2
+#define SC_P_GPT1_CLK_LSIO_GPIO0_IO17                           SC_P_GPT1_CLK                      3
+#define SC_P_GPT1_CAPTURE_LSIO_GPT1_CAPTURE                     SC_P_GPT1_CAPTURE                  0
+#define SC_P_GPT1_CAPTURE_DMA_I2C2_SDA                          SC_P_GPT1_CAPTURE                  1
+#define SC_P_GPT1_CAPTURE_LSIO_KPP0_ROW4                        SC_P_GPT1_CAPTURE                  2
+#define SC_P_GPT1_CAPTURE_LSIO_GPIO0_IO18                       SC_P_GPT1_CAPTURE                  3
+#define SC_P_GPT1_COMPARE_LSIO_GPT1_COMPARE                     SC_P_GPT1_COMPARE                  0
+#define SC_P_GPT1_COMPARE_LSIO_PWM2_OUT                         SC_P_GPT1_COMPARE                  1
+#define SC_P_GPT1_COMPARE_LSIO_KPP0_ROW5                        SC_P_GPT1_COMPARE                  2
+#define SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19                       SC_P_GPT1_COMPARE                  3
+#define SC_P_UART0_RX_DMA_UART0_RX                              SC_P_UART0_RX                      0
+#define SC_P_UART0_RX_SCU_UART0_RX                              SC_P_UART0_RX                      1
+#define SC_P_UART0_RX_LSIO_GPIO0_IO20                           SC_P_UART0_RX                      3
+#define SC_P_UART0_TX_DMA_UART0_TX                              SC_P_UART0_TX                      0
+#define SC_P_UART0_TX_SCU_UART0_TX                              SC_P_UART0_TX                      1
+#define SC_P_UART0_TX_LSIO_GPIO0_IO21                           SC_P_UART0_TX                      3
+#define SC_P_UART0_RTS_B_DMA_UART0_RTS_B                        SC_P_UART0_RTS_B                   0
+#define SC_P_UART0_RTS_B_LSIO_PWM0_OUT                          SC_P_UART0_RTS_B                   1
+#define SC_P_UART0_RTS_B_DMA_UART2_RX                           SC_P_UART0_RTS_B                   2
+#define SC_P_UART0_RTS_B_LSIO_GPIO0_IO22                        SC_P_UART0_RTS_B                   3
+#define SC_P_UART0_CTS_B_DMA_UART0_CTS_B                        SC_P_UART0_CTS_B                   0
+#define SC_P_UART0_CTS_B_LSIO_PWM1_OUT                          SC_P_UART0_CTS_B                   1
+#define SC_P_UART0_CTS_B_DMA_UART2_TX                           SC_P_UART0_CTS_B                   2
+#define SC_P_UART0_CTS_B_LSIO_GPIO0_IO23                        SC_P_UART0_CTS_B                   3
+#define SC_P_UART1_TX_DMA_UART1_TX                              SC_P_UART1_TX                      0
+#define SC_P_UART1_TX_DMA_SPI3_SCK                              SC_P_UART1_TX                      1
+#define SC_P_UART1_TX_LSIO_GPIO0_IO24                           SC_P_UART1_TX                      3
+#define SC_P_UART1_RX_DMA_UART1_RX                              SC_P_UART1_RX                      0
+#define SC_P_UART1_RX_DMA_SPI3_SDO                              SC_P_UART1_RX                      1
+#define SC_P_UART1_RX_LSIO_GPIO0_IO25                           SC_P_UART1_RX                      3
+#define SC_P_UART1_RTS_B_DMA_UART1_RTS_B                        SC_P_UART1_RTS_B                   0
+#define SC_P_UART1_RTS_B_DMA_SPI3_SDI                           SC_P_UART1_RTS_B                   1
+#define SC_P_UART1_RTS_B_DMA_UART1_CTS_B                        SC_P_UART1_RTS_B                   2
+#define SC_P_UART1_RTS_B_LSIO_GPIO0_IO26                        SC_P_UART1_RTS_B                   3
+#define SC_P_UART1_CTS_B_DMA_UART1_CTS_B                        SC_P_UART1_CTS_B                   0
+#define SC_P_UART1_CTS_B_DMA_SPI3_CS0                           SC_P_UART1_CTS_B                   1
+#define SC_P_UART1_CTS_B_DMA_UART1_RTS_B                        SC_P_UART1_CTS_B                   2
+#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO27                        SC_P_UART1_CTS_B                   3
+#define SC_P_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON       SC_P_SCU_PMIC_MEMC_ON              0
+#define SC_P_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT                    SC_P_SCU_WDOG_OUT                  0
+#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA                      SC_P_PMIC_I2C_SDA                  0
+#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL                      SC_P_PMIC_I2C_SCL                  0
+#define SC_P_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING          SC_P_PMIC_EARLY_WARNING            0
+#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B                      SC_P_PMIC_INT_B                    0
+#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00                        SC_P_SCU_GPIO0_00                  0
+#define SC_P_SCU_GPIO0_00_SCU_UART0_RX                          SC_P_SCU_GPIO0_00                  1
+#define SC_P_SCU_GPIO0_00_LSIO_GPIO0_IO28                       SC_P_SCU_GPIO0_00                  3
+#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01                        SC_P_SCU_GPIO0_01                  0
+#define SC_P_SCU_GPIO0_01_SCU_UART0_TX                          SC_P_SCU_GPIO0_01                  1
+#define SC_P_SCU_GPIO0_01_LSIO_GPIO0_IO29                       SC_P_SCU_GPIO0_01                  3
+#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IO02                        SC_P_SCU_GPIO0_02                  0
+#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON           SC_P_SCU_GPIO0_02                  1
+#define SC_P_SCU_GPIO0_02_LSIO_GPIO0_IO30                       SC_P_SCU_GPIO0_02                  3
+#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IO03                        SC_P_SCU_GPIO0_03                  0
+#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON           SC_P_SCU_GPIO0_03                  1
+#define SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31                       SC_P_SCU_GPIO0_03                  3
+#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IO04                        SC_P_SCU_GPIO0_04                  0
+#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON            SC_P_SCU_GPIO0_04                  1
+#define SC_P_SCU_GPIO0_04_LSIO_GPIO1_IO00                       SC_P_SCU_GPIO0_04                  3
+#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IO05                        SC_P_SCU_GPIO0_05                  0
+#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON            SC_P_SCU_GPIO0_05                  1
+#define SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01                       SC_P_SCU_GPIO0_05                  3
+#define SC_P_SCU_GPIO0_06_SCU_GPIO0_IO06                        SC_P_SCU_GPIO0_06                  0
+#define SC_P_SCU_GPIO0_06_SCU_TPM0_CH0                          SC_P_SCU_GPIO0_06                  1
+#define SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02                       SC_P_SCU_GPIO0_06                  3
+#define SC_P_SCU_GPIO0_07_SCU_GPIO0_IO07                        SC_P_SCU_GPIO0_07                  0
+#define SC_P_SCU_GPIO0_07_SCU_TPM0_CH1                          SC_P_SCU_GPIO0_07                  1
+#define SC_P_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K          SC_P_SCU_GPIO0_07                  2
+#define SC_P_SCU_GPIO0_07_LSIO_GPIO1_IO03                       SC_P_SCU_GPIO0_07                  3
+#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0                  SC_P_SCU_BOOT_MODE0                0
+#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1                  SC_P_SCU_BOOT_MODE1                0
+#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2                  SC_P_SCU_BOOT_MODE2                0
+#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3                  SC_P_SCU_BOOT_MODE3                0
+#define SC_P_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4                  SC_P_SCU_BOOT_MODE4                0
+#define SC_P_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL                    SC_P_SCU_BOOT_MODE4                1
+#define SC_P_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5                  SC_P_SCU_BOOT_MODE5                0
+#define SC_P_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA                    SC_P_SCU_BOOT_MODE5                1
+#define SC_P_LVDS0_GPIO00_LVDS0_GPIO0_IO00                      SC_P_LVDS0_GPIO00                  0
+#define SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT                        SC_P_LVDS0_GPIO00                  1
+#define SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04                       SC_P_LVDS0_GPIO00                  3
+#define SC_P_LVDS0_GPIO01_LVDS0_GPIO0_IO01                      SC_P_LVDS0_GPIO01                  0
+#define SC_P_LVDS0_GPIO01_LSIO_GPIO1_IO05                       SC_P_LVDS0_GPIO01                  3
+#define SC_P_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL                      SC_P_LVDS0_I2C0_SCL                0
+#define SC_P_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02                    SC_P_LVDS0_I2C0_SCL                1
+#define SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06                     SC_P_LVDS0_I2C0_SCL                3
+#define SC_P_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA                      SC_P_LVDS0_I2C0_SDA                0
+#define SC_P_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03                    SC_P_LVDS0_I2C0_SDA                1
+#define SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07                     SC_P_LVDS0_I2C0_SDA                3
+#define SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL                      SC_P_LVDS0_I2C1_SCL                0
+#define SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX                        SC_P_LVDS0_I2C1_SCL                1
+#define SC_P_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08                     SC_P_LVDS0_I2C1_SCL                3
+#define SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA                      SC_P_LVDS0_I2C1_SDA                0
+#define SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX                        SC_P_LVDS0_I2C1_SDA                1
+#define SC_P_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09                     SC_P_LVDS0_I2C1_SDA                3
+#define SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00                      SC_P_LVDS1_GPIO00                  0
+#define SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT                        SC_P_LVDS1_GPIO00                  1
+#define SC_P_LVDS1_GPIO00_LSIO_GPIO1_IO10                       SC_P_LVDS1_GPIO00                  3
+#define SC_P_LVDS1_GPIO01_LVDS1_GPIO0_IO01                      SC_P_LVDS1_GPIO01                  0
+#define SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11                       SC_P_LVDS1_GPIO01                  3
+#define SC_P_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL                      SC_P_LVDS1_I2C0_SCL                0
+#define SC_P_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02                    SC_P_LVDS1_I2C0_SCL                1
+#define SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12                     SC_P_LVDS1_I2C0_SCL                3
+#define SC_P_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA                      SC_P_LVDS1_I2C0_SDA                0
+#define SC_P_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03                    SC_P_LVDS1_I2C0_SDA                1
+#define SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13                     SC_P_LVDS1_I2C0_SDA                3
+#define SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL                      SC_P_LVDS1_I2C1_SCL                0
+#define SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX                        SC_P_LVDS1_I2C1_SCL                1
+#define SC_P_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14                     SC_P_LVDS1_I2C1_SCL                3
+#define SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA                      SC_P_LVDS1_I2C1_SDA                0
+#define SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX                        SC_P_LVDS1_I2C1_SDA                1
+#define SC_P_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15                     SC_P_LVDS1_I2C1_SDA                3
+#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL              SC_P_MIPI_DSI0_I2C0_SCL            0
+#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16                 SC_P_MIPI_DSI0_I2C0_SCL            3
+#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA              SC_P_MIPI_DSI0_I2C0_SDA            0
+#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17                 SC_P_MIPI_DSI0_I2C0_SDA            3
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00            SC_P_MIPI_DSI0_GPIO0_00            0
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT              SC_P_MIPI_DSI0_GPIO0_00            1
+#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18                 SC_P_MIPI_DSI0_GPIO0_00            3
+#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01            SC_P_MIPI_DSI0_GPIO0_01            0
+#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19                 SC_P_MIPI_DSI0_GPIO0_01            3
+#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL              SC_P_MIPI_DSI1_I2C0_SCL            0
+#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20                 SC_P_MIPI_DSI1_I2C0_SCL            3
+#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA              SC_P_MIPI_DSI1_I2C0_SDA            0
+#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21                 SC_P_MIPI_DSI1_I2C0_SDA            3
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00            SC_P_MIPI_DSI1_GPIO0_00            0
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT              SC_P_MIPI_DSI1_GPIO0_00            1
+#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22                 SC_P_MIPI_DSI1_GPIO0_00            3
+#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01            SC_P_MIPI_DSI1_GPIO0_01            0
+#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23                 SC_P_MIPI_DSI1_GPIO0_01            3
+#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT          SC_P_MIPI_CSI0_MCLK_OUT            0
+#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24                 SC_P_MIPI_CSI0_MCLK_OUT            3
+#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL              SC_P_MIPI_CSI0_I2C0_SCL            0
+#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25                 SC_P_MIPI_CSI0_I2C0_SCL            3
+#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA              SC_P_MIPI_CSI0_I2C0_SDA            0
+#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26                 SC_P_MIPI_CSI0_I2C0_SDA            3
+#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00            SC_P_MIPI_CSI0_GPIO0_00            0
+#define SC_P_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL                    SC_P_MIPI_CSI0_GPIO0_00            1
+#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL              SC_P_MIPI_CSI0_GPIO0_00            2
+#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27                 SC_P_MIPI_CSI0_GPIO0_00            3
+#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01            SC_P_MIPI_CSI0_GPIO0_01            0
+#define SC_P_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA                    SC_P_MIPI_CSI0_GPIO0_01            1
+#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA              SC_P_MIPI_CSI0_GPIO0_01            2
+#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28                 SC_P_MIPI_CSI0_GPIO0_01            3
+#define SC_P_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT          SC_P_MIPI_CSI1_MCLK_OUT            0
+#define SC_P_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29                 SC_P_MIPI_CSI1_MCLK_OUT            3
+#define SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00            SC_P_MIPI_CSI1_GPIO0_00            0
+#define SC_P_MIPI_CSI1_GPIO0_00_DMA_UART4_RX                    SC_P_MIPI_CSI1_GPIO0_00            1
+#define SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30                 SC_P_MIPI_CSI1_GPIO0_00            3
+#define SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01            SC_P_MIPI_CSI1_GPIO0_01            0
+#define SC_P_MIPI_CSI1_GPIO0_01_DMA_UART4_TX                    SC_P_MIPI_CSI1_GPIO0_01            1
+#define SC_P_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31                 SC_P_MIPI_CSI1_GPIO0_01            3
+#define SC_P_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL              SC_P_MIPI_CSI1_I2C0_SCL            0
+#define SC_P_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00                 SC_P_MIPI_CSI1_I2C0_SCL            3
+#define SC_P_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA              SC_P_MIPI_CSI1_I2C0_SDA            0
+#define SC_P_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01                 SC_P_MIPI_CSI1_I2C0_SDA            3
+#define SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL                  SC_P_HDMI_TX0_TS_SCL               0
+#define SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL                       SC_P_HDMI_TX0_TS_SCL               1
+#define SC_P_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02                    SC_P_HDMI_TX0_TS_SCL               3
+#define SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA                  SC_P_HDMI_TX0_TS_SDA               0
+#define SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA                       SC_P_HDMI_TX0_TS_SDA               1
+#define SC_P_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03                    SC_P_HDMI_TX0_TS_SDA               3
+#define SC_P_ESAI1_FSR_AUD_ESAI1_FSR                            SC_P_ESAI1_FSR                     0
+#define SC_P_ESAI1_FSR_LSIO_GPIO2_IO04                          SC_P_ESAI1_FSR                     3
+#define SC_P_ESAI1_FST_AUD_ESAI1_FST                            SC_P_ESAI1_FST                     0
+#define SC_P_ESAI1_FST_AUD_SPDIF0_EXT_CLK                       SC_P_ESAI1_FST                     1
+#define SC_P_ESAI1_FST_LSIO_GPIO2_IO05                          SC_P_ESAI1_FST                     3
+#define SC_P_ESAI1_SCKR_AUD_ESAI1_SCKR                          SC_P_ESAI1_SCKR                    0
+#define SC_P_ESAI1_SCKR_LSIO_GPIO2_IO06                         SC_P_ESAI1_SCKR                    3
+#define SC_P_ESAI1_SCKT_AUD_ESAI1_SCKT                          SC_P_ESAI1_SCKT                    0
+#define SC_P_ESAI1_SCKT_AUD_SAI2_RXC                            SC_P_ESAI1_SCKT                    1
+#define SC_P_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK                      SC_P_ESAI1_SCKT                    2
+#define SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07                         SC_P_ESAI1_SCKT                    3
+#define SC_P_ESAI1_TX0_AUD_ESAI1_TX0                            SC_P_ESAI1_TX0                     0
+#define SC_P_ESAI1_TX0_AUD_SAI2_RXD                             SC_P_ESAI1_TX0                     1
+#define SC_P_ESAI1_TX0_AUD_SPDIF0_RX                            SC_P_ESAI1_TX0                     2
+#define SC_P_ESAI1_TX0_LSIO_GPIO2_IO08                          SC_P_ESAI1_TX0                     3
+#define SC_P_ESAI1_TX1_AUD_ESAI1_TX1                            SC_P_ESAI1_TX1                     0
+#define SC_P_ESAI1_TX1_AUD_SAI2_RXFS                            SC_P_ESAI1_TX1                     1
+#define SC_P_ESAI1_TX1_AUD_SPDIF0_TX                            SC_P_ESAI1_TX1                     2
+#define SC_P_ESAI1_TX1_LSIO_GPIO2_IO09                          SC_P_ESAI1_TX1                     3
+#define SC_P_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3                    SC_P_ESAI1_TX2_RX3                 0
+#define SC_P_ESAI1_TX2_RX3_AUD_SPDIF0_RX                        SC_P_ESAI1_TX2_RX3                 1
+#define SC_P_ESAI1_TX2_RX3_LSIO_GPIO2_IO10                      SC_P_ESAI1_TX2_RX3                 3
+#define SC_P_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2                    SC_P_ESAI1_TX3_RX2                 0
+#define SC_P_ESAI1_TX3_RX2_AUD_SPDIF0_TX                        SC_P_ESAI1_TX3_RX2                 1
+#define SC_P_ESAI1_TX3_RX2_LSIO_GPIO2_IO11                      SC_P_ESAI1_TX3_RX2                 3
+#define SC_P_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1                    SC_P_ESAI1_TX4_RX1                 0
+#define SC_P_ESAI1_TX4_RX1_LSIO_GPIO2_IO12                      SC_P_ESAI1_TX4_RX1                 3
+#define SC_P_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0                    SC_P_ESAI1_TX5_RX0                 0
+#define SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13                      SC_P_ESAI1_TX5_RX0                 3
+#define SC_P_SPDIF0_RX_AUD_SPDIF0_RX                            SC_P_SPDIF0_RX                     0
+#define SC_P_SPDIF0_RX_AUD_MQS_R                                SC_P_SPDIF0_RX                     1
+#define SC_P_SPDIF0_RX_AUD_ACM_MCLK_IN1                         SC_P_SPDIF0_RX                     2
+#define SC_P_SPDIF0_RX_LSIO_GPIO2_IO14                          SC_P_SPDIF0_RX                     3
+#define SC_P_SPDIF0_TX_AUD_SPDIF0_TX                            SC_P_SPDIF0_TX                     0
+#define SC_P_SPDIF0_TX_AUD_MQS_L                                SC_P_SPDIF0_TX                     1
+#define SC_P_SPDIF0_TX_AUD_ACM_MCLK_OUT1                        SC_P_SPDIF0_TX                     2
+#define SC_P_SPDIF0_TX_LSIO_GPIO2_IO15                          SC_P_SPDIF0_TX                     3
+#define SC_P_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK                  SC_P_SPDIF0_EXT_CLK                0
+#define SC_P_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0                    SC_P_SPDIF0_EXT_CLK                1
+#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16                     SC_P_SPDIF0_EXT_CLK                3
+#define SC_P_SPI3_SCK_DMA_SPI3_SCK                              SC_P_SPI3_SCK                      0
+#define SC_P_SPI3_SCK_LSIO_GPIO2_IO17                           SC_P_SPI3_SCK                      3
+#define SC_P_SPI3_SDO_DMA_SPI3_SDO                              SC_P_SPI3_SDO                      0
+#define SC_P_SPI3_SDO_DMA_FTM_CH0                               SC_P_SPI3_SDO                      1
+#define SC_P_SPI3_SDO_LSIO_GPIO2_IO18                           SC_P_SPI3_SDO                      3
+#define SC_P_SPI3_SDI_DMA_SPI3_SDI                              SC_P_SPI3_SDI                      0
+#define SC_P_SPI3_SDI_DMA_FTM_CH1                               SC_P_SPI3_SDI                      1
+#define SC_P_SPI3_SDI_LSIO_GPIO2_IO19                           SC_P_SPI3_SDI                      3
+#define SC_P_SPI3_CS0_DMA_SPI3_CS0                              SC_P_SPI3_CS0                      0
+#define SC_P_SPI3_CS0_DMA_FTM_CH2                               SC_P_SPI3_CS0                      1
+#define SC_P_SPI3_CS0_LSIO_GPIO2_IO20                           SC_P_SPI3_CS0                      3
+#define SC_P_SPI3_CS1_DMA_SPI3_CS1                              SC_P_SPI3_CS1                      0
+#define SC_P_SPI3_CS1_LSIO_GPIO2_IO21                           SC_P_SPI3_CS1                      3
+#define SC_P_ESAI0_FSR_AUD_ESAI0_FSR                            SC_P_ESAI0_FSR                     0
+#define SC_P_ESAI0_FSR_LSIO_GPIO2_IO22                          SC_P_ESAI0_FSR                     3
+#define SC_P_ESAI0_FST_AUD_ESAI0_FST                            SC_P_ESAI0_FST                     0
+#define SC_P_ESAI0_FST_LSIO_GPIO2_IO23                          SC_P_ESAI0_FST                     3
+#define SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR                          SC_P_ESAI0_SCKR                    0
+#define SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24                         SC_P_ESAI0_SCKR                    3
+#define SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT                          SC_P_ESAI0_SCKT                    0
+#define SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25                         SC_P_ESAI0_SCKT                    3
+#define SC_P_ESAI0_TX0_AUD_ESAI0_TX0                            SC_P_ESAI0_TX0                     0
+#define SC_P_ESAI0_TX0_LSIO_GPIO2_IO26                          SC_P_ESAI0_TX0                     3
+#define SC_P_ESAI0_TX1_AUD_ESAI0_TX1                            SC_P_ESAI0_TX1                     0
+#define SC_P_ESAI0_TX1_LSIO_GPIO2_IO27                          SC_P_ESAI0_TX1                     3
+#define SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3                    SC_P_ESAI0_TX2_RX3                 0
+#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28                      SC_P_ESAI0_TX2_RX3                 3
+#define SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2                    SC_P_ESAI0_TX3_RX2                 0
+#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29                      SC_P_ESAI0_TX3_RX2                 3
+#define SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1                    SC_P_ESAI0_TX4_RX1                 0
+#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30                      SC_P_ESAI0_TX4_RX1                 3
+#define SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0                    SC_P_ESAI0_TX5_RX0                 0
+#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31                      SC_P_ESAI0_TX5_RX0                 3
+#define SC_P_MCLK_IN0_AUD_ACM_MCLK_IN0                          SC_P_MCLK_IN0                      0
+#define SC_P_MCLK_IN0_AUD_ESAI0_RX_HF_CLK                       SC_P_MCLK_IN0                      1
+#define SC_P_MCLK_IN0_AUD_ESAI1_RX_HF_CLK                       SC_P_MCLK_IN0                      2
+#define SC_P_MCLK_IN0_LSIO_GPIO3_IO00                           SC_P_MCLK_IN0                      3
+#define SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0                        SC_P_MCLK_OUT0                     0
+#define SC_P_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK                      SC_P_MCLK_OUT0                     1
+#define SC_P_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK                      SC_P_MCLK_OUT0                     2
+#define SC_P_MCLK_OUT0_LSIO_GPIO3_IO01                          SC_P_MCLK_OUT0                     3
+#define SC_P_SPI0_SCK_DMA_SPI0_SCK                              SC_P_SPI0_SCK                      0
+#define SC_P_SPI0_SCK_AUD_SAI0_RXC                              SC_P_SPI0_SCK                      1
+#define SC_P_SPI0_SCK_LSIO_GPIO3_IO02                           SC_P_SPI0_SCK                      3
+#define SC_P_SPI0_SDO_DMA_SPI0_SDO                              SC_P_SPI0_SDO                      0
+#define SC_P_SPI0_SDO_AUD_SAI0_TXD                              SC_P_SPI0_SDO                      1
+#define SC_P_SPI0_SDO_LSIO_GPIO3_IO03                           SC_P_SPI0_SDO                      3
+#define SC_P_SPI0_SDI_DMA_SPI0_SDI                              SC_P_SPI0_SDI                      0
+#define SC_P_SPI0_SDI_AUD_SAI0_RXD                              SC_P_SPI0_SDI                      1
+#define SC_P_SPI0_SDI_LSIO_GPIO3_IO04                           SC_P_SPI0_SDI                      3
+#define SC_P_SPI0_CS0_DMA_SPI0_CS0                              SC_P_SPI0_CS0                      0
+#define SC_P_SPI0_CS0_AUD_SAI0_RXFS                             SC_P_SPI0_CS0                      1
+#define SC_P_SPI0_CS0_LSIO_GPIO3_IO05                           SC_P_SPI0_CS0                      3
+#define SC_P_SPI0_CS1_DMA_SPI0_CS1                              SC_P_SPI0_CS1                      0
+#define SC_P_SPI0_CS1_AUD_SAI0_TXC                              SC_P_SPI0_CS1                      1
+#define SC_P_SPI0_CS1_LSIO_GPIO3_IO06                           SC_P_SPI0_CS1                      3
+#define SC_P_SPI2_SCK_DMA_SPI2_SCK                              SC_P_SPI2_SCK                      0
+#define SC_P_SPI2_SCK_LSIO_GPIO3_IO07                           SC_P_SPI2_SCK                      3
+#define SC_P_SPI2_SDO_DMA_SPI2_SDO                              SC_P_SPI2_SDO                      0
+#define SC_P_SPI2_SDO_LSIO_GPIO3_IO08                           SC_P_SPI2_SDO                      3
+#define SC_P_SPI2_SDI_DMA_SPI2_SDI                              SC_P_SPI2_SDI                      0
+#define SC_P_SPI2_SDI_LSIO_GPIO3_IO09                           SC_P_SPI2_SDI                      3
+#define SC_P_SPI2_CS0_DMA_SPI2_CS0                              SC_P_SPI2_CS0                      0
+#define SC_P_SPI2_CS0_LSIO_GPIO3_IO10                           SC_P_SPI2_CS0                      3
+#define SC_P_SPI2_CS1_DMA_SPI2_CS1                              SC_P_SPI2_CS1                      0
+#define SC_P_SPI2_CS1_AUD_SAI0_TXFS                             SC_P_SPI2_CS1                      1
+#define SC_P_SPI2_CS1_LSIO_GPIO3_IO11                           SC_P_SPI2_CS1                      3
+#define SC_P_SAI1_RXC_AUD_SAI1_RXC                              SC_P_SAI1_RXC                      0
+#define SC_P_SAI1_RXC_AUD_SAI0_TXD                              SC_P_SAI1_RXC                      1
+#define SC_P_SAI1_RXC_LSIO_GPIO3_IO12                           SC_P_SAI1_RXC                      3
+#define SC_P_SAI1_RXD_AUD_SAI1_RXD                              SC_P_SAI1_RXD                      0
+#define SC_P_SAI1_RXD_AUD_SAI0_TXFS                             SC_P_SAI1_RXD                      1
+#define SC_P_SAI1_RXD_LSIO_GPIO3_IO13                           SC_P_SAI1_RXD                      3
+#define SC_P_SAI1_RXFS_AUD_SAI1_RXFS                            SC_P_SAI1_RXFS                     0
+#define SC_P_SAI1_RXFS_AUD_SAI0_RXD                             SC_P_SAI1_RXFS                     1
+#define SC_P_SAI1_RXFS_LSIO_GPIO3_IO14                          SC_P_SAI1_RXFS                     3
+#define SC_P_SAI1_TXC_AUD_SAI1_TXC                              SC_P_SAI1_TXC                      0
+#define SC_P_SAI1_TXC_AUD_SAI0_TXC                              SC_P_SAI1_TXC                      1
+#define SC_P_SAI1_TXC_LSIO_GPIO3_IO15                           SC_P_SAI1_TXC                      3
+#define SC_P_SAI1_TXD_AUD_SAI1_TXD                              SC_P_SAI1_TXD                      0
+#define SC_P_SAI1_TXD_AUD_SAI1_RXC                              SC_P_SAI1_TXD                      1
+#define SC_P_SAI1_TXD_LSIO_GPIO3_IO16                           SC_P_SAI1_TXD                      3
+#define SC_P_SAI1_TXFS_AUD_SAI1_TXFS                            SC_P_SAI1_TXFS                     0
+#define SC_P_SAI1_TXFS_AUD_SAI1_RXFS                            SC_P_SAI1_TXFS                     1
+#define SC_P_SAI1_TXFS_LSIO_GPIO3_IO17                          SC_P_SAI1_TXFS                     3
+#define SC_P_ADC_IN7_DMA_ADC1_IN3                               SC_P_ADC_IN7                       0
+#define SC_P_ADC_IN7_DMA_SPI1_CS1                               SC_P_ADC_IN7                       1
+#define SC_P_ADC_IN7_LSIO_KPP0_ROW3                             SC_P_ADC_IN7                       2
+#define SC_P_ADC_IN7_LSIO_GPIO3_IO25                            SC_P_ADC_IN7                       3
+#define SC_P_ADC_IN6_DMA_ADC1_IN2                               SC_P_ADC_IN6                       0
+#define SC_P_ADC_IN6_DMA_SPI1_CS0                               SC_P_ADC_IN6                       1
+#define SC_P_ADC_IN6_LSIO_KPP0_ROW2                             SC_P_ADC_IN6                       2
+#define SC_P_ADC_IN6_LSIO_GPIO3_IO24                            SC_P_ADC_IN6                       3
+#define SC_P_ADC_IN5_DMA_ADC1_IN1                               SC_P_ADC_IN5                       0
+#define SC_P_ADC_IN5_DMA_SPI1_SDI                               SC_P_ADC_IN5                       1
+#define SC_P_ADC_IN5_LSIO_KPP0_ROW1                             SC_P_ADC_IN5                       2
+#define SC_P_ADC_IN5_LSIO_GPIO3_IO23                            SC_P_ADC_IN5                       3
+#define SC_P_ADC_IN4_DMA_ADC1_IN0                               SC_P_ADC_IN4                       0
+#define SC_P_ADC_IN4_DMA_SPI1_SDO                               SC_P_ADC_IN4                       1
+#define SC_P_ADC_IN4_LSIO_KPP0_ROW0                             SC_P_ADC_IN4                       2
+#define SC_P_ADC_IN4_LSIO_GPIO3_IO22                            SC_P_ADC_IN4                       3
+#define SC_P_ADC_IN3_DMA_ADC0_IN3                               SC_P_ADC_IN3                       0
+#define SC_P_ADC_IN3_DMA_SPI1_SCK                               SC_P_ADC_IN3                       1
+#define SC_P_ADC_IN3_LSIO_KPP0_COL3                             SC_P_ADC_IN3                       2
+#define SC_P_ADC_IN3_LSIO_GPIO3_IO21                            SC_P_ADC_IN3                       3
+#define SC_P_ADC_IN2_DMA_ADC0_IN2                               SC_P_ADC_IN2                       0
+#define SC_P_ADC_IN2_LSIO_KPP0_COL2                             SC_P_ADC_IN2                       2
+#define SC_P_ADC_IN2_LSIO_GPIO3_IO20                            SC_P_ADC_IN2                       3
+#define SC_P_ADC_IN1_DMA_ADC0_IN1                               SC_P_ADC_IN1                       0
+#define SC_P_ADC_IN1_LSIO_KPP0_COL1                             SC_P_ADC_IN1                       2
+#define SC_P_ADC_IN1_LSIO_GPIO3_IO19                            SC_P_ADC_IN1                       3
+#define SC_P_ADC_IN0_DMA_ADC0_IN0                               SC_P_ADC_IN0                       0
+#define SC_P_ADC_IN0_LSIO_KPP0_COL0                             SC_P_ADC_IN0                       2
+#define SC_P_ADC_IN0_LSIO_GPIO3_IO18                            SC_P_ADC_IN0                       3
+#define SC_P_MLB_SIG_CONN_MLB_SIG                               SC_P_MLB_SIG                       0
+#define SC_P_MLB_SIG_AUD_SAI3_RXC                               SC_P_MLB_SIG                       1
+#define SC_P_MLB_SIG_LSIO_GPIO3_IO26                            SC_P_MLB_SIG                       3
+#define SC_P_MLB_CLK_CONN_MLB_CLK                               SC_P_MLB_CLK                       0
+#define SC_P_MLB_CLK_AUD_SAI3_RXFS                              SC_P_MLB_CLK                       1
+#define SC_P_MLB_CLK_LSIO_GPIO3_IO27                            SC_P_MLB_CLK                       3
+#define SC_P_MLB_DATA_CONN_MLB_DATA                             SC_P_MLB_DATA                      0
+#define SC_P_MLB_DATA_AUD_SAI3_RXD                              SC_P_MLB_DATA                      1
+#define SC_P_MLB_DATA_LSIO_GPIO3_IO28                           SC_P_MLB_DATA                      3
+#define SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX                        SC_P_FLEXCAN0_RX                   0
+#define SC_P_FLEXCAN0_RX_LSIO_GPIO3_IO29                        SC_P_FLEXCAN0_RX                   3
+#define SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX                        SC_P_FLEXCAN0_TX                   0
+#define SC_P_FLEXCAN0_TX_LSIO_GPIO3_IO30                        SC_P_FLEXCAN0_TX                   3
+#define SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX                        SC_P_FLEXCAN1_RX                   0
+#define SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31                        SC_P_FLEXCAN1_RX                   3
+#define SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX                        SC_P_FLEXCAN1_TX                   0
+#define SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00                        SC_P_FLEXCAN1_TX                   3
+#define SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX                        SC_P_FLEXCAN2_RX                   0
+#define SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01                        SC_P_FLEXCAN2_RX                   3
+#define SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX                        SC_P_FLEXCAN2_TX                   0
+#define SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02                        SC_P_FLEXCAN2_TX                   3
+#define SC_P_USB_SS3_TC0_DMA_I2C1_SCL                           SC_P_USB_SS3_TC0                   0
+#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR                      SC_P_USB_SS3_TC0                   1
+#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03                        SC_P_USB_SS3_TC0                   3
+#define SC_P_USB_SS3_TC1_DMA_I2C1_SCL                           SC_P_USB_SS3_TC1                   0
+#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR                      SC_P_USB_SS3_TC1                   1
+#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04                        SC_P_USB_SS3_TC1                   3
+#define SC_P_USB_SS3_TC2_DMA_I2C1_SDA                           SC_P_USB_SS3_TC2                   0
+#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC                       SC_P_USB_SS3_TC2                   1
+#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05                        SC_P_USB_SS3_TC2                   3
+#define SC_P_USB_SS3_TC3_DMA_I2C1_SDA                           SC_P_USB_SS3_TC3                   0
+#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC                       SC_P_USB_SS3_TC3                   1
+#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06                        SC_P_USB_SS3_TC3                   3
+#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B                 SC_P_USDHC1_RESET_B                0
+#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07                     SC_P_USDHC1_RESET_B                3
+#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT                 SC_P_USDHC1_VSELECT                0
+#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08                     SC_P_USDHC1_VSELECT                3
+#define SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B                 SC_P_USDHC2_RESET_B                0
+#define SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09                     SC_P_USDHC2_RESET_B                3
+#define SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT                 SC_P_USDHC2_VSELECT                0
+#define SC_P_USDHC2_VSELECT_LSIO_GPIO4_IO10                     SC_P_USDHC2_VSELECT                3
+#define SC_P_USDHC2_WP_CONN_USDHC2_WP                           SC_P_USDHC2_WP                     0
+#define SC_P_USDHC2_WP_LSIO_GPIO4_IO11                          SC_P_USDHC2_WP                     3
+#define SC_P_USDHC2_CD_B_CONN_USDHC2_CD_B                       SC_P_USDHC2_CD_B                   0
+#define SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12                        SC_P_USDHC2_CD_B                   3
+#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO                         SC_P_ENET0_MDIO                    0
+#define SC_P_ENET0_MDIO_DMA_I2C4_SDA                            SC_P_ENET0_MDIO                    1
+#define SC_P_ENET0_MDIO_LSIO_GPIO4_IO13                         SC_P_ENET0_MDIO                    3
+#define SC_P_ENET0_MDC_CONN_ENET0_MDC                           SC_P_ENET0_MDC                     0
+#define SC_P_ENET0_MDC_DMA_I2C4_SCL                             SC_P_ENET0_MDC                     1
+#define SC_P_ENET0_MDC_LSIO_GPIO4_IO14                          SC_P_ENET0_MDC                     3
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M   SC_P_ENET0_REFCLK_125M_25M         0
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS               SC_P_ENET0_REFCLK_125M_25M         1
+#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15              SC_P_ENET0_REFCLK_125M_25M         3
+#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M   SC_P_ENET1_REFCLK_125M_25M         0
+#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS               SC_P_ENET1_REFCLK_125M_25M         1
+#define SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16              SC_P_ENET1_REFCLK_125M_25M         3
+#define SC_P_ENET1_MDIO_CONN_ENET1_MDIO                         SC_P_ENET1_MDIO                    0
+#define SC_P_ENET1_MDIO_DMA_I2C4_SDA                            SC_P_ENET1_MDIO                    1
+#define SC_P_ENET1_MDIO_LSIO_GPIO4_IO17                         SC_P_ENET1_MDIO                    3
+#define SC_P_ENET1_MDC_CONN_ENET1_MDC                           SC_P_ENET1_MDC                     0
+#define SC_P_ENET1_MDC_DMA_I2C4_SCL                             SC_P_ENET1_MDC                     1
+#define SC_P_ENET1_MDC_LSIO_GPIO4_IO18                          SC_P_ENET1_MDC                     3
+#define SC_P_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B                     SC_P_QSPI1A_SS0_B                  0
+#define SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19                       SC_P_QSPI1A_SS0_B                  3
+#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B                     SC_P_QSPI1A_SS1_B                  0
+#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2                     SC_P_QSPI1A_SS1_B                  1
+#define SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20                       SC_P_QSPI1A_SS1_B                  3
+#define SC_P_QSPI1A_SCLK_LSIO_QSPI1A_SCLK                       SC_P_QSPI1A_SCLK                   0
+#define SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21                        SC_P_QSPI1A_SCLK                   3
+#define SC_P_QSPI1A_DQS_LSIO_QSPI1A_DQS                         SC_P_QSPI1A_DQS                    0
+#define SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22                         SC_P_QSPI1A_DQS                    3
+#define SC_P_QSPI1A_DATA3_LSIO_QSPI1A_DATA3                     SC_P_QSPI1A_DATA3                  0
+#define SC_P_QSPI1A_DATA3_DMA_I2C1_SDA                          SC_P_QSPI1A_DATA3                  1
+#define SC_P_QSPI1A_DATA3_CONN_USB_OTG1_OC                      SC_P_QSPI1A_DATA3                  2
+#define SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23                       SC_P_QSPI1A_DATA3                  3
+#define SC_P_QSPI1A_DATA2_LSIO_QSPI1A_DATA2                     SC_P_QSPI1A_DATA2                  0
+#define SC_P_QSPI1A_DATA2_DMA_I2C1_SCL                          SC_P_QSPI1A_DATA2                  1
+#define SC_P_QSPI1A_DATA2_CONN_USB_OTG2_PWR                     SC_P_QSPI1A_DATA2                  2
+#define SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24                       SC_P_QSPI1A_DATA2                  3
+#define SC_P_QSPI1A_DATA1_LSIO_QSPI1A_DATA1                     SC_P_QSPI1A_DATA1                  0
+#define SC_P_QSPI1A_DATA1_DMA_I2C1_SDA                          SC_P_QSPI1A_DATA1                  1
+#define SC_P_QSPI1A_DATA1_CONN_USB_OTG2_OC                      SC_P_QSPI1A_DATA1                  2
+#define SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25                       SC_P_QSPI1A_DATA1                  3
+#define SC_P_QSPI1A_DATA0_LSIO_QSPI1A_DATA0                     SC_P_QSPI1A_DATA0                  0
+#define SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26                       SC_P_QSPI1A_DATA0                  3
+#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0                     SC_P_QSPI0A_DATA0                  0
+#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1                     SC_P_QSPI0A_DATA1                  0
+#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2                     SC_P_QSPI0A_DATA2                  0
+#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3                     SC_P_QSPI0A_DATA3                  0
+#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS                         SC_P_QSPI0A_DQS                    0
+#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B                     SC_P_QSPI0A_SS0_B                  0
+#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B                     SC_P_QSPI0A_SS1_B                  0
+#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2                     SC_P_QSPI0A_SS1_B                  1
+#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK                       SC_P_QSPI0A_SCLK                   0
+#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK                       SC_P_QSPI0B_SCLK                   0
+#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0                     SC_P_QSPI0B_DATA0                  0
+#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1                     SC_P_QSPI0B_DATA1                  0
+#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2                     SC_P_QSPI0B_DATA2                  0
+#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3                     SC_P_QSPI0B_DATA3                  0
+#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS                         SC_P_QSPI0B_DQS                    0
+#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B                     SC_P_QSPI0B_SS0_B                  0
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B                     SC_P_QSPI0B_SS1_B                  0
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2                     SC_P_QSPI0B_SS1_B                  1
+#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B            SC_P_PCIE_CTRL0_CLKREQ_B           0
+#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27                SC_P_PCIE_CTRL0_CLKREQ_B           3
+#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B                SC_P_PCIE_CTRL0_WAKE_B             0
+#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28                  SC_P_PCIE_CTRL0_WAKE_B             3
+#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B              SC_P_PCIE_CTRL0_PERST_B            0
+#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29                 SC_P_PCIE_CTRL0_PERST_B            3
+#define SC_P_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B            SC_P_PCIE_CTRL1_CLKREQ_B           0
+#define SC_P_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA                   SC_P_PCIE_CTRL1_CLKREQ_B           1
+#define SC_P_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC               SC_P_PCIE_CTRL1_CLKREQ_B           2
+#define SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30                SC_P_PCIE_CTRL1_CLKREQ_B           3
+#define SC_P_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B                SC_P_PCIE_CTRL1_WAKE_B             0
+#define SC_P_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL                     SC_P_PCIE_CTRL1_WAKE_B             1
+#define SC_P_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR                SC_P_PCIE_CTRL1_WAKE_B             2
+#define SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31                  SC_P_PCIE_CTRL1_WAKE_B             3
+#define SC_P_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B              SC_P_PCIE_CTRL1_PERST_B            0
+#define SC_P_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL                    SC_P_PCIE_CTRL1_PERST_B            1
+#define SC_P_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR               SC_P_PCIE_CTRL1_PERST_B            2
+#define SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00                 SC_P_PCIE_CTRL1_PERST_B            3
+#define SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA                 SC_P_USB_HSIC0_DATA                0
+#define SC_P_USB_HSIC0_DATA_DMA_I2C1_SDA                        SC_P_USB_HSIC0_DATA                1
+#define SC_P_USB_HSIC0_DATA_LSIO_GPIO5_IO01                     SC_P_USB_HSIC0_DATA                3
+#define SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE             SC_P_USB_HSIC0_STROBE              0
+#define SC_P_USB_HSIC0_STROBE_DMA_I2C1_SCL                      SC_P_USB_HSIC0_STROBE              1
+#define SC_P_USB_HSIC0_STROBE_LSIO_GPIO5_IO02                   SC_P_USB_HSIC0_STROBE              3
+#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK                           SC_P_EMMC0_CLK                     0
+#define SC_P_EMMC0_CLK_CONN_NAND_READY_B                        SC_P_EMMC0_CLK                     1
+#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD                           SC_P_EMMC0_CMD                     0
+#define SC_P_EMMC0_CMD_CONN_NAND_DQS                            SC_P_EMMC0_CMD                     1
+#define SC_P_EMMC0_CMD_AUD_MQS_R                                SC_P_EMMC0_CMD                     2
+#define SC_P_EMMC0_CMD_LSIO_GPIO5_IO03                          SC_P_EMMC0_CMD                     3
+#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0                       SC_P_EMMC0_DATA0                   0
+#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00                       SC_P_EMMC0_DATA0                   1
+#define SC_P_EMMC0_DATA0_LSIO_GPIO5_IO04                        SC_P_EMMC0_DATA0                   3
+#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1                       SC_P_EMMC0_DATA1                   0
+#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01                       SC_P_EMMC0_DATA1                   1
+#define SC_P_EMMC0_DATA1_LSIO_GPIO5_IO05                        SC_P_EMMC0_DATA1                   3
+#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2                       SC_P_EMMC0_DATA2                   0
+#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02                       SC_P_EMMC0_DATA2                   1
+#define SC_P_EMMC0_DATA2_LSIO_GPIO5_IO06                        SC_P_EMMC0_DATA2                   3
+#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3                       SC_P_EMMC0_DATA3                   0
+#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03                       SC_P_EMMC0_DATA3                   1
+#define SC_P_EMMC0_DATA3_LSIO_GPIO5_IO07                        SC_P_EMMC0_DATA3                   3
+#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4                       SC_P_EMMC0_DATA4                   0
+#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04                       SC_P_EMMC0_DATA4                   1
+#define SC_P_EMMC0_DATA4_LSIO_GPIO5_IO08                        SC_P_EMMC0_DATA4                   3
+#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5                       SC_P_EMMC0_DATA5                   0
+#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05                       SC_P_EMMC0_DATA5                   1
+#define SC_P_EMMC0_DATA5_LSIO_GPIO5_IO09                        SC_P_EMMC0_DATA5                   3
+#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6                       SC_P_EMMC0_DATA6                   0
+#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06                       SC_P_EMMC0_DATA6                   1
+#define SC_P_EMMC0_DATA6_LSIO_GPIO5_IO10                        SC_P_EMMC0_DATA6                   3
+#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7                       SC_P_EMMC0_DATA7                   0
+#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07                       SC_P_EMMC0_DATA7                   1
+#define SC_P_EMMC0_DATA7_LSIO_GPIO5_IO11                        SC_P_EMMC0_DATA7                   3
+#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE                     SC_P_EMMC0_STROBE                  0
+#define SC_P_EMMC0_STROBE_CONN_NAND_CLE                         SC_P_EMMC0_STROBE                  1
+#define SC_P_EMMC0_STROBE_LSIO_GPIO5_IO12                       SC_P_EMMC0_STROBE                  3
+#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B                   SC_P_EMMC0_RESET_B                 0
+#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B                       SC_P_EMMC0_RESET_B                 1
+#define SC_P_EMMC0_RESET_B_CONN_USDHC1_VSELECT                  SC_P_EMMC0_RESET_B                 2
+#define SC_P_EMMC0_RESET_B_LSIO_GPIO5_IO13                      SC_P_EMMC0_RESET_B                 3
+#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK                         SC_P_USDHC1_CLK                    0
+#define SC_P_USDHC1_CLK_AUD_MQS_R                               SC_P_USDHC1_CLK                    1
+#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD                         SC_P_USDHC1_CMD                    0
+#define SC_P_USDHC1_CMD_AUD_MQS_L                               SC_P_USDHC1_CMD                    1
+#define SC_P_USDHC1_CMD_LSIO_GPIO5_IO14                         SC_P_USDHC1_CMD                    3
+#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0                     SC_P_USDHC1_DATA0                  0
+#define SC_P_USDHC1_DATA0_CONN_NAND_RE_N                        SC_P_USDHC1_DATA0                  1
+#define SC_P_USDHC1_DATA0_LSIO_GPIO5_IO15                       SC_P_USDHC1_DATA0                  3
+#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1                     SC_P_USDHC1_DATA1                  0
+#define SC_P_USDHC1_DATA1_CONN_NAND_RE_P                        SC_P_USDHC1_DATA1                  1
+#define SC_P_USDHC1_DATA1_LSIO_GPIO5_IO16                       SC_P_USDHC1_DATA1                  3
+#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2                     SC_P_USDHC1_DATA2                  0
+#define SC_P_USDHC1_DATA2_CONN_NAND_DQS_N                       SC_P_USDHC1_DATA2                  1
+#define SC_P_USDHC1_DATA2_LSIO_GPIO5_IO17                       SC_P_USDHC1_DATA2                  3
+#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3                     SC_P_USDHC1_DATA3                  0
+#define SC_P_USDHC1_DATA3_CONN_NAND_DQS_P                       SC_P_USDHC1_DATA3                  1
+#define SC_P_USDHC1_DATA3_LSIO_GPIO5_IO18                       SC_P_USDHC1_DATA3                  3
+#define SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4                     SC_P_USDHC1_DATA4                  0
+#define SC_P_USDHC1_DATA4_CONN_NAND_CE0_B                       SC_P_USDHC1_DATA4                  1
+#define SC_P_USDHC1_DATA4_AUD_MQS_R                             SC_P_USDHC1_DATA4                  2
+#define SC_P_USDHC1_DATA4_LSIO_GPIO5_IO19                       SC_P_USDHC1_DATA4                  3
+#define SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5                     SC_P_USDHC1_DATA5                  0
+#define SC_P_USDHC1_DATA5_CONN_NAND_RE_B                        SC_P_USDHC1_DATA5                  1
+#define SC_P_USDHC1_DATA5_AUD_MQS_L                             SC_P_USDHC1_DATA5                  2
+#define SC_P_USDHC1_DATA5_LSIO_GPIO5_IO20                       SC_P_USDHC1_DATA5                  3
+#define SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6                     SC_P_USDHC1_DATA6                  0
+#define SC_P_USDHC1_DATA6_CONN_NAND_WE_B                        SC_P_USDHC1_DATA6                  1
+#define SC_P_USDHC1_DATA6_CONN_USDHC1_WP                        SC_P_USDHC1_DATA6                  2
+#define SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21                       SC_P_USDHC1_DATA6                  3
+#define SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7                     SC_P_USDHC1_DATA7                  0
+#define SC_P_USDHC1_DATA7_CONN_NAND_ALE                         SC_P_USDHC1_DATA7                  1
+#define SC_P_USDHC1_DATA7_CONN_USDHC1_CD_B                      SC_P_USDHC1_DATA7                  2
+#define SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22                       SC_P_USDHC1_DATA7                  3
+#define SC_P_USDHC1_STROBE_CONN_USDHC1_STROBE                   SC_P_USDHC1_STROBE                 0
+#define SC_P_USDHC1_STROBE_CONN_NAND_CE1_B                      SC_P_USDHC1_STROBE                 1
+#define SC_P_USDHC1_STROBE_CONN_USDHC1_RESET_B                  SC_P_USDHC1_STROBE                 2
+#define SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23                      SC_P_USDHC1_STROBE                 3
+#define SC_P_USDHC2_CLK_CONN_USDHC2_CLK                         SC_P_USDHC2_CLK                    0
+#define SC_P_USDHC2_CLK_AUD_MQS_R                               SC_P_USDHC2_CLK                    1
+#define SC_P_USDHC2_CLK_LSIO_GPIO5_IO24                         SC_P_USDHC2_CLK                    3
+#define SC_P_USDHC2_CMD_CONN_USDHC2_CMD                         SC_P_USDHC2_CMD                    0
+#define SC_P_USDHC2_CMD_AUD_MQS_L                               SC_P_USDHC2_CMD                    1
+#define SC_P_USDHC2_CMD_LSIO_GPIO5_IO25                         SC_P_USDHC2_CMD                    3
+#define SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0                     SC_P_USDHC2_DATA0                  0
+#define SC_P_USDHC2_DATA0_DMA_UART4_RX                          SC_P_USDHC2_DATA0                  1
+#define SC_P_USDHC2_DATA0_LSIO_GPIO5_IO26                       SC_P_USDHC2_DATA0                  3
+#define SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1                     SC_P_USDHC2_DATA1                  0
+#define SC_P_USDHC2_DATA1_DMA_UART4_TX                          SC_P_USDHC2_DATA1                  1
+#define SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27                       SC_P_USDHC2_DATA1                  3
+#define SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2                     SC_P_USDHC2_DATA2                  0
+#define SC_P_USDHC2_DATA2_DMA_UART4_CTS_B                       SC_P_USDHC2_DATA2                  1
+#define SC_P_USDHC2_DATA2_LSIO_GPIO5_IO28                       SC_P_USDHC2_DATA2                  3
+#define SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3                     SC_P_USDHC2_DATA3                  0
+#define SC_P_USDHC2_DATA3_DMA_UART4_RTS_B                       SC_P_USDHC2_DATA3                  1
+#define SC_P_USDHC2_DATA3_LSIO_GPIO5_IO29                       SC_P_USDHC2_DATA3                  3
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC               SC_P_ENET0_RGMII_TXC               0
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT             SC_P_ENET0_RGMII_TXC               1
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN              SC_P_ENET0_RGMII_TXC               2
+#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO5_IO30                    SC_P_ENET0_RGMII_TXC               3
+#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL         SC_P_ENET0_RGMII_TX_CTL            0
+#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31                 SC_P_ENET0_RGMII_TX_CTL            3
+#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0             SC_P_ENET0_RGMII_TXD0              0
+#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00                   SC_P_ENET0_RGMII_TXD0              3
+#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1             SC_P_ENET0_RGMII_TXD1              0
+#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01                   SC_P_ENET0_RGMII_TXD1              3
+#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2             SC_P_ENET0_RGMII_TXD2              0
+#define SC_P_ENET0_RGMII_TXD2_DMA_UART3_TX                      SC_P_ENET0_RGMII_TXD2              1
+#define SC_P_ENET0_RGMII_TXD2_VPU_TSI_S1_VID                    SC_P_ENET0_RGMII_TXD2              2
+#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02                   SC_P_ENET0_RGMII_TXD2              3
+#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3             SC_P_ENET0_RGMII_TXD3              0
+#define SC_P_ENET0_RGMII_TXD3_DMA_UART3_RTS_B                   SC_P_ENET0_RGMII_TXD3              1
+#define SC_P_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC                   SC_P_ENET0_RGMII_TXD3              2
+#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03                   SC_P_ENET0_RGMII_TXD3              3
+#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC               SC_P_ENET0_RGMII_RXC               0
+#define SC_P_ENET0_RGMII_RXC_DMA_UART3_CTS_B                    SC_P_ENET0_RGMII_RXC               1
+#define SC_P_ENET0_RGMII_RXC_VPU_TSI_S1_DATA                    SC_P_ENET0_RGMII_RXC               2
+#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO6_IO04                    SC_P_ENET0_RGMII_RXC               3
+#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL         SC_P_ENET0_RGMII_RX_CTL            0
+#define SC_P_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID                  SC_P_ENET0_RGMII_RX_CTL            2
+#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05                 SC_P_ENET0_RGMII_RX_CTL            3
+#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0             SC_P_ENET0_RGMII_RXD0              0
+#define SC_P_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC                   SC_P_ENET0_RGMII_RXD0              2
+#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06                   SC_P_ENET0_RGMII_RXD0              3
+#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1             SC_P_ENET0_RGMII_RXD1              0
+#define SC_P_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA                   SC_P_ENET0_RGMII_RXD1              2
+#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07                   SC_P_ENET0_RGMII_RXD1              3
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2             SC_P_ENET0_RGMII_RXD2              0
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER             SC_P_ENET0_RGMII_RXD2              1
+#define SC_P_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK                    SC_P_ENET0_RGMII_RXD2              2
+#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08                   SC_P_ENET0_RGMII_RXD2              3
+#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3             SC_P_ENET0_RGMII_RXD3              0
+#define SC_P_ENET0_RGMII_RXD3_DMA_UART3_RX                      SC_P_ENET0_RGMII_RXD3              1
+#define SC_P_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK                    SC_P_ENET0_RGMII_RXD3              2
+#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09                   SC_P_ENET0_RGMII_RXD3              3
+#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC               SC_P_ENET1_RGMII_TXC               0
+#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT             SC_P_ENET1_RGMII_TXC               1
+#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN              SC_P_ENET1_RGMII_TXC               2
+#define SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10                    SC_P_ENET1_RGMII_TXC               3
+#define SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL         SC_P_ENET1_RGMII_TX_CTL            0
+#define SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11                 SC_P_ENET1_RGMII_TX_CTL            3
+#define SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0             SC_P_ENET1_RGMII_TXD0              0
+#define SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12                   SC_P_ENET1_RGMII_TXD0              3
+#define SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1             SC_P_ENET1_RGMII_TXD1              0
+#define SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13                   SC_P_ENET1_RGMII_TXD1              3
+#define SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2             SC_P_ENET1_RGMII_TXD2              0
+#define SC_P_ENET1_RGMII_TXD2_DMA_UART3_TX                      SC_P_ENET1_RGMII_TXD2              1
+#define SC_P_ENET1_RGMII_TXD2_VPU_TSI_S1_VID                    SC_P_ENET1_RGMII_TXD2              2
+#define SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14                   SC_P_ENET1_RGMII_TXD2              3
+#define SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3             SC_P_ENET1_RGMII_TXD3              0
+#define SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B                   SC_P_ENET1_RGMII_TXD3              1
+#define SC_P_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC                   SC_P_ENET1_RGMII_TXD3              2
+#define SC_P_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15                   SC_P_ENET1_RGMII_TXD3              3
+#define SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC               SC_P_ENET1_RGMII_RXC               0
+#define SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B                    SC_P_ENET1_RGMII_RXC               1
+#define SC_P_ENET1_RGMII_RXC_VPU_TSI_S1_DATA                    SC_P_ENET1_RGMII_RXC               2
+#define SC_P_ENET1_RGMII_RXC_LSIO_GPIO6_IO16                    SC_P_ENET1_RGMII_RXC               3
+#define SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL         SC_P_ENET1_RGMII_RX_CTL            0
+#define SC_P_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID                  SC_P_ENET1_RGMII_RX_CTL            2
+#define SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17                 SC_P_ENET1_RGMII_RX_CTL            3
+#define SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0             SC_P_ENET1_RGMII_RXD0              0
+#define SC_P_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC                   SC_P_ENET1_RGMII_RXD0              2
+#define SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18                   SC_P_ENET1_RGMII_RXD0              3
+#define SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1             SC_P_ENET1_RGMII_RXD1              0
+#define SC_P_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA                   SC_P_ENET1_RGMII_RXD1              2
+#define SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19                   SC_P_ENET1_RGMII_RXD1              3
+#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2             SC_P_ENET1_RGMII_RXD2              0
+#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER             SC_P_ENET1_RGMII_RXD2              1
+#define SC_P_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK                    SC_P_ENET1_RGMII_RXD2              2
+#define SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20                   SC_P_ENET1_RGMII_RXD2              3
+#define SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3             SC_P_ENET1_RGMII_RXD3              0
+#define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX                      SC_P_ENET1_RGMII_RXD3              1
+#define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK                    SC_P_ENET1_RGMII_RXD3              2
+#define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21                   SC_P_ENET1_RGMII_RXD3              3
+/*@}*/
+
+#endif /* SC_PADS_H */
+
diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h
new file mode 100644
index 0000000000..8049735841
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h
@@ -0,0 +1,770 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*!
+ * Header file used to configure SoC pad list.
+ */
+
+#ifndef SC_PADS_H
+#define SC_PADS_H
+
+/* Includes */
+
+/* Defines */
+
+/*!
+ * @name Pad Definitions
+ */
+/*@{*/
+#define SC_P_PCIE_CTRL0_PERST_B                  0    /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
+#define SC_P_PCIE_CTRL0_CLKREQ_B                 1    /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
+#define SC_P_PCIE_CTRL0_WAKE_B                   2    /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP       3    /*!<  */
+#define SC_P_USB_SS3_TC0                         4    /*!< ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */
+#define SC_P_USB_SS3_TC1                         5    /*!< ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
+#define SC_P_USB_SS3_TC2                         6    /*!< ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */
+#define SC_P_USB_SS3_TC3                         7    /*!< ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO            8    /*!<  */
+#define SC_P_EMMC0_CLK                           9    /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
+#define SC_P_EMMC0_CMD                           10   /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
+#define SC_P_EMMC0_DATA0                         11   /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
+#define SC_P_EMMC0_DATA1                         12   /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
+#define SC_P_EMMC0_DATA2                         13   /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
+#define SC_P_EMMC0_DATA3                         14   /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0       15   /*!<  */
+#define SC_P_EMMC0_DATA4                         16   /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */
+#define SC_P_EMMC0_DATA5                         17   /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */
+#define SC_P_EMMC0_DATA6                         18   /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
+#define SC_P_EMMC0_DATA7                         19   /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */
+#define SC_P_EMMC0_STROBE                        20   /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */
+#define SC_P_EMMC0_RESET_B                       21   /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1       22   /*!<  */
+#define SC_P_USDHC1_RESET_B                      23   /*!< CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */
+#define SC_P_USDHC1_VSELECT                      24   /*!< CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */
+#define SC_P_CTL_NAND_RE_P_N                     25   /*!<  */
+#define SC_P_USDHC1_WP                           26   /*!< CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */
+#define SC_P_USDHC1_CD_B                         27   /*!< CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */
+#define SC_P_CTL_NAND_DQS_P_N                    28   /*!<  */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP       29   /*!<  */
+#define SC_P_USDHC1_CLK                          30   /*!< CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */
+#define SC_P_USDHC1_CMD                          31   /*!< CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */
+#define SC_P_USDHC1_DATA0                        32   /*!< CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */
+#define SC_P_USDHC1_DATA1                        33   /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */
+#define SC_P_USDHC1_DATA2                        34   /*!< CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */
+#define SC_P_USDHC1_DATA3                        35   /*!< CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3         36   /*!<  */
+#define SC_P_ENET0_RGMII_TXC                     37   /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */
+#define SC_P_ENET0_RGMII_TX_CTL                  38   /*!< CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */
+#define SC_P_ENET0_RGMII_TXD0                    39   /*!< CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */
+#define SC_P_ENET0_RGMII_TXD1                    40   /*!< CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */
+#define SC_P_ENET0_RGMII_TXD2                    41   /*!< CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */
+#define SC_P_ENET0_RGMII_TXD3                    42   /*!< CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0   43   /*!<  */
+#define SC_P_ENET0_RGMII_RXC                     44   /*!< CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
+#define SC_P_ENET0_RGMII_RX_CTL                  45   /*!< CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
+#define SC_P_ENET0_RGMII_RXD0                    46   /*!< CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
+#define SC_P_ENET0_RGMII_RXD1                    47   /*!< CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
+#define SC_P_ENET0_RGMII_RXD2                    48   /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
+#define SC_P_ENET0_RGMII_RXD3                    49   /*!< CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1   50   /*!<  */
+#define SC_P_ENET0_REFCLK_125M_25M               51   /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */
+#define SC_P_ENET0_MDIO                          52   /*!< CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */
+#define SC_P_ENET0_MDC                           53   /*!< CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT        54   /*!<  */
+#define SC_P_ESAI0_FSR                           55   /*!< ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */
+#define SC_P_ESAI0_FST                           56   /*!< ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */
+#define SC_P_ESAI0_SCKR                          57   /*!< ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
+#define SC_P_ESAI0_SCKT                          58   /*!< ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */
+#define SC_P_ESAI0_TX0                           59   /*!< ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */
+#define SC_P_ESAI0_TX1                           60   /*!< ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */
+#define SC_P_ESAI0_TX2_RX3                       61   /*!< ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */
+#define SC_P_ESAI0_TX3_RX2                       62   /*!< ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */
+#define SC_P_ESAI0_TX4_RX1                       63   /*!< ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */
+#define SC_P_ESAI0_TX5_RX0                       64   /*!< ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */
+#define SC_P_SPDIF0_RX                           65   /*!< ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */
+#define SC_P_SPDIF0_TX                           66   /*!< ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */
+#define SC_P_SPDIF0_EXT_CLK                      67   /*!< ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB       68   /*!<  */
+#define SC_P_SPI3_SCK                            69   /*!< ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */
+#define SC_P_SPI3_SDO                            70   /*!< ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */
+#define SC_P_SPI3_SDI                            71   /*!< ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */
+#define SC_P_SPI3_CS0                            72   /*!< ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */
+#define SC_P_SPI3_CS1                            73   /*!< ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */
+#define SC_P_MCLK_IN1                            74   /*!< ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */
+#define SC_P_MCLK_IN0                            75   /*!< ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */
+#define SC_P_MCLK_OUT0                           76   /*!< ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */
+#define SC_P_UART1_TX                            77   /*!< ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */
+#define SC_P_UART1_RX                            78   /*!< ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
+#define SC_P_UART1_RTS_B                         79   /*!< ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
+#define SC_P_UART1_CTS_B                         80   /*!< ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK       81   /*!<  */
+#define SC_P_SAI0_TXD                            82   /*!< ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */
+#define SC_P_SAI0_TXC                            83   /*!< ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */
+#define SC_P_SAI0_RXD                            84   /*!< ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */
+#define SC_P_SAI0_TXFS                           85   /*!< ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */
+#define SC_P_SAI1_RXD                            86   /*!< ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */
+#define SC_P_SAI1_RXC                            87   /*!< ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */
+#define SC_P_SAI1_RXFS                           88   /*!< ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */
+#define SC_P_SPI2_CS0                            89   /*!< ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */
+#define SC_P_SPI2_SDO                            90   /*!< ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */
+#define SC_P_SPI2_SDI                            91   /*!< ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */
+#define SC_P_SPI2_SCK                            92   /*!< ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */
+#define SC_P_SPI0_SCK                            93   /*!< ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */
+#define SC_P_SPI0_SDI                            94   /*!< ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */
+#define SC_P_SPI0_SDO                            95   /*!< ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */
+#define SC_P_SPI0_CS1                            96   /*!< ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */
+#define SC_P_SPI0_CS0                            97   /*!< ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT       98   /*!<  */
+#define SC_P_ADC_IN1                             99   /*!< ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */
+#define SC_P_ADC_IN0                             100  /*!< ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */
+#define SC_P_ADC_IN3                             101  /*!< ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */
+#define SC_P_ADC_IN2                             102  /*!< ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */
+#define SC_P_ADC_IN5                             103  /*!< ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */
+#define SC_P_ADC_IN4                             104  /*!< ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */
+#define SC_P_FLEXCAN0_RX                         105  /*!< ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */
+#define SC_P_FLEXCAN0_TX                         106  /*!< ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */
+#define SC_P_FLEXCAN1_RX                         107  /*!< ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */
+#define SC_P_FLEXCAN1_TX                         108  /*!< ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
+#define SC_P_FLEXCAN2_RX                         109  /*!< ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
+#define SC_P_FLEXCAN2_TX                         110  /*!< ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
+#define SC_P_UART0_RX                            111  /*!< ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */
+#define SC_P_UART0_TX                            112  /*!< ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */
+#define SC_P_UART2_TX                            113  /*!< ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
+#define SC_P_UART2_RX                            114  /*!< ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH        115  /*!<  */
+#define SC_P_MIPI_DSI0_I2C0_SCL                  116  /*!< MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */
+#define SC_P_MIPI_DSI0_I2C0_SDA                  117  /*!< MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */
+#define SC_P_MIPI_DSI0_GPIO0_00                  118  /*!< MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_DSI0_GPIO0_01                  119  /*!< MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_DSI1_I2C0_SCL                  120  /*!< MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */
+#define SC_P_MIPI_DSI1_I2C0_SDA                  121  /*!< MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */
+#define SC_P_MIPI_DSI1_GPIO0_00                  122  /*!< MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */
+#define SC_P_MIPI_DSI1_GPIO0_01                  123  /*!< MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO   124  /*!<  */
+#define SC_P_JTAG_TRST_B                         125  /*!< SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SCL                        126  /*!< SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
+#define SC_P_PMIC_I2C_SDA                        127  /*!< SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
+#define SC_P_PMIC_INT_B                          128  /*!< SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00                        129  /*!< SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
+#define SC_P_SCU_GPIO0_01                        130  /*!< SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
+#define SC_P_SCU_PMIC_STANDBY                    131  /*!< SCU.DSC.PMIC_STANDBY */
+#define SC_P_SCU_BOOT_MODE0                      132  /*!< SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE1                      133  /*!< SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE2                      134  /*!< SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */
+#define SC_P_SCU_BOOT_MODE3                      135  /*!< SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
+#define SC_P_CSI_D00                             136  /*!< CI_PI.D02, ADMA.SAI0.RXC */
+#define SC_P_CSI_D01                             137  /*!< CI_PI.D03, ADMA.SAI0.RXD */
+#define SC_P_CSI_D02                             138  /*!< CI_PI.D04, ADMA.SAI0.RXFS */
+#define SC_P_CSI_D03                             139  /*!< CI_PI.D05, ADMA.SAI2.RXC */
+#define SC_P_CSI_D04                             140  /*!< CI_PI.D06, ADMA.SAI2.RXD */
+#define SC_P_CSI_D05                             141  /*!< CI_PI.D07, ADMA.SAI2.RXFS */
+#define SC_P_CSI_D06                             142  /*!< CI_PI.D08, ADMA.SAI3.RXC */
+#define SC_P_CSI_D07                             143  /*!< CI_PI.D09, ADMA.SAI3.RXD */
+#define SC_P_CSI_HSYNC                           144  /*!< CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */
+#define SC_P_CSI_VSYNC                           145  /*!< CI_PI.VSYNC, CI_PI.D01 */
+#define SC_P_CSI_PCLK                            146  /*!< CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
+#define SC_P_CSI_MCLK                            147  /*!< CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
+#define SC_P_CSI_EN                              148  /*!< CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
+#define SC_P_CSI_RESET                           149  /*!< CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD       150  /*!<  */
+#define SC_P_MIPI_CSI0_MCLK_OUT                  151  /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */
+#define SC_P_MIPI_CSI0_I2C0_SCL                  152  /*!< MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */
+#define SC_P_MIPI_CSI0_I2C0_SDA                  153  /*!< MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */
+#define SC_P_MIPI_CSI0_GPIO0_01                  154  /*!< MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */
+#define SC_P_MIPI_CSI0_GPIO0_00                  155  /*!< MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */
+#define SC_P_QSPI0A_DATA0                        156  /*!< LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
+#define SC_P_QSPI0A_DATA1                        157  /*!< LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
+#define SC_P_QSPI0A_DATA2                        158  /*!< LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
+#define SC_P_QSPI0A_DATA3                        159  /*!< LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
+#define SC_P_QSPI0A_DQS                          160  /*!< LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
+#define SC_P_QSPI0A_SS0_B                        161  /*!< LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
+#define SC_P_QSPI0A_SS1_B                        162  /*!< LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */
+#define SC_P_QSPI0A_SCLK                         163  /*!< LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A        164  /*!<  */
+#define SC_P_QSPI0B_SCLK                         165  /*!< LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */
+#define SC_P_QSPI0B_DATA0                        166  /*!< LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */
+#define SC_P_QSPI0B_DATA1                        167  /*!< LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */
+#define SC_P_QSPI0B_DATA2                        168  /*!< LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */
+#define SC_P_QSPI0B_DATA3                        169  /*!< LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */
+#define SC_P_QSPI0B_DQS                          170  /*!< LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */
+#define SC_P_QSPI0B_SS0_B                        171  /*!< LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */
+#define SC_P_QSPI0B_SS1_B                        172  /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B        173  /*!<  */
+/*@}*/
+
+/*!
+ * @name Pad Mux Definitions
+ * format: name padid padmux
+ */
+/*@{*/
+#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B              SC_P_PCIE_CTRL0_PERST_B            0
+#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00                 SC_P_PCIE_CTRL0_PERST_B            4
+#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B            SC_P_PCIE_CTRL0_CLKREQ_B           0
+#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01                SC_P_PCIE_CTRL0_CLKREQ_B           4
+#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B                SC_P_PCIE_CTRL0_WAKE_B             0
+#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02                  SC_P_PCIE_CTRL0_WAKE_B             4
+#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL                          SC_P_USB_SS3_TC0                   0
+#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR                      SC_P_USB_SS3_TC0                   1
+#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR                      SC_P_USB_SS3_TC0                   2
+#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03                        SC_P_USB_SS3_TC0                   4
+#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL                          SC_P_USB_SS3_TC1                   0
+#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR                      SC_P_USB_SS3_TC1                   1
+#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04                        SC_P_USB_SS3_TC1                   4
+#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA                          SC_P_USB_SS3_TC2                   0
+#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC                       SC_P_USB_SS3_TC2                   1
+#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC                       SC_P_USB_SS3_TC2                   2
+#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05                        SC_P_USB_SS3_TC2                   4
+#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA                          SC_P_USB_SS3_TC3                   0
+#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC                       SC_P_USB_SS3_TC3                   1
+#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06                        SC_P_USB_SS3_TC3                   4
+#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK                           SC_P_EMMC0_CLK                     0
+#define SC_P_EMMC0_CLK_CONN_NAND_READY_B                        SC_P_EMMC0_CLK                     1
+#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07                          SC_P_EMMC0_CLK                     4
+#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD                           SC_P_EMMC0_CMD                     0
+#define SC_P_EMMC0_CMD_CONN_NAND_DQS                            SC_P_EMMC0_CMD                     1
+#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08                          SC_P_EMMC0_CMD                     4
+#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0                       SC_P_EMMC0_DATA0                   0
+#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00                       SC_P_EMMC0_DATA0                   1
+#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09                        SC_P_EMMC0_DATA0                   4
+#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1                       SC_P_EMMC0_DATA1                   0
+#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01                       SC_P_EMMC0_DATA1                   1
+#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10                        SC_P_EMMC0_DATA1                   4
+#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2                       SC_P_EMMC0_DATA2                   0
+#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02                       SC_P_EMMC0_DATA2                   1
+#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11                        SC_P_EMMC0_DATA2                   4
+#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3                       SC_P_EMMC0_DATA3                   0
+#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03                       SC_P_EMMC0_DATA3                   1
+#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12                        SC_P_EMMC0_DATA3                   4
+#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4                       SC_P_EMMC0_DATA4                   0
+#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04                       SC_P_EMMC0_DATA4                   1
+#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP                          SC_P_EMMC0_DATA4                   3
+#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13                        SC_P_EMMC0_DATA4                   4
+#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5                       SC_P_EMMC0_DATA5                   0
+#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05                       SC_P_EMMC0_DATA5                   1
+#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT                     SC_P_EMMC0_DATA5                   3
+#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14                        SC_P_EMMC0_DATA5                   4
+#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6                       SC_P_EMMC0_DATA6                   0
+#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06                       SC_P_EMMC0_DATA6                   1
+#define SC_P_EMMC0_DATA6_CONN_MLB_CLK                           SC_P_EMMC0_DATA6                   3
+#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15                        SC_P_EMMC0_DATA6                   4
+#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7                       SC_P_EMMC0_DATA7                   0
+#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07                       SC_P_EMMC0_DATA7                   1
+#define SC_P_EMMC0_DATA7_CONN_MLB_SIG                           SC_P_EMMC0_DATA7                   3
+#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16                        SC_P_EMMC0_DATA7                   4
+#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE                     SC_P_EMMC0_STROBE                  0
+#define SC_P_EMMC0_STROBE_CONN_NAND_CLE                         SC_P_EMMC0_STROBE                  1
+#define SC_P_EMMC0_STROBE_CONN_MLB_DATA                         SC_P_EMMC0_STROBE                  3
+#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17                       SC_P_EMMC0_STROBE                  4
+#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B                   SC_P_EMMC0_RESET_B                 0
+#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B                       SC_P_EMMC0_RESET_B                 1
+#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18                      SC_P_EMMC0_RESET_B                 4
+#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B                 SC_P_USDHC1_RESET_B                0
+#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N                      SC_P_USDHC1_RESET_B                1
+#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK                       SC_P_USDHC1_RESET_B                2
+#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19                     SC_P_USDHC1_RESET_B                4
+#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT                 SC_P_USDHC1_VSELECT                0
+#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P                      SC_P_USDHC1_VSELECT                1
+#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO                       SC_P_USDHC1_VSELECT                2
+#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B                      SC_P_USDHC1_VSELECT                3
+#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20                     SC_P_USDHC1_VSELECT                4
+#define SC_P_USDHC1_WP_CONN_USDHC1_WP                           SC_P_USDHC1_WP                     0
+#define SC_P_USDHC1_WP_CONN_NAND_DQS_N                          SC_P_USDHC1_WP                     1
+#define SC_P_USDHC1_WP_ADMA_SPI2_SDI                            SC_P_USDHC1_WP                     2
+#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21                          SC_P_USDHC1_WP                     4
+#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B                       SC_P_USDHC1_CD_B                   0
+#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P                        SC_P_USDHC1_CD_B                   1
+#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0                          SC_P_USDHC1_CD_B                   2
+#define SC_P_USDHC1_CD_B_CONN_NAND_DQS                          SC_P_USDHC1_CD_B                   3
+#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22                        SC_P_USDHC1_CD_B                   4
+#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK                         SC_P_USDHC1_CLK                    0
+#define SC_P_USDHC1_CLK_ADMA_UART3_RX                           SC_P_USDHC1_CLK                    2
+#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23                         SC_P_USDHC1_CLK                    4
+#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD                         SC_P_USDHC1_CMD                    0
+#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B                         SC_P_USDHC1_CMD                    1
+#define SC_P_USDHC1_CMD_ADMA_MQS_R                              SC_P_USDHC1_CMD                    2
+#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24                         SC_P_USDHC1_CMD                    4
+#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0                     SC_P_USDHC1_DATA0                  0
+#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B                       SC_P_USDHC1_DATA0                  1
+#define SC_P_USDHC1_DATA0_ADMA_MQS_L                            SC_P_USDHC1_DATA0                  2
+#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25                       SC_P_USDHC1_DATA0                  4
+#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1                     SC_P_USDHC1_DATA1                  0
+#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B                        SC_P_USDHC1_DATA1                  1
+#define SC_P_USDHC1_DATA1_ADMA_UART3_TX                         SC_P_USDHC1_DATA1                  2
+#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26                       SC_P_USDHC1_DATA1                  4
+#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2                     SC_P_USDHC1_DATA2                  0
+#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B                        SC_P_USDHC1_DATA2                  1
+#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B                      SC_P_USDHC1_DATA2                  2
+#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27                       SC_P_USDHC1_DATA2                  4
+#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3                     SC_P_USDHC1_DATA3                  0
+#define SC_P_USDHC1_DATA3_CONN_NAND_ALE                         SC_P_USDHC1_DATA3                  1
+#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B                      SC_P_USDHC1_DATA3                  2
+#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28                       SC_P_USDHC1_DATA3                  4
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC               SC_P_ENET0_RGMII_TXC               0
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT             SC_P_ENET0_RGMII_TXC               1
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN              SC_P_ENET0_RGMII_TXC               2
+#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B                    SC_P_ENET0_RGMII_TXC               3
+#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29                    SC_P_ENET0_RGMII_TXC               4
+#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL         SC_P_ENET0_RGMII_TX_CTL            0
+#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B             SC_P_ENET0_RGMII_TX_CTL            3
+#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30                 SC_P_ENET0_RGMII_TX_CTL            4
+#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0             SC_P_ENET0_RGMII_TXD0              0
+#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT               SC_P_ENET0_RGMII_TXD0              3
+#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31                   SC_P_ENET0_RGMII_TXD0              4
+#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1             SC_P_ENET0_RGMII_TXD1              0
+#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP                    SC_P_ENET0_RGMII_TXD1              3
+#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00                   SC_P_ENET0_RGMII_TXD1              4
+#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2             SC_P_ENET0_RGMII_TXD2              0
+#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK                      SC_P_ENET0_RGMII_TXD2              1
+#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B                   SC_P_ENET0_RGMII_TXD2              2
+#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B                  SC_P_ENET0_RGMII_TXD2              3
+#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01                   SC_P_ENET0_RGMII_TXD2              4
+#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3             SC_P_ENET0_RGMII_TXD3              0
+#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG                      SC_P_ENET0_RGMII_TXD3              1
+#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B                    SC_P_ENET0_RGMII_TXD3              2
+#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02                   SC_P_ENET0_RGMII_TXD3              4
+#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC               SC_P_ENET0_RGMII_RXC               0
+#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA                      SC_P_ENET0_RGMII_RXC               1
+#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B                     SC_P_ENET0_RGMII_RXC               2
+#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK                    SC_P_ENET0_RGMII_RXC               3
+#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03                    SC_P_ENET0_RGMII_RXC               4
+#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL         SC_P_ENET0_RGMII_RX_CTL            0
+#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD                 SC_P_ENET0_RGMII_RX_CTL            3
+#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04                 SC_P_ENET0_RGMII_RX_CTL            4
+#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0             SC_P_ENET0_RGMII_RXD0              0
+#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0                 SC_P_ENET0_RGMII_RXD0              3
+#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05                   SC_P_ENET0_RGMII_RXD0              4
+#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1             SC_P_ENET0_RGMII_RXD1              0
+#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1                 SC_P_ENET0_RGMII_RXD1              3
+#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06                   SC_P_ENET0_RGMII_RXD1              4
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2             SC_P_ENET0_RGMII_RXD2              0
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER             SC_P_ENET0_RGMII_RXD2              1
+#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2                 SC_P_ENET0_RGMII_RXD2              3
+#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07                   SC_P_ENET0_RGMII_RXD2              4
+#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3             SC_P_ENET0_RGMII_RXD3              0
+#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE                     SC_P_ENET0_RGMII_RXD3              2
+#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3                 SC_P_ENET0_RGMII_RXD3              3
+#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08                   SC_P_ENET0_RGMII_RXD3              4
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M   SC_P_ENET0_REFCLK_125M_25M         0
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS               SC_P_ENET0_REFCLK_125M_25M         1
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS               SC_P_ENET0_REFCLK_125M_25M         2
+#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09              SC_P_ENET0_REFCLK_125M_25M         4
+#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO                         SC_P_ENET0_MDIO                    0
+#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA                           SC_P_ENET0_MDIO                    1
+#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO                         SC_P_ENET0_MDIO                    2
+#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10                         SC_P_ENET0_MDIO                    4
+#define SC_P_ENET0_MDC_CONN_ENET0_MDC                           SC_P_ENET0_MDC                     0
+#define SC_P_ENET0_MDC_ADMA_I2C3_SCL                            SC_P_ENET0_MDC                     1
+#define SC_P_ENET0_MDC_CONN_ENET1_MDC                           SC_P_ENET0_MDC                     2
+#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11                          SC_P_ENET0_MDC                     4
+#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR                           SC_P_ESAI0_FSR                     0
+#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT                   SC_P_ESAI0_FSR                     1
+#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00                           SC_P_ESAI0_FSR                     2
+#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC                     SC_P_ESAI0_FSR                     3
+#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN                    SC_P_ESAI0_FSR                     4
+#define SC_P_ESAI0_FST_ADMA_ESAI0_FST                           SC_P_ESAI0_FST                     0
+#define SC_P_ESAI0_FST_CONN_MLB_CLK                             SC_P_ESAI0_FST                     1
+#define SC_P_ESAI0_FST_ADMA_LCDIF_D01                           SC_P_ESAI0_FST                     2
+#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2                    SC_P_ESAI0_FST                     3
+#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01                          SC_P_ESAI0_FST                     4
+#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR                         SC_P_ESAI0_SCKR                    0
+#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02                          SC_P_ESAI0_SCKR                    2
+#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL                 SC_P_ESAI0_SCKR                    3
+#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02                         SC_P_ESAI0_SCKR                    4
+#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT                         SC_P_ESAI0_SCKT                    0
+#define SC_P_ESAI0_SCKT_CONN_MLB_SIG                            SC_P_ESAI0_SCKT                    1
+#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03                          SC_P_ESAI0_SCKT                    2
+#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3                   SC_P_ESAI0_SCKT                    3
+#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03                         SC_P_ESAI0_SCKT                    4
+#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0                           SC_P_ESAI0_TX0                     0
+#define SC_P_ESAI0_TX0_CONN_MLB_DATA                            SC_P_ESAI0_TX0                     1
+#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04                           SC_P_ESAI0_TX0                     2
+#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC                     SC_P_ESAI0_TX0                     3
+#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04                          SC_P_ESAI0_TX0                     4
+#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1                           SC_P_ESAI0_TX1                     0
+#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05                           SC_P_ESAI0_TX1                     2
+#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3                    SC_P_ESAI0_TX1                     3
+#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05                          SC_P_ESAI0_TX1                     4
+#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3                   SC_P_ESAI0_TX2_RX3                 0
+#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER                SC_P_ESAI0_TX2_RX3                 1
+#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06                       SC_P_ESAI0_TX2_RX3                 2
+#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2                SC_P_ESAI0_TX2_RX3                 3
+#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06                      SC_P_ESAI0_TX2_RX3                 4
+#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2                   SC_P_ESAI0_TX3_RX2                 0
+#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07                       SC_P_ESAI0_TX3_RX2                 2
+#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1                SC_P_ESAI0_TX3_RX2                 3
+#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07                      SC_P_ESAI0_TX3_RX2                 4
+#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1                   SC_P_ESAI0_TX4_RX1                 0
+#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08                       SC_P_ESAI0_TX4_RX1                 2
+#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0                SC_P_ESAI0_TX4_RX1                 3
+#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08                      SC_P_ESAI0_TX4_RX1                 4
+#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0                   SC_P_ESAI0_TX5_RX0                 0
+#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09                       SC_P_ESAI0_TX5_RX0                 2
+#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1                SC_P_ESAI0_TX5_RX0                 3
+#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09                      SC_P_ESAI0_TX5_RX0                 4
+#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX                           SC_P_SPDIF0_RX                     0
+#define SC_P_SPDIF0_RX_ADMA_MQS_R                               SC_P_SPDIF0_RX                     1
+#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10                           SC_P_SPDIF0_RX                     2
+#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0                    SC_P_SPDIF0_RX                     3
+#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10                          SC_P_SPDIF0_RX                     4
+#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX                           SC_P_SPDIF0_TX                     0
+#define SC_P_SPDIF0_TX_ADMA_MQS_L                               SC_P_SPDIF0_TX                     1
+#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11                           SC_P_SPDIF0_TX                     2
+#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL                  SC_P_SPDIF0_TX                     3
+#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11                          SC_P_SPDIF0_TX                     4
+#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK                 SC_P_SPDIF0_EXT_CLK                0
+#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12                      SC_P_SPDIF0_EXT_CLK                2
+#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M          SC_P_SPDIF0_EXT_CLK                3
+#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12                     SC_P_SPDIF0_EXT_CLK                4
+#define SC_P_SPI3_SCK_ADMA_SPI3_SCK                             SC_P_SPI3_SCK                      0
+#define SC_P_SPI3_SCK_ADMA_LCDIF_D13                            SC_P_SPI3_SCK                      2
+#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13                           SC_P_SPI3_SCK                      4
+#define SC_P_SPI3_SDO_ADMA_SPI3_SDO                             SC_P_SPI3_SDO                      0
+#define SC_P_SPI3_SDO_ADMA_LCDIF_D14                            SC_P_SPI3_SDO                      2
+#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14                           SC_P_SPI3_SDO                      4
+#define SC_P_SPI3_SDI_ADMA_SPI3_SDI                             SC_P_SPI3_SDI                      0
+#define SC_P_SPI3_SDI_ADMA_LCDIF_D15                            SC_P_SPI3_SDI                      2
+#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15                           SC_P_SPI3_SDI                      4
+#define SC_P_SPI3_CS0_ADMA_SPI3_CS0                             SC_P_SPI3_CS0                      0
+#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1                        SC_P_SPI3_CS0                      1
+#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC                          SC_P_SPI3_CS0                      2
+#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16                           SC_P_SPI3_CS0                      4
+#define SC_P_SPI3_CS1_ADMA_SPI3_CS1                             SC_P_SPI3_CS1                      0
+#define SC_P_SPI3_CS1_ADMA_I2C3_SCL                             SC_P_SPI3_CS1                      1
+#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET                          SC_P_SPI3_CS1                      2
+#define SC_P_SPI3_CS1_ADMA_SPI2_CS0                             SC_P_SPI3_CS1                      3
+#define SC_P_SPI3_CS1_ADMA_LCDIF_D16                            SC_P_SPI3_CS1                      4
+#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1                         SC_P_MCLK_IN1                      0
+#define SC_P_MCLK_IN1_ADMA_I2C3_SDA                             SC_P_MCLK_IN1                      1
+#define SC_P_MCLK_IN1_ADMA_LCDIF_EN                             SC_P_MCLK_IN1                      2
+#define SC_P_MCLK_IN1_ADMA_SPI2_SCK                             SC_P_MCLK_IN1                      3
+#define SC_P_MCLK_IN1_ADMA_LCDIF_D17                            SC_P_MCLK_IN1                      4
+#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0                         SC_P_MCLK_IN0                      0
+#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK                      SC_P_MCLK_IN0                      1
+#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC                          SC_P_MCLK_IN0                      2
+#define SC_P_MCLK_IN0_ADMA_SPI2_SDI                             SC_P_MCLK_IN0                      3
+#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19                           SC_P_MCLK_IN0                      4
+#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0                       SC_P_MCLK_OUT0                     0
+#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK                     SC_P_MCLK_OUT0                     1
+#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK                           SC_P_MCLK_OUT0                     2
+#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO                            SC_P_MCLK_OUT0                     3
+#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20                          SC_P_MCLK_OUT0                     4
+#define SC_P_UART1_TX_ADMA_UART1_TX                             SC_P_UART1_TX                      0
+#define SC_P_UART1_TX_LSIO_PWM0_OUT                             SC_P_UART1_TX                      1
+#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE                         SC_P_UART1_TX                      2
+#define SC_P_UART1_TX_LSIO_GPIO0_IO21                           SC_P_UART1_TX                      4
+#define SC_P_UART1_RX_ADMA_UART1_RX                             SC_P_UART1_RX                      0
+#define SC_P_UART1_RX_LSIO_PWM1_OUT                             SC_P_UART1_RX                      1
+#define SC_P_UART1_RX_LSIO_GPT0_COMPARE                         SC_P_UART1_RX                      2
+#define SC_P_UART1_RX_LSIO_GPT1_CLK                             SC_P_UART1_RX                      3
+#define SC_P_UART1_RX_LSIO_GPIO0_IO22                           SC_P_UART1_RX                      4
+#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B                       SC_P_UART1_RTS_B                   0
+#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT                          SC_P_UART1_RTS_B                   1
+#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16                         SC_P_UART1_RTS_B                   2
+#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE                      SC_P_UART1_RTS_B                   3
+#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK                          SC_P_UART1_RTS_B                   4
+#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B                       SC_P_UART1_CTS_B                   0
+#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT                          SC_P_UART1_CTS_B                   1
+#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17                         SC_P_UART1_CTS_B                   2
+#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE                      SC_P_UART1_CTS_B                   3
+#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24                        SC_P_UART1_CTS_B                   4
+#define SC_P_SAI0_TXD_ADMA_SAI0_TXD                             SC_P_SAI0_TXD                      0
+#define SC_P_SAI0_TXD_ADMA_SAI1_RXC                             SC_P_SAI0_TXD                      1
+#define SC_P_SAI0_TXD_ADMA_SPI1_SDO                             SC_P_SAI0_TXD                      2
+#define SC_P_SAI0_TXD_ADMA_LCDIF_D18                            SC_P_SAI0_TXD                      3
+#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25                           SC_P_SAI0_TXD                      4
+#define SC_P_SAI0_TXC_ADMA_SAI0_TXC                             SC_P_SAI0_TXC                      0
+#define SC_P_SAI0_TXC_ADMA_SAI1_TXD                             SC_P_SAI0_TXC                      1
+#define SC_P_SAI0_TXC_ADMA_SPI1_SDI                             SC_P_SAI0_TXC                      2
+#define SC_P_SAI0_TXC_ADMA_LCDIF_D19                            SC_P_SAI0_TXC                      3
+#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26                           SC_P_SAI0_TXC                      4
+#define SC_P_SAI0_RXD_ADMA_SAI0_RXD                             SC_P_SAI0_RXD                      0
+#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS                            SC_P_SAI0_RXD                      1
+#define SC_P_SAI0_RXD_ADMA_SPI1_CS0                             SC_P_SAI0_RXD                      2
+#define SC_P_SAI0_RXD_ADMA_LCDIF_D20                            SC_P_SAI0_RXD                      3
+#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27                           SC_P_SAI0_RXD                      4
+#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS                           SC_P_SAI0_TXFS                     0
+#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1                            SC_P_SAI0_TXFS                     1
+#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK                            SC_P_SAI0_TXFS                     2
+#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28                          SC_P_SAI0_TXFS                     4
+#define SC_P_SAI1_RXD_ADMA_SAI1_RXD                             SC_P_SAI1_RXD                      0
+#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS                            SC_P_SAI1_RXD                      1
+#define SC_P_SAI1_RXD_ADMA_SPI1_CS1                             SC_P_SAI1_RXD                      2
+#define SC_P_SAI1_RXD_ADMA_LCDIF_D21                            SC_P_SAI1_RXD                      3
+#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29                           SC_P_SAI1_RXD                      4
+#define SC_P_SAI1_RXC_ADMA_SAI1_RXC                             SC_P_SAI1_RXC                      0
+#define SC_P_SAI1_RXC_ADMA_SAI1_TXC                             SC_P_SAI1_RXC                      1
+#define SC_P_SAI1_RXC_ADMA_LCDIF_D22                            SC_P_SAI1_RXC                      3
+#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30                           SC_P_SAI1_RXC                      4
+#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS                           SC_P_SAI1_RXFS                     0
+#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS                           SC_P_SAI1_RXFS                     1
+#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23                           SC_P_SAI1_RXFS                     3
+#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31                          SC_P_SAI1_RXFS                     4
+#define SC_P_SPI2_CS0_ADMA_SPI2_CS0                             SC_P_SPI2_CS0                      0
+#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00                           SC_P_SPI2_CS0                      4
+#define SC_P_SPI2_SDO_ADMA_SPI2_SDO                             SC_P_SPI2_SDO                      0
+#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01                           SC_P_SPI2_SDO                      4
+#define SC_P_SPI2_SDI_ADMA_SPI2_SDI                             SC_P_SPI2_SDI                      0
+#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02                           SC_P_SPI2_SDI                      4
+#define SC_P_SPI2_SCK_ADMA_SPI2_SCK                             SC_P_SPI2_SCK                      0
+#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03                           SC_P_SPI2_SCK                      4
+#define SC_P_SPI0_SCK_ADMA_SPI0_SCK                             SC_P_SPI0_SCK                      0
+#define SC_P_SPI0_SCK_ADMA_SAI0_TXC                             SC_P_SPI0_SCK                      1
+#define SC_P_SPI0_SCK_M40_I2C0_SCL                              SC_P_SPI0_SCK                      2
+#define SC_P_SPI0_SCK_M40_GPIO0_IO00                            SC_P_SPI0_SCK                      3
+#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04                           SC_P_SPI0_SCK                      4
+#define SC_P_SPI0_SDI_ADMA_SPI0_SDI                             SC_P_SPI0_SDI                      0
+#define SC_P_SPI0_SDI_ADMA_SAI0_TXD                             SC_P_SPI0_SDI                      1
+#define SC_P_SPI0_SDI_M40_TPM0_CH0                              SC_P_SPI0_SDI                      2
+#define SC_P_SPI0_SDI_M40_GPIO0_IO02                            SC_P_SPI0_SDI                      3
+#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05                           SC_P_SPI0_SDI                      4
+#define SC_P_SPI0_SDO_ADMA_SPI0_SDO                             SC_P_SPI0_SDO                      0
+#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS                            SC_P_SPI0_SDO                      1
+#define SC_P_SPI0_SDO_M40_I2C0_SDA                              SC_P_SPI0_SDO                      2
+#define SC_P_SPI0_SDO_M40_GPIO0_IO01                            SC_P_SPI0_SDO                      3
+#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06                           SC_P_SPI0_SDO                      4
+#define SC_P_SPI0_CS1_ADMA_SPI0_CS1                             SC_P_SPI0_CS1                      0
+#define SC_P_SPI0_CS1_ADMA_SAI0_RXC                             SC_P_SPI0_CS1                      1
+#define SC_P_SPI0_CS1_ADMA_SAI1_TXD                             SC_P_SPI0_CS1                      2
+#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT                         SC_P_SPI0_CS1                      3
+#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07                           SC_P_SPI0_CS1                      4
+#define SC_P_SPI0_CS0_ADMA_SPI0_CS0                             SC_P_SPI0_CS0                      0
+#define SC_P_SPI0_CS0_ADMA_SAI0_RXD                             SC_P_SPI0_CS0                      1
+#define SC_P_SPI0_CS0_M40_TPM0_CH1                              SC_P_SPI0_CS0                      2
+#define SC_P_SPI0_CS0_M40_GPIO0_IO03                            SC_P_SPI0_CS0                      3
+#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08                           SC_P_SPI0_CS0                      4
+#define SC_P_ADC_IN1_ADMA_ADC_IN1                               SC_P_ADC_IN1                       0
+#define SC_P_ADC_IN1_M40_I2C0_SDA                               SC_P_ADC_IN1                       1
+#define SC_P_ADC_IN1_M40_GPIO0_IO01                             SC_P_ADC_IN1                       2
+#define SC_P_ADC_IN1_LSIO_GPIO1_IO09                            SC_P_ADC_IN1                       4
+#define SC_P_ADC_IN0_ADMA_ADC_IN0                               SC_P_ADC_IN0                       0
+#define SC_P_ADC_IN0_M40_I2C0_SCL                               SC_P_ADC_IN0                       1
+#define SC_P_ADC_IN0_M40_GPIO0_IO00                             SC_P_ADC_IN0                       2
+#define SC_P_ADC_IN0_LSIO_GPIO1_IO10                            SC_P_ADC_IN0                       4
+#define SC_P_ADC_IN3_ADMA_ADC_IN3                               SC_P_ADC_IN3                       0
+#define SC_P_ADC_IN3_M40_UART0_TX                               SC_P_ADC_IN3                       1
+#define SC_P_ADC_IN3_M40_GPIO0_IO03                             SC_P_ADC_IN3                       2
+#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0                         SC_P_ADC_IN3                       3
+#define SC_P_ADC_IN3_LSIO_GPIO1_IO11                            SC_P_ADC_IN3                       4
+#define SC_P_ADC_IN2_ADMA_ADC_IN2                               SC_P_ADC_IN2                       0
+#define SC_P_ADC_IN2_M40_UART0_RX                               SC_P_ADC_IN2                       1
+#define SC_P_ADC_IN2_M40_GPIO0_IO02                             SC_P_ADC_IN2                       2
+#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0                          SC_P_ADC_IN2                       3
+#define SC_P_ADC_IN2_LSIO_GPIO1_IO12                            SC_P_ADC_IN2                       4
+#define SC_P_ADC_IN5_ADMA_ADC_IN5                               SC_P_ADC_IN5                       0
+#define SC_P_ADC_IN5_M40_TPM0_CH1                               SC_P_ADC_IN5                       1
+#define SC_P_ADC_IN5_M40_GPIO0_IO05                             SC_P_ADC_IN5                       2
+#define SC_P_ADC_IN5_LSIO_GPIO1_IO13                            SC_P_ADC_IN5                       4
+#define SC_P_ADC_IN4_ADMA_ADC_IN4                               SC_P_ADC_IN4                       0
+#define SC_P_ADC_IN4_M40_TPM0_CH0                               SC_P_ADC_IN4                       1
+#define SC_P_ADC_IN4_M40_GPIO0_IO04                             SC_P_ADC_IN4                       2
+#define SC_P_ADC_IN4_LSIO_GPIO1_IO14                            SC_P_ADC_IN4                       4
+#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX                       SC_P_FLEXCAN0_RX                   0
+#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC                          SC_P_FLEXCAN0_RX                   1
+#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B                       SC_P_FLEXCAN0_RX                   2
+#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC                          SC_P_FLEXCAN0_RX                   3
+#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15                        SC_P_FLEXCAN0_RX                   4
+#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX                       SC_P_FLEXCAN0_TX                   0
+#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD                          SC_P_FLEXCAN0_TX                   1
+#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B                       SC_P_FLEXCAN0_TX                   2
+#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS                         SC_P_FLEXCAN0_TX                   3
+#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16                        SC_P_FLEXCAN0_TX                   4
+#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX                       SC_P_FLEXCAN1_RX                   0
+#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS                         SC_P_FLEXCAN1_RX                   1
+#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2                           SC_P_FLEXCAN1_RX                   2
+#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD                          SC_P_FLEXCAN1_RX                   3
+#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17                        SC_P_FLEXCAN1_RX                   4
+#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX                       SC_P_FLEXCAN1_TX                   0
+#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC                          SC_P_FLEXCAN1_TX                   1
+#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0                      SC_P_FLEXCAN1_TX                   2
+#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD                          SC_P_FLEXCAN1_TX                   3
+#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18                        SC_P_FLEXCAN1_TX                   4
+#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX                       SC_P_FLEXCAN2_RX                   0
+#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD                          SC_P_FLEXCAN2_RX                   1
+#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX                          SC_P_FLEXCAN2_RX                   2
+#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS                         SC_P_FLEXCAN2_RX                   3
+#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19                        SC_P_FLEXCAN2_RX                   4
+#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX                       SC_P_FLEXCAN2_TX                   0
+#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS                         SC_P_FLEXCAN2_TX                   1
+#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX                          SC_P_FLEXCAN2_TX                   2
+#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC                          SC_P_FLEXCAN2_TX                   3
+#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20                        SC_P_FLEXCAN2_TX                   4
+#define SC_P_UART0_RX_ADMA_UART0_RX                             SC_P_UART0_RX                      0
+#define SC_P_UART0_RX_ADMA_MQS_R                                SC_P_UART0_RX                      1
+#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX                          SC_P_UART0_RX                      2
+#define SC_P_UART0_RX_SCU_UART0_RX                              SC_P_UART0_RX                      3
+#define SC_P_UART0_RX_LSIO_GPIO1_IO21                           SC_P_UART0_RX                      4
+#define SC_P_UART0_TX_ADMA_UART0_TX                             SC_P_UART0_TX                      0
+#define SC_P_UART0_TX_ADMA_MQS_L                                SC_P_UART0_TX                      1
+#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX                          SC_P_UART0_TX                      2
+#define SC_P_UART0_TX_SCU_UART0_TX                              SC_P_UART0_TX                      3
+#define SC_P_UART0_TX_LSIO_GPIO1_IO22                           SC_P_UART0_TX                      4
+#define SC_P_UART2_TX_ADMA_UART2_TX                             SC_P_UART2_TX                      0
+#define SC_P_UART2_TX_ADMA_FTM_CH1                              SC_P_UART2_TX                      1
+#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX                          SC_P_UART2_TX                      2
+#define SC_P_UART2_TX_LSIO_GPIO1_IO23                           SC_P_UART2_TX                      4
+#define SC_P_UART2_RX_ADMA_UART2_RX                             SC_P_UART2_RX                      0
+#define SC_P_UART2_RX_ADMA_FTM_CH0                              SC_P_UART2_RX                      1
+#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX                          SC_P_UART2_RX                      2
+#define SC_P_UART2_RX_LSIO_GPIO1_IO24                           SC_P_UART2_RX                      4
+#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL              SC_P_MIPI_DSI0_I2C0_SCL            0
+#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02            SC_P_MIPI_DSI0_I2C0_SCL            1
+#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25                 SC_P_MIPI_DSI0_I2C0_SCL            4
+#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA              SC_P_MIPI_DSI0_I2C0_SDA            0
+#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03            SC_P_MIPI_DSI0_I2C0_SDA            1
+#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26                 SC_P_MIPI_DSI0_I2C0_SDA            4
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00            SC_P_MIPI_DSI0_GPIO0_00            0
+#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL                   SC_P_MIPI_DSI0_GPIO0_00            1
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT              SC_P_MIPI_DSI0_GPIO0_00            2
+#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27                 SC_P_MIPI_DSI0_GPIO0_00            4
+#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01            SC_P_MIPI_DSI0_GPIO0_01            0
+#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA                   SC_P_MIPI_DSI0_GPIO0_01            1
+#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28                 SC_P_MIPI_DSI0_GPIO0_01            4
+#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL              SC_P_MIPI_DSI1_I2C0_SCL            0
+#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02            SC_P_MIPI_DSI1_I2C0_SCL            1
+#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29                 SC_P_MIPI_DSI1_I2C0_SCL            4
+#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA              SC_P_MIPI_DSI1_I2C0_SDA            0
+#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03            SC_P_MIPI_DSI1_I2C0_SDA            1
+#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30                 SC_P_MIPI_DSI1_I2C0_SDA            4
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00            SC_P_MIPI_DSI1_GPIO0_00            0
+#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL                   SC_P_MIPI_DSI1_GPIO0_00            1
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT              SC_P_MIPI_DSI1_GPIO0_00            2
+#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31                 SC_P_MIPI_DSI1_GPIO0_00            4
+#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01            SC_P_MIPI_DSI1_GPIO0_01            0
+#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA                   SC_P_MIPI_DSI1_GPIO0_01            1
+#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00                 SC_P_MIPI_DSI1_GPIO0_01            4
+#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B                        SC_P_JTAG_TRST_B                   0
+#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT                     SC_P_JTAG_TRST_B                   1
+#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL                      SC_P_PMIC_I2C_SCL                  0
+#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON            SC_P_PMIC_I2C_SCL                  1
+#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01                       SC_P_PMIC_I2C_SCL                  4
+#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA                      SC_P_PMIC_I2C_SDA                  0
+#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON            SC_P_PMIC_I2C_SDA                  1
+#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02                       SC_P_PMIC_I2C_SDA                  4
+#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B                      SC_P_PMIC_INT_B                    0
+#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00                        SC_P_SCU_GPIO0_00                  0
+#define SC_P_SCU_GPIO0_00_SCU_UART0_RX                          SC_P_SCU_GPIO0_00                  1
+#define SC_P_SCU_GPIO0_00_M40_UART0_RX                          SC_P_SCU_GPIO0_00                  2
+#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX                         SC_P_SCU_GPIO0_00                  3
+#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03                       SC_P_SCU_GPIO0_00                  4
+#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01                        SC_P_SCU_GPIO0_01                  0
+#define SC_P_SCU_GPIO0_01_SCU_UART0_TX                          SC_P_SCU_GPIO0_01                  1
+#define SC_P_SCU_GPIO0_01_M40_UART0_TX                          SC_P_SCU_GPIO0_01                  2
+#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX                         SC_P_SCU_GPIO0_01                  3
+#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT                    SC_P_SCU_GPIO0_01                  4
+#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY              SC_P_SCU_PMIC_STANDBY              0
+#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0                  SC_P_SCU_BOOT_MODE0                0
+#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1                  SC_P_SCU_BOOT_MODE1                0
+#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2                  SC_P_SCU_BOOT_MODE2                0
+#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA                    SC_P_SCU_BOOT_MODE2                1
+#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3                  SC_P_SCU_BOOT_MODE3                0
+#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL                    SC_P_SCU_BOOT_MODE3                1
+#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K        SC_P_SCU_BOOT_MODE3                3
+#define SC_P_CSI_D00_CI_PI_D02                                  SC_P_CSI_D00                       0
+#define SC_P_CSI_D00_ADMA_SAI0_RXC                              SC_P_CSI_D00                       2
+#define SC_P_CSI_D01_CI_PI_D03                                  SC_P_CSI_D01                       0
+#define SC_P_CSI_D01_ADMA_SAI0_RXD                              SC_P_CSI_D01                       2
+#define SC_P_CSI_D02_CI_PI_D04                                  SC_P_CSI_D02                       0
+#define SC_P_CSI_D02_ADMA_SAI0_RXFS                             SC_P_CSI_D02                       2
+#define SC_P_CSI_D03_CI_PI_D05                                  SC_P_CSI_D03                       0
+#define SC_P_CSI_D03_ADMA_SAI2_RXC                              SC_P_CSI_D03                       2
+#define SC_P_CSI_D04_CI_PI_D06                                  SC_P_CSI_D04                       0
+#define SC_P_CSI_D04_ADMA_SAI2_RXD                              SC_P_CSI_D04                       2
+#define SC_P_CSI_D05_CI_PI_D07                                  SC_P_CSI_D05                       0
+#define SC_P_CSI_D05_ADMA_SAI2_RXFS                             SC_P_CSI_D05                       2
+#define SC_P_CSI_D06_CI_PI_D08                                  SC_P_CSI_D06                       0
+#define SC_P_CSI_D06_ADMA_SAI3_RXC                              SC_P_CSI_D06                       2
+#define SC_P_CSI_D07_CI_PI_D09                                  SC_P_CSI_D07                       0
+#define SC_P_CSI_D07_ADMA_SAI3_RXD                              SC_P_CSI_D07                       2
+#define SC_P_CSI_HSYNC_CI_PI_HSYNC                              SC_P_CSI_HSYNC                     0
+#define SC_P_CSI_HSYNC_CI_PI_D00                                SC_P_CSI_HSYNC                     1
+#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS                           SC_P_CSI_HSYNC                     2
+#define SC_P_CSI_VSYNC_CI_PI_VSYNC                              SC_P_CSI_VSYNC                     0
+#define SC_P_CSI_VSYNC_CI_PI_D01                                SC_P_CSI_VSYNC                     1
+#define SC_P_CSI_PCLK_CI_PI_PCLK                                SC_P_CSI_PCLK                      0
+#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL                        SC_P_CSI_PCLK                      1
+#define SC_P_CSI_PCLK_ADMA_SPI1_SCK                             SC_P_CSI_PCLK                      3
+#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00                           SC_P_CSI_PCLK                      4
+#define SC_P_CSI_MCLK_CI_PI_MCLK                                SC_P_CSI_MCLK                      0
+#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA                        SC_P_CSI_MCLK                      1
+#define SC_P_CSI_MCLK_ADMA_SPI1_SDO                             SC_P_CSI_MCLK                      3
+#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01                           SC_P_CSI_MCLK                      4
+#define SC_P_CSI_EN_CI_PI_EN                                    SC_P_CSI_EN                        0
+#define SC_P_CSI_EN_CI_PI_I2C_SCL                               SC_P_CSI_EN                        1
+#define SC_P_CSI_EN_ADMA_I2C3_SCL                               SC_P_CSI_EN                        2
+#define SC_P_CSI_EN_ADMA_SPI1_SDI                               SC_P_CSI_EN                        3
+#define SC_P_CSI_EN_LSIO_GPIO3_IO02                             SC_P_CSI_EN                        4
+#define SC_P_CSI_RESET_CI_PI_RESET                              SC_P_CSI_RESET                     0
+#define SC_P_CSI_RESET_CI_PI_I2C_SDA                            SC_P_CSI_RESET                     1
+#define SC_P_CSI_RESET_ADMA_I2C3_SDA                            SC_P_CSI_RESET                     2
+#define SC_P_CSI_RESET_ADMA_SPI1_CS0                            SC_P_CSI_RESET                     3
+#define SC_P_CSI_RESET_LSIO_GPIO3_IO03                          SC_P_CSI_RESET                     4
+#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT          SC_P_MIPI_CSI0_MCLK_OUT            0
+#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04                 SC_P_MIPI_CSI0_MCLK_OUT            4
+#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL              SC_P_MIPI_CSI0_I2C0_SCL            0
+#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02            SC_P_MIPI_CSI0_I2C0_SCL            1
+#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05                 SC_P_MIPI_CSI0_I2C0_SCL            4
+#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA              SC_P_MIPI_CSI0_I2C0_SDA            0
+#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03            SC_P_MIPI_CSI0_I2C0_SDA            1
+#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06                 SC_P_MIPI_CSI0_I2C0_SDA            4
+#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01            SC_P_MIPI_CSI0_GPIO0_01            0
+#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA                   SC_P_MIPI_CSI0_GPIO0_01            1
+#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07                 SC_P_MIPI_CSI0_GPIO0_01            4
+#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00            SC_P_MIPI_CSI0_GPIO0_00            0
+#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL                   SC_P_MIPI_CSI0_GPIO0_00            1
+#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08                 SC_P_MIPI_CSI0_GPIO0_00            4
+#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0                     SC_P_QSPI0A_DATA0                  0
+#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09                       SC_P_QSPI0A_DATA0                  4
+#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1                     SC_P_QSPI0A_DATA1                  0
+#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10                       SC_P_QSPI0A_DATA1                  4
+#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2                     SC_P_QSPI0A_DATA2                  0
+#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11                       SC_P_QSPI0A_DATA2                  4
+#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3                     SC_P_QSPI0A_DATA3                  0
+#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12                       SC_P_QSPI0A_DATA3                  4
+#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS                         SC_P_QSPI0A_DQS                    0
+#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13                         SC_P_QSPI0A_DQS                    4
+#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B                     SC_P_QSPI0A_SS0_B                  0
+#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14                       SC_P_QSPI0A_SS0_B                  4
+#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B                     SC_P_QSPI0A_SS1_B                  0
+#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15                       SC_P_QSPI0A_SS1_B                  4
+#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK                       SC_P_QSPI0A_SCLK                   0
+#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16                        SC_P_QSPI0A_SCLK                   4
+#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK                       SC_P_QSPI0B_SCLK                   0
+#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK                       SC_P_QSPI0B_SCLK                   1
+#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0                         SC_P_QSPI0B_SCLK                   2
+#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17                        SC_P_QSPI0B_SCLK                   4
+#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0                     SC_P_QSPI0B_DATA0                  0
+#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0                     SC_P_QSPI0B_DATA0                  1
+#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1                        SC_P_QSPI0B_DATA0                  2
+#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18                       SC_P_QSPI0B_DATA0                  4
+#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1                     SC_P_QSPI0B_DATA1                  0
+#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1                     SC_P_QSPI0B_DATA1                  1
+#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2                        SC_P_QSPI0B_DATA1                  2
+#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19                       SC_P_QSPI0B_DATA1                  4
+#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2                     SC_P_QSPI0B_DATA2                  0
+#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2                     SC_P_QSPI0B_DATA2                  1
+#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3                        SC_P_QSPI0B_DATA2                  2
+#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20                       SC_P_QSPI0B_DATA2                  4
+#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3                     SC_P_QSPI0B_DATA3                  0
+#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3                     SC_P_QSPI0B_DATA3                  1
+#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0                        SC_P_QSPI0B_DATA3                  2
+#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21                       SC_P_QSPI0B_DATA3                  4
+#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS                         SC_P_QSPI0B_DQS                    0
+#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS                         SC_P_QSPI0B_DQS                    1
+#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1                          SC_P_QSPI0B_DQS                    2
+#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22                         SC_P_QSPI0B_DQS                    4
+#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B                     SC_P_QSPI0B_SS0_B                  0
+#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B                     SC_P_QSPI0B_SS0_B                  1
+#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2                        SC_P_QSPI0B_SS0_B                  2
+#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23                       SC_P_QSPI0B_SS0_B                  4
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B                     SC_P_QSPI0B_SS1_B                  0
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B                     SC_P_QSPI0B_SS1_B                  1
+#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3                        SC_P_QSPI0B_SS1_B                  2
+#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24                       SC_P_QSPI0B_SS1_B                  4
+/*@}*/
+
+#endif /* SC_PADS_H */
+
diff --git a/include/dt-bindings/soc/imx_rsrc.h b/include/dt-bindings/soc/imx_rsrc.h
new file mode 100644
index 0000000000..b2154e9a94
--- /dev/null
+++ b/include/dt-bindings/soc/imx_rsrc.h
@@ -0,0 +1,560 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef DT_BINDINGS_RSCRC_IMX_H
+#define DT_BINDINGS_RSCRC_IMX_H
+
+/*!
+ * These defines are used to indicate a resource. Resources include peripherals
+ * and bus masters (but not memory regions). Note items from list should
+ * never be changed or removed (only added to at the end of the list).
+ */
+#define SC_R_A53                        0
+#define SC_R_A53_0                      1
+#define SC_R_A53_1                      2
+#define SC_R_A53_2                      3
+#define SC_R_A53_3                      4
+#define SC_R_A72                        5
+#define SC_R_A72_0                      6
+#define SC_R_A72_1                      7
+#define SC_R_A72_2                      8
+#define SC_R_A72_3                      9
+#define SC_R_CCI                        10
+#define SC_R_DB                         11
+#define SC_R_DRC_0                      12
+#define SC_R_DRC_1                      13
+#define SC_R_GIC_SMMU                   14
+#define SC_R_IRQSTR_M4_0                15
+#define SC_R_IRQSTR_M4_1                16
+#define SC_R_SMMU                       17
+#define SC_R_GIC                        18
+#define SC_R_DC_0_BLIT0                 19
+#define SC_R_DC_0_BLIT1                 20
+#define SC_R_DC_0_BLIT2                 21
+#define SC_R_DC_0_BLIT_OUT              22
+#define SC_R_DC_0_CAPTURE0              23
+#define SC_R_DC_0_CAPTURE1              24
+#define SC_R_DC_0_WARP                  25
+#define SC_R_DC_0_INTEGRAL0             26
+#define SC_R_DC_0_INTEGRAL1             27
+#define SC_R_DC_0_VIDEO0                28
+#define SC_R_DC_0_VIDEO1                29
+#define SC_R_DC_0_FRAC0                 30
+#define SC_R_DC_0_FRAC1                 31
+#define SC_R_DC_0                       32
+#define SC_R_GPU_2_PID0                 33
+#define SC_R_DC_0_PLL_0                 34
+#define SC_R_DC_0_PLL_1                 35
+#define SC_R_DC_1_BLIT0                 36
+#define SC_R_DC_1_BLIT1                 37
+#define SC_R_DC_1_BLIT2                 38
+#define SC_R_DC_1_BLIT_OUT              39
+#define SC_R_DC_1_CAPTURE0              40
+#define SC_R_DC_1_CAPTURE1              41
+#define SC_R_DC_1_WARP                  42
+#define SC_R_DC_1_INTEGRAL0             43
+#define SC_R_DC_1_INTEGRAL1             44
+#define SC_R_DC_1_VIDEO0                45
+#define SC_R_DC_1_VIDEO1                46
+#define SC_R_DC_1_FRAC0                 47
+#define SC_R_DC_1_FRAC1                 48
+#define SC_R_DC_1                       49
+#define SC_R_GPU_3_PID0                 50
+#define SC_R_DC_1_PLL_0                 51
+#define SC_R_DC_1_PLL_1                 52
+#define SC_R_SPI_0                      53
+#define SC_R_SPI_1                      54
+#define SC_R_SPI_2                      55
+#define SC_R_SPI_3                      56
+#define SC_R_UART_0                     57
+#define SC_R_UART_1                     58
+#define SC_R_UART_2                     59
+#define SC_R_UART_3                     60
+#define SC_R_UART_4                     61
+#define SC_R_EMVSIM_0                   62
+#define SC_R_EMVSIM_1                   63
+#define SC_R_DMA_0_CH0                  64
+#define SC_R_DMA_0_CH1                  65
+#define SC_R_DMA_0_CH2                  66
+#define SC_R_DMA_0_CH3                  67
+#define SC_R_DMA_0_CH4                  68
+#define SC_R_DMA_0_CH5                  69
+#define SC_R_DMA_0_CH6                  70
+#define SC_R_DMA_0_CH7                  71
+#define SC_R_DMA_0_CH8                  72
+#define SC_R_DMA_0_CH9                  73
+#define SC_R_DMA_0_CH10                 74
+#define SC_R_DMA_0_CH11                 75
+#define SC_R_DMA_0_CH12                 76
+#define SC_R_DMA_0_CH13                 77
+#define SC_R_DMA_0_CH14                 78
+#define SC_R_DMA_0_CH15                 79
+#define SC_R_DMA_0_CH16                 80
+#define SC_R_DMA_0_CH17                 81
+#define SC_R_DMA_0_CH18                 82
+#define SC_R_DMA_0_CH19                 83
+#define SC_R_DMA_0_CH20                 84
+#define SC_R_DMA_0_CH21                 85
+#define SC_R_DMA_0_CH22                 86
+#define SC_R_DMA_0_CH23                 87
+#define SC_R_DMA_0_CH24                 88
+#define SC_R_DMA_0_CH25                 89
+#define SC_R_DMA_0_CH26                 90
+#define SC_R_DMA_0_CH27                 91
+#define SC_R_DMA_0_CH28                 92
+#define SC_R_DMA_0_CH29                 93
+#define SC_R_DMA_0_CH30                 94
+#define SC_R_DMA_0_CH31                 95
+#define SC_R_I2C_0                      96
+#define SC_R_I2C_1                      97
+#define SC_R_I2C_2                      98
+#define SC_R_I2C_3                      99
+#define SC_R_I2C_4                      100
+#define SC_R_ADC_0                      101
+#define SC_R_ADC_1                      102
+#define SC_R_FTM_0                      103
+#define SC_R_FTM_1                      104
+#define SC_R_CAN_0                      105
+#define SC_R_CAN_1                      106
+#define SC_R_CAN_2                      107
+#define SC_R_DMA_1_CH0                  108
+#define SC_R_DMA_1_CH1                  109
+#define SC_R_DMA_1_CH2                  110
+#define SC_R_DMA_1_CH3                  111
+#define SC_R_DMA_1_CH4                  112
+#define SC_R_DMA_1_CH5                  113
+#define SC_R_DMA_1_CH6                  114
+#define SC_R_DMA_1_CH7                  115
+#define SC_R_DMA_1_CH8                  116
+#define SC_R_DMA_1_CH9                  117
+#define SC_R_DMA_1_CH10                 118
+#define SC_R_DMA_1_CH11                 119
+#define SC_R_DMA_1_CH12                 120
+#define SC_R_DMA_1_CH13                 121
+#define SC_R_DMA_1_CH14                 122
+#define SC_R_DMA_1_CH15                 123
+#define SC_R_DMA_1_CH16                 124
+#define SC_R_DMA_1_CH17                 125
+#define SC_R_DMA_1_CH18                 126
+#define SC_R_DMA_1_CH19                 127
+#define SC_R_DMA_1_CH20                 128
+#define SC_R_DMA_1_CH21                 129
+#define SC_R_DMA_1_CH22                 130
+#define SC_R_DMA_1_CH23                 131
+#define SC_R_DMA_1_CH24                 132
+#define SC_R_DMA_1_CH25                 133
+#define SC_R_DMA_1_CH26                 134
+#define SC_R_DMA_1_CH27                 135
+#define SC_R_DMA_1_CH28                 136
+#define SC_R_DMA_1_CH29                 137
+#define SC_R_DMA_1_CH30                 138
+#define SC_R_DMA_1_CH31                 139
+#define SC_R_UNUSED1                    140
+#define SC_R_UNUSED2                    141
+#define SC_R_UNUSED3                    142
+#define SC_R_UNUSED4                    143
+#define SC_R_GPU_0_PID0                 144
+#define SC_R_GPU_0_PID1                 145
+#define SC_R_GPU_0_PID2                 146
+#define SC_R_GPU_0_PID3                 147
+#define SC_R_GPU_1_PID0                 148
+#define SC_R_GPU_1_PID1                 149
+#define SC_R_GPU_1_PID2                 150
+#define SC_R_GPU_1_PID3                 151
+#define SC_R_PCIE_A                     152
+#define SC_R_SERDES_0                   153
+#define SC_R_MATCH_0                    154
+#define SC_R_MATCH_1                    155
+#define SC_R_MATCH_2                    156
+#define SC_R_MATCH_3                    157
+#define SC_R_MATCH_4                    158
+#define SC_R_MATCH_5                    159
+#define SC_R_MATCH_6                    160
+#define SC_R_MATCH_7                    161
+#define SC_R_MATCH_8                    162
+#define SC_R_MATCH_9                    163
+#define SC_R_MATCH_10                   164
+#define SC_R_MATCH_11                   165
+#define SC_R_MATCH_12                   166
+#define SC_R_MATCH_13                   167
+#define SC_R_MATCH_14                   168
+#define SC_R_PCIE_B                     169
+#define SC_R_SATA_0                     170
+#define SC_R_SERDES_1                   171
+#define SC_R_HSIO_GPIO                  172
+#define SC_R_MATCH_15                   173
+#define SC_R_MATCH_16                   174
+#define SC_R_MATCH_17                   175
+#define SC_R_MATCH_18                   176
+#define SC_R_MATCH_19                   177
+#define SC_R_MATCH_20                   178
+#define SC_R_MATCH_21                   179
+#define SC_R_MATCH_22                   180
+#define SC_R_MATCH_23                   181
+#define SC_R_MATCH_24                   182
+#define SC_R_MATCH_25                   183
+#define SC_R_MATCH_26                   184
+#define SC_R_MATCH_27                   185
+#define SC_R_MATCH_28                   186
+#define SC_R_LCD_0                      187
+#define SC_R_LCD_0_PWM_0                188
+#define SC_R_LCD_0_I2C_0                189
+#define SC_R_LCD_0_I2C_1                190
+#define SC_R_PWM_0                      191
+#define SC_R_PWM_1                      192
+#define SC_R_PWM_2                      193
+#define SC_R_PWM_3                      194
+#define SC_R_PWM_4                      195
+#define SC_R_PWM_5                      196
+#define SC_R_PWM_6                      197
+#define SC_R_PWM_7                      198
+#define SC_R_GPIO_0                     199
+#define SC_R_GPIO_1                     200
+#define SC_R_GPIO_2                     201
+#define SC_R_GPIO_3                     202
+#define SC_R_GPIO_4                     203
+#define SC_R_GPIO_5                     204
+#define SC_R_GPIO_6                     205
+#define SC_R_GPIO_7                     206
+#define SC_R_GPT_0                      207
+#define SC_R_GPT_1                      208
+#define SC_R_GPT_2                      209
+#define SC_R_GPT_3                      210
+#define SC_R_GPT_4                      211
+#define SC_R_KPP                        212
+#define SC_R_MU_0A                      213
+#define SC_R_MU_1A                      214
+#define SC_R_MU_2A                      215
+#define SC_R_MU_3A                      216
+#define SC_R_MU_4A                      217
+#define SC_R_MU_5A                      218
+#define SC_R_MU_6A                      219
+#define SC_R_MU_7A                      220
+#define SC_R_MU_8A                      221
+#define SC_R_MU_9A                      222
+#define SC_R_MU_10A                     223
+#define SC_R_MU_11A                     224
+#define SC_R_MU_12A                     225
+#define SC_R_MU_13A                     226
+#define SC_R_MU_5B                      227
+#define SC_R_MU_6B                      228
+#define SC_R_MU_7B                      229
+#define SC_R_MU_8B                      230
+#define SC_R_MU_9B                      231
+#define SC_R_MU_10B                     232
+#define SC_R_MU_11B                     233
+#define SC_R_MU_12B                     234
+#define SC_R_MU_13B                     235
+#define SC_R_ROM_0                      236
+#define SC_R_FSPI_0                     237
+#define SC_R_FSPI_1                     238
+#define SC_R_IEE                        239
+#define SC_R_IEE_R0                     240
+#define SC_R_IEE_R1                     241
+#define SC_R_IEE_R2                     242
+#define SC_R_IEE_R3                     243
+#define SC_R_IEE_R4                     244
+#define SC_R_IEE_R5                     245
+#define SC_R_IEE_R6                     246
+#define SC_R_IEE_R7                     247
+#define SC_R_SDHC_0                     248
+#define SC_R_SDHC_1                     249
+#define SC_R_SDHC_2                     250
+#define SC_R_ENET_0                     251
+#define SC_R_ENET_1                     252
+#define SC_R_MLB_0                      253
+#define SC_R_DMA_2_CH0                  254
+#define SC_R_DMA_2_CH1                  255
+#define SC_R_DMA_2_CH2                  256
+#define SC_R_DMA_2_CH3                  257
+#define SC_R_DMA_2_CH4                  258
+#define SC_R_USB_0                      259
+#define SC_R_USB_1                      260
+#define SC_R_USB_0_PHY                  261
+#define SC_R_USB_2                      262
+#define SC_R_USB_2_PHY                  263
+#define SC_R_DTCP                       264
+#define SC_R_NAND                       265
+#define SC_R_LVDS_0                     266
+#define SC_R_LVDS_0_PWM_0               267
+#define SC_R_LVDS_0_I2C_0               268
+#define SC_R_LVDS_0_I2C_1               269
+#define SC_R_LVDS_1                     270
+#define SC_R_LVDS_1_PWM_0               271
+#define SC_R_LVDS_1_I2C_0               272
+#define SC_R_LVDS_1_I2C_1               273
+#define SC_R_LVDS_2                     274
+#define SC_R_LVDS_2_PWM_0               275
+#define SC_R_LVDS_2_I2C_0               276
+#define SC_R_LVDS_2_I2C_1               277
+#define SC_R_M4_0_PID0                  278
+#define SC_R_M4_0_PID1                  279
+#define SC_R_M4_0_PID2                  280
+#define SC_R_M4_0_PID3                  281
+#define SC_R_M4_0_PID4                  282
+#define SC_R_M4_0_RGPIO                 283
+#define SC_R_M4_0_SEMA42                284
+#define SC_R_M4_0_TPM                   285
+#define SC_R_M4_0_PIT                   286
+#define SC_R_M4_0_UART                  287
+#define SC_R_M4_0_I2C                   288
+#define SC_R_M4_0_INTMUX                289
+#define SC_R_M4_0_SIM                   290
+#define SC_R_M4_0_WDOG                  291
+#define SC_R_M4_0_MU_0B                 292
+#define SC_R_M4_0_MU_0A0                293
+#define SC_R_M4_0_MU_0A1                294
+#define SC_R_M4_0_MU_0A2                295
+#define SC_R_M4_0_MU_0A3                296
+#define SC_R_M4_0_MU_1A                 297
+#define SC_R_M4_1_PID0                  298
+#define SC_R_M4_1_PID1                  299
+#define SC_R_M4_1_PID2                  300
+#define SC_R_M4_1_PID3                  301
+#define SC_R_M4_1_PID4                  302
+#define SC_R_M4_1_RGPIO                 303
+#define SC_R_M4_1_SEMA42                304
+#define SC_R_M4_1_TPM                   305
+#define SC_R_M4_1_PIT                   306
+#define SC_R_M4_1_UART                  307
+#define SC_R_M4_1_I2C                   308
+#define SC_R_M4_1_INTMUX                309
+#define SC_R_M4_1_SIM                   310
+#define SC_R_M4_1_WDOG                  311
+#define SC_R_M4_1_MU_0B                 312
+#define SC_R_M4_1_MU_0A0                313
+#define SC_R_M4_1_MU_0A1                314
+#define SC_R_M4_1_MU_0A2                315
+#define SC_R_M4_1_MU_0A3                316
+#define SC_R_M4_1_MU_1A                 317
+#define SC_R_SAI_0                      318
+#define SC_R_SAI_1                      319
+#define SC_R_SAI_2                      320
+#define SC_R_IRQSTR_SCU2                321
+#define SC_R_IRQSTR_DSP                 322
+#define SC_R_UNUSED5                    323
+#define SC_R_OCRAM                      324
+#define SC_R_AUDIO_PLL_0                325
+#define SC_R_PI_0                       326
+#define SC_R_PI_0_PWM_0                 327
+#define SC_R_PI_0_PWM_1                 328
+#define SC_R_PI_0_I2C_0                 329
+#define SC_R_PI_0_PLL                   330
+#define SC_R_PI_1                       331
+#define SC_R_PI_1_PWM_0                 332
+#define SC_R_PI_1_PWM_1                 333
+#define SC_R_PI_1_I2C_0                 334
+#define SC_R_PI_1_PLL                   335
+#define SC_R_SC_PID0                    336
+#define SC_R_SC_PID1                    337
+#define SC_R_SC_PID2                    338
+#define SC_R_SC_PID3                    339
+#define SC_R_SC_PID4                    340
+#define SC_R_SC_SEMA42                  341
+#define SC_R_SC_TPM                     342
+#define SC_R_SC_PIT                     343
+#define SC_R_SC_UART                    344
+#define SC_R_SC_I2C                     345
+#define SC_R_SC_MU_0B                   346
+#define SC_R_SC_MU_0A0                  347
+#define SC_R_SC_MU_0A1                  348
+#define SC_R_SC_MU_0A2                  349
+#define SC_R_SC_MU_0A3                  350
+#define SC_R_SC_MU_1A                   351
+#define SC_R_SYSCNT_RD                  352
+#define SC_R_SYSCNT_CMP                 353
+#define SC_R_DEBUG                      354
+#define SC_R_SYSTEM                     355
+#define SC_R_SNVS                       356
+#define SC_R_OTP                        357
+#define SC_R_VPU_PID0                   358
+#define SC_R_VPU_PID1                   359
+#define SC_R_VPU_PID2                   360
+#define SC_R_VPU_PID3                   361
+#define SC_R_VPU_PID4                   362
+#define SC_R_VPU_PID5                   363
+#define SC_R_VPU_PID6                   364
+#define SC_R_VPU_PID7                   365
+#define SC_R_VPU_UART                   366
+#define SC_R_VPUCORE                    367
+#define SC_R_VPUCORE_0                  368
+#define SC_R_VPUCORE_1                  369
+#define SC_R_VPUCORE_2                  370
+#define SC_R_VPUCORE_3                  371
+#define SC_R_DMA_4_CH0                  372
+#define SC_R_DMA_4_CH1                  373
+#define SC_R_DMA_4_CH2                  374
+#define SC_R_DMA_4_CH3                  375
+#define SC_R_DMA_4_CH4                  376
+#define SC_R_ISI_CH0                    377
+#define SC_R_ISI_CH1                    378
+#define SC_R_ISI_CH2                    379
+#define SC_R_ISI_CH3                    380
+#define SC_R_ISI_CH4                    381
+#define SC_R_ISI_CH5                    382
+#define SC_R_ISI_CH6                    383
+#define SC_R_ISI_CH7                    384
+#define SC_R_MJPEG_DEC_S0               385
+#define SC_R_MJPEG_DEC_S1               386
+#define SC_R_MJPEG_DEC_S2               387
+#define SC_R_MJPEG_DEC_S3               388
+#define SC_R_MJPEG_ENC_S0               389
+#define SC_R_MJPEG_ENC_S1               390
+#define SC_R_MJPEG_ENC_S2               391
+#define SC_R_MJPEG_ENC_S3               392
+#define SC_R_MIPI_0                     393
+#define SC_R_MIPI_0_PWM_0               394
+#define SC_R_MIPI_0_I2C_0               395
+#define SC_R_MIPI_0_I2C_1               396
+#define SC_R_MIPI_1                     397
+#define SC_R_MIPI_1_PWM_0               398
+#define SC_R_MIPI_1_I2C_0               399
+#define SC_R_MIPI_1_I2C_1               400
+#define SC_R_CSI_0                      401
+#define SC_R_CSI_0_PWM_0                402
+#define SC_R_CSI_0_I2C_0                403
+#define SC_R_CSI_1                      404
+#define SC_R_CSI_1_PWM_0                405
+#define SC_R_CSI_1_I2C_0                406
+#define SC_R_HDMI                       407
+#define SC_R_HDMI_I2S                   408
+#define SC_R_HDMI_I2C_0                 409
+#define SC_R_HDMI_PLL_0                 410
+#define SC_R_HDMI_RX                    411
+#define SC_R_HDMI_RX_BYPASS             412
+#define SC_R_HDMI_RX_I2C_0              413
+#define SC_R_ASRC_0                     414
+#define SC_R_ESAI_0                     415
+#define SC_R_SPDIF_0                    416
+#define SC_R_SPDIF_1                    417
+#define SC_R_SAI_3                      418
+#define SC_R_SAI_4                      419
+#define SC_R_SAI_5                      420
+#define SC_R_GPT_5                      421
+#define SC_R_GPT_6                      422
+#define SC_R_GPT_7                      423
+#define SC_R_GPT_8                      424
+#define SC_R_GPT_9                      425
+#define SC_R_GPT_10                     426
+#define SC_R_DMA_2_CH5                  427
+#define SC_R_DMA_2_CH6                  428
+#define SC_R_DMA_2_CH7                  429
+#define SC_R_DMA_2_CH8                  430
+#define SC_R_DMA_2_CH9                  431
+#define SC_R_DMA_2_CH10                 432
+#define SC_R_DMA_2_CH11                 433
+#define SC_R_DMA_2_CH12                 434
+#define SC_R_DMA_2_CH13                 435
+#define SC_R_DMA_2_CH14                 436
+#define SC_R_DMA_2_CH15                 437
+#define SC_R_DMA_2_CH16                 438
+#define SC_R_DMA_2_CH17                 439
+#define SC_R_DMA_2_CH18                 440
+#define SC_R_DMA_2_CH19                 441
+#define SC_R_DMA_2_CH20                 442
+#define SC_R_DMA_2_CH21                 443
+#define SC_R_DMA_2_CH22                 444
+#define SC_R_DMA_2_CH23                 445
+#define SC_R_DMA_2_CH24                 446
+#define SC_R_DMA_2_CH25                 447
+#define SC_R_DMA_2_CH26                 448
+#define SC_R_DMA_2_CH27                 449
+#define SC_R_DMA_2_CH28                 450
+#define SC_R_DMA_2_CH29                 451
+#define SC_R_DMA_2_CH30                 452
+#define SC_R_DMA_2_CH31                 453
+#define SC_R_ASRC_1                     454
+#define SC_R_ESAI_1                     455
+#define SC_R_SAI_6                      456
+#define SC_R_SAI_7                      457
+#define SC_R_AMIX                       458
+#define SC_R_MQS_0                      459
+#define SC_R_DMA_3_CH0                  460
+#define SC_R_DMA_3_CH1                  461
+#define SC_R_DMA_3_CH2                  462
+#define SC_R_DMA_3_CH3                  463
+#define SC_R_DMA_3_CH4                  464
+#define SC_R_DMA_3_CH5                  465
+#define SC_R_DMA_3_CH6                  466
+#define SC_R_DMA_3_CH7                  467
+#define SC_R_DMA_3_CH8                  468
+#define SC_R_DMA_3_CH9                  469
+#define SC_R_DMA_3_CH10                 470
+#define SC_R_DMA_3_CH11                 471
+#define SC_R_DMA_3_CH12                 472
+#define SC_R_DMA_3_CH13                 473
+#define SC_R_DMA_3_CH14                 474
+#define SC_R_DMA_3_CH15                 475
+#define SC_R_DMA_3_CH16                 476
+#define SC_R_DMA_3_CH17                 477
+#define SC_R_DMA_3_CH18                 478
+#define SC_R_DMA_3_CH19                 479
+#define SC_R_DMA_3_CH20                 480
+#define SC_R_DMA_3_CH21                 481
+#define SC_R_DMA_3_CH22                 482
+#define SC_R_DMA_3_CH23                 483
+#define SC_R_DMA_3_CH24                 484
+#define SC_R_DMA_3_CH25                 485
+#define SC_R_DMA_3_CH26                 486
+#define SC_R_DMA_3_CH27                 487
+#define SC_R_DMA_3_CH28                 488
+#define SC_R_DMA_3_CH29                 489
+#define SC_R_DMA_3_CH30                 490
+#define SC_R_DMA_3_CH31                 491
+#define SC_R_AUDIO_PLL_1                492
+#define SC_R_AUDIO_CLK_0                493
+#define SC_R_AUDIO_CLK_1                494
+#define SC_R_MCLK_OUT_0                 495
+#define SC_R_MCLK_OUT_1                 496
+#define SC_R_PMIC_0                     497
+#define SC_R_PMIC_1                     498
+#define SC_R_SECO                       499
+#define SC_R_CAAM_JR1                   500
+#define SC_R_CAAM_JR2                   501
+#define SC_R_CAAM_JR3                   502
+#define SC_R_SECO_MU_2                  503
+#define SC_R_SECO_MU_3                  504
+#define SC_R_SECO_MU_4                  505
+#define SC_R_HDMI_RX_PWM_0              506
+#define SC_R_A35                        507
+#define SC_R_A35_0                      508
+#define SC_R_A35_1                      509
+#define SC_R_A35_2                      510
+#define SC_R_A35_3                      511
+#define SC_R_DSP                        512
+#define SC_R_DSP_RAM                    513
+#define SC_R_CAAM_JR1_OUT               514
+#define SC_R_CAAM_JR2_OUT               515
+#define SC_R_CAAM_JR3_OUT               516
+#define SC_R_VPU_DEC_0                  517
+#define SC_R_VPU_ENC_0                  518
+#define SC_R_CAAM_JR0                   519
+#define SC_R_CAAM_JR0_OUT               520
+#define SC_R_PMIC_2                     521
+#define SC_R_DBLOGIC                    522
+#define SC_R_HDMI_PLL_1                 523
+#define SC_R_BOARD_R0                   524
+#define SC_R_BOARD_R1                   525
+#define SC_R_BOARD_R2                   526
+#define SC_R_BOARD_R3                   527
+#define SC_R_BOARD_R4                   528
+#define SC_R_BOARD_R5                   529
+#define SC_R_BOARD_R6                   530
+#define SC_R_BOARD_R7                   531
+#define SC_R_MJPEG_DEC_MP               532
+#define SC_R_MJPEG_ENC_MP               533
+#define SC_R_VPU_TS_0                   534
+#define SC_R_VPU_MU_0                   535
+#define SC_R_VPU_MU_1                   536
+#define SC_R_VPU_MU_2                   537
+#define SC_R_VPU_MU_3                   538
+#define SC_R_VPU_ENC_1                  539
+#define SC_R_VPU                        540
+#define SC_R_LAST                       541
+
+#endif /* DT_BINDINGS_RSCRC_IMX_H */
+
-- 
2.14.1



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