[U-Boot] [PATCH 44/93] arm: Remove devkit8000 board
Simon Glass
sjg at chromium.org
Mon Nov 19 15:53:24 UTC 2018
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg at chromium.org>
---
arch/arm/mach-omap2/omap3/Kconfig | 1 -
board/timll/devkit8000/Kconfig | 12 -
board/timll/devkit8000/MAINTAINERS | 6 -
board/timll/devkit8000/Makefile | 9 -
board/timll/devkit8000/README | 15 --
board/timll/devkit8000/devkit8000.c | 206 ----------------
board/timll/devkit8000/devkit8000.h | 359 ----------------------------
configs/devkit8000_defconfig | 34 ---
include/configs/devkit8000.h | 190 ---------------
9 files changed, 832 deletions(-)
delete mode 100644 board/timll/devkit8000/Kconfig
delete mode 100644 board/timll/devkit8000/MAINTAINERS
delete mode 100644 board/timll/devkit8000/Makefile
delete mode 100644 board/timll/devkit8000/README
delete mode 100644 board/timll/devkit8000/devkit8000.c
delete mode 100644 board/timll/devkit8000/devkit8000.h
delete mode 100644 configs/devkit8000_defconfig
delete mode 100644 include/configs/devkit8000.h
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index d2d4d2b3809..edd5e3f255b 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -198,7 +198,6 @@ source "board/teejet/mt_ventoux/Kconfig"
source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
source "board/compulab/cm_t3517/Kconfig"
-source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/8dtech/eco5pk/Kconfig"
diff --git a/board/timll/devkit8000/Kconfig b/board/timll/devkit8000/Kconfig
deleted file mode 100644
index 3c63ced9a1a..00000000000
--- a/board/timll/devkit8000/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DEVKIT8000
-
-config SYS_BOARD
- default "devkit8000"
-
-config SYS_VENDOR
- default "timll"
-
-config SYS_CONFIG_NAME
- default "devkit8000"
-
-endif
diff --git a/board/timll/devkit8000/MAINTAINERS b/board/timll/devkit8000/MAINTAINERS
deleted file mode 100644
index c490757d684..00000000000
--- a/board/timll/devkit8000/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DEVKIT8000 BOARD
-M: Thomas Weber <weber at corscience.de>
-S: Maintained
-F: board/timll/devkit8000/
-F: include/configs/devkit8000.h
-F: configs/devkit8000_defconfig
diff --git a/board/timll/devkit8000/Makefile b/board/timll/devkit8000/Makefile
deleted file mode 100644
index 4d681701cf3..00000000000
--- a/board/timll/devkit8000/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2009
-# Frederik Kriewitz <frederik at kriewitz.eu>
-
-obj-y := devkit8000.o
diff --git a/board/timll/devkit8000/README b/board/timll/devkit8000/README
deleted file mode 100644
index 609bf51aee2..00000000000
--- a/board/timll/devkit8000/README
+++ /dev/null
@@ -1,15 +0,0 @@
-DevKit8000
-==========
-
-The OMAP3 DevKit8000 from Embest/Timll is a clone of the OMAP3 beagle board
-with Ethernet and Touch Screen controller on board.
-
-For more information go to:
-http://www.embedinfo.com/English/Product/devkit8000.asp
-
-There's no real MAC address available.
-If ethaddr is not set, 5 Bytes of the OMAP Die ID will be used.
-
-Build:
-make devkit8000_config
-make
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
deleted file mode 100644
index 50b70a501cc..00000000000
--- a/board/timll/devkit8000/devkit8000.c
+++ /dev/null
@@ -1,206 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Sunil Kumar <sunilsaini05 at gmail.com>
- * Shashi Ranjan <shashiranjanmca05 at gmail.com>
- *
- * (C) Copyright 2009
- * Frederik Kriewitz <frederik at kriewitz.eu>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2 at ti.com>
- * Syed Mohammed Khasim <khasim at ti.com>
- *
- */
-#include <common.h>
-#include <dm.h>
-#include <environment.h>
-#include <ns16550.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/mach-types.h>
-#include "devkit8000.h"
-#include <asm/gpio.h>
-#ifdef CONFIG_DRIVER_DM9000
-#include <net.h>
-#include <netdev.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static u32 gpmc_net_config[GPMC_MAX_REG] = {
- NET_GPMC_CONFIG1,
- NET_GPMC_CONFIG2,
- NET_GPMC_CONFIG3,
- NET_GPMC_CONFIG4,
- NET_GPMC_CONFIG5,
- NET_GPMC_CONFIG6,
- 0
-};
-
-static const struct ns16550_platdata devkit8000_serial = {
- .base = OMAP34XX_UART3,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(devkit8000_uart) = {
- "ns16550_serial",
- &devkit8000_serial
-};
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-/* Configure GPMC registers for DM9000 */
-static void gpmc_dm9000_config(void)
-{
- enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
- CONFIG_DM9000_BASE, GPMC_SIZE_16M);
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
- struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
-#ifdef CONFIG_DRIVER_DM9000
- uchar enetaddr[6];
- u32 die_id_0;
-#endif
-
- twl4030_power_init();
-#ifdef CONFIG_TWL4030_LED
- twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
-#endif
-
-#ifdef CONFIG_DRIVER_DM9000
- /* Configure GPMC registers for DM9000 */
- enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
- CONFIG_DM9000_BASE, GPMC_SIZE_16M);
-
- /* Use OMAP DIE_ID as MAC address */
- if (!eth_env_get_enetaddr("ethaddr", enetaddr)) {
- printf("ethaddr not set, using Die ID\n");
- die_id_0 = readl(&id_base->die_id_0);
- enetaddr[0] = 0x02; /* locally administered */
- enetaddr[1] = readl(&id_base->die_id_1) & 0xff;
- enetaddr[2] = (die_id_0 & 0xff000000) >> 24;
- enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16;
- enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8;
- enetaddr[5] = (die_id_0 & 0x000000ff);
- eth_env_set_enetaddr("ethaddr", enetaddr);
- }
-#endif
-
- omap_die_id_display();
-
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_DEVKIT8000();
-}
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_MMC)
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
-
-#if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
-/*
- * Routine: board_eth_init
- * Description: Setting up the Ethernet hardware.
- */
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
-
-#ifdef CONFIG_SPL_OS_BOOT
-/*
- * Do board specific preparation before SPL
- * Linux boot
- */
-void spl_board_prepare_for_linux(void)
-{
- gpmc_dm9000_config();
-}
-
-/*
- * devkit8000 specific implementation of spl_start_uboot()
- *
- * RETURN
- * 0 if the button is not pressed
- * 1 if the button is pressed
- */
-int spl_start_uboot(void)
-{
- int val = 0;
- if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
- gpio_direction_input(SPL_OS_BOOT_KEY);
- val = gpio_get_value(SPL_OS_BOOT_KEY);
- gpio_free(SPL_OS_BOOT_KEY);
- }
- return !val;
-}
-#endif
-
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on the first bank. This
- * provides the timing values back to the function that configures
- * the memory. We have either one or two banks of 128MB DDR.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- /* General SDRC config */
- timings->mcfg = MICRON_V_MCFG_165(128 << 20);
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
-
- /* AC timings */
- timings->ctrla = MICRON_V_ACTIMA_165;
- timings->ctrlb = MICRON_V_ACTIMB_165;
-
- timings->mr = MICRON_V_MR_165;
-}
diff --git a/board/timll/devkit8000/devkit8000.h b/board/timll/devkit8000/devkit8000.h
deleted file mode 100644
index c8d57d167eb..00000000000
--- a/board/timll/devkit8000/devkit8000.h
+++ /dev/null
@@ -1,359 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008
- * Dirk Behme <dirk.behme at gmail.com>
- *
- * (C) Copyright 2009
- * Frederik Kriewitz <frederik at kriewitz.eu>
- */
-#ifndef _DEVKIT8000_H_
-#define _DEVKIT8000_H_
-
-const omap3_sysinfo sysinfo = {
- DDR_STACKED,
- "OMAP3 DevKit8000",
- "NAND",
-};
-
-/* GPIO used to select between U-Boot and kernel */
-#define SPL_OS_BOOT_KEY 26
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-
-#define MUX_DEVKIT8000() \
- /* SDRC */\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /* GPMC */\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0 NAND*/\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
- MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6 DM9000*/\
- MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
- /* DSS */\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
- /* CAMERA */\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
- /* Audio Interface */\
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
- /* MMC Slot */\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
- /* Expansion Header */\
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
- MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\
- MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\
- MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\
- MUX_VAL(CP(UART2_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_144*/\
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_145*/\
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M4)) /*GPIO_146*/\
- MUX_VAL(CP(UART2_RX), (IDIS | PTD | DIS | M4)) /*GPIO_147*/\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*GPIO_148*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
- MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*GPIO_151*/\
- MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*GPIO_152*/\
- MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*GPIO_153*/\
- MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*GPIO_154*/\
- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*GPIO_155*/\
- MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
- MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*GPIO_160*/\
- MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
- /* Serial Interface */\
- MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | EN | M4)) /*GPIO_163 - LED2*/\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)) /*GPIO_164 - LED3*/\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
- /* Host USB0 */\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
- MUX_VAL(CP(I2C2_SCL), (IDIS | PTU | DIS | M4)) /*GPIO_168*/\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | DIS | M0)) /*I2C4_SDA*/\
- MUX_VAL(CP(HDQ_SIO), (IDIS | PTD | DIS | M4)) /*GPIO_170*/\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M4)) /*GPIO_171*/\
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M4)) /*GPIO_172*/\
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*MCSPI1_SOMI*/\
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | DIS | M0)) /*MCSPI1_CS0*/\
- MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | DIS | M0)) /*MCSPI1_CS1*/\
- MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
- /* USB EHCI (port 2) */\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*HSUSB2_DATA2*/\
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA7*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA4*/\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA5*/\
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*HSUSB2_DATA6*/\
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*HSUSB2_DATA3*/\
- /*Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | EN | M0)) /*SYS_CLKOUT1*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | EN | M4)) /*GPIO_186 - LED1*/\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB1_STP*/\
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | EN | M3)) /*HSUSB1_CLK*/\
- MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA0*/\
- MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA1*/\
- MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA2*/\
- MUX_VAL(CP(ETK_D3_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA7*/\
- MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA4*/\
- MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA5*/\
- MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA6*/\
- MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA3*/\
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DIR*/\
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_NXT*/\
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | EN | M4)) /*GPIO_24*/\
- MUX_VAL(CP(ETK_D11_ES2), (IEN | PTU | EN | M4)) /*GPIO_25*/\
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | EN | M4)) /*GPIO_26*/\
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | EN | M4)) /*GPIO_27*/\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /*GPIO_28*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | EN | M4)) /*GPIO_29*/\
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*D2D_MCAD1*/\
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*D2D_MCAD2*/\
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*D2D_MCAD3*/\
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*D2D_MCAD4*/\
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*D2D_MCAD5*/\
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*D2D_MCAD6*/\
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*D2D_MCAD7*/\
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*D2D_MCAD8*/\
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*D2D_MCAD9*/\
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*D2D_MCAD10*/\
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*D2D_MCAD11*/\
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*D2D_MCAD12*/\
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*D2D_MCAD13*/\
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*D2D_MCAD14*/\
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*D2D_MCAD15*/\
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*D2D_MCAD16*/\
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*D2D_MCAD17*/\
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*D2D_MCAD18*/\
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*D2D_MCAD19*/\
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*D2D_MCAD20*/\
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*D2D_MCAD21*/\
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*D2D_MCAD22*/\
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*D2D_MCAD23*/\
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*D2D_MCAD24*/\
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*D2D_MCAD25*/\
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*D2D_MCAD26*/\
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*D2D_MCAD27*/\
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*D2D_MCAD28*/\
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*D2D_MCAD29*/\
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*D2D_MCAD30*/\
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*D2D_MCAD31*/\
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*D2D_MCAD32*/\
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*D2D_MCAD33*/\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*D2D_MCAD34*/\
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*D2D_MCAD35*/\
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*D2D_MCAD36*/\
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*D2D_clk26mi*/\
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*D2D_nrespwron*/\
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*D2D_nreswarm */\
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*D2D_arm9nirq */\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*D2D_uma2p6fiq*/\
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*D2D_spint*/\
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*D2D_frint*/\
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*D2D_dmareq0*/\
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*D2D_dmareq1*/\
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*D2D_dmareq2*/\
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*D2D_dmareq3*/\
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*D2D_n3gtrst*/\
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*D2D_n3gtdi*/\
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*D2D_n3gtdo*/\
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*D2D_n3gtms*/\
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*D2D_n3gtck*/\
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*D2D_n3grtck*/\
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*D2D_mstdby*/\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*D2D_swakeup*/\
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*D2D_idlereq*/\
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*D2D_idleack*/\
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*D2D_mwrite*/\
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*D2D_swrite*/\
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*D2D_mread*/\
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*D2D_sread*/\
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*D2D_mbusflag*/\
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*D2D_sbusflag*/\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
-
-#endif
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
deleted file mode 100644
index ea2aee4ef4a..00000000000
--- a/configs/devkit8000_defconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_TARGET_DEVKIT8000=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_OS_BOOT=y
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x680000
-CONFIG_CMD_SPL_WRITE_SIZE=0x400
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_BOOTP_NTPSERVER=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_TWL4030_LED=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_CONS_INDEX=3
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
deleted file mode 100644
index 1b175be3870..00000000000
--- a/include/configs/devkit8000.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2 at ti.com>
- * Syed Mohammed Khasim <x0khasim at ti.com>
- *
- * (C) Copyright 2009
- * Frederik Kriewitz <frederik at kriewitz.eu>
- *
- * Configuration settings for the DevKit8000 board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-
-#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-
-#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
-
-/* Physical Memory Map */
-
-#include <configs/ti_omap3_common.h>
-
-#define CONFIG_REVISION_TAG 1
-
-/* Size of malloc() pool */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
- /* Sector */
-#undef CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-
-/* Hardware drivers */
-/* DM9000 */
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x2c000000
-#define DM9000_IO CONFIG_DM9000_BASE
-#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
-#define CONFIG_DM9000_USE_16BIT 1
-#define CONFIG_DM9000_NO_SROM 1
-#undef CONFIG_DM9000_DEBUG
-
-/* TWL4030 */
-
-/* Board NAND Info */
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV "nand0"
-/* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET 0x680000
-#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
- /* partition */
-
-/* BOOTP/DHCP options */
-#define CONFIG_BOOTP_NISDOMAIN
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_TIMEOFFSET
-#undef CONFIG_BOOTP_VENDOREX
-
-/* Environment information */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyO2,115200n8\0" \
- "mmcdev=0\0" \
- "vram=12M\0" \
- "dvimode=1024x768MR-16 at 60\0" \
- "defaultdisplay=dvi\0" \
- "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
- "kernelopts=rw\0" \
- "commonargs=" \
- "setenv bootargs console=${console} " \
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay}\0" \
- "mmcargs=" \
- "run commonargs; " \
- "setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk0p2 " \
- "rootwait " \
- "${kernelopts}\0" \
- "nandargs=" \
- "run commonargs; " \
- "setenv bootargs ${bootargs} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=/dev/mtdblock4 " \
- "rootfstype=jffs2 " \
- "${kernelopts}\0" \
- "netargs=" \
- "run commonargs; " \
- "setenv bootargs ${bootargs} " \
- "root=/dev/nfs " \
- "nfsroot=${serverip}:${rootpath},${nfsopts} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
- "${kernelopts} " \
- "dnsip1=${dnsip} " \
- "dnsip2=${dnsip2}\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${loadaddr} 280000 400000; " \
- "bootm ${loadaddr}\0" \
- "netboot=echo Booting from network ...; " \
- "dhcp ${loadaddr}; " \
- "run netargs; " \
- "bootm ${loadaddr}\0" \
- "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run nandboot; " \
- "fi; " \
- "fi; " \
- "else run nandboot; fi\0"
-
-#define CONFIG_BOOTCOMMAND "run autoboot"
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
- 0x01000000) /* 16MB */
-
-/* NAND and environment organization */
-
-#define CONFIG_ENV_OFFSET 0x260000
-
-/* SRAM config */
-#define CONFIG_SYS_SRAM_START 0x40200000
-#define CONFIG_SYS_SRAM_SIZE 0x10000
-
-/* Defines for SPL */
-
-#undef CONFIG_SPL_TEXT_BASE
-#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
-
-/* NAND boot config */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
- 10, 11, 12, 13}
-
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
-
-/* SPL OS boot options */
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
-
-#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
-#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
-#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
-
-#undef CONFIG_SYS_SPL_ARGS_ADDR
-#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
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