[U-Boot] [PATCH v2 7/7] aspeed: ast2500: fix D2-PLL clock setting in RGMII mode

[Simon Glass]

On 1 October 2018 at 01:53, Cédric Le Goater <clg at kaod.org> wrote:
> The algorithm in the ast2500_calc_clock_config() routine suffers from
> integer rounding and the requested rate does not get the appropriate
> set of Numerator, Denumerator, Post Divider parameters.
>
> This is the case for the D2-PLL clock used by the MAC controllers in
> RGMII mode. The requested rated is 250MHz but a 251MHz is assigned.
>
> The easiest way to fix this problem is to introduce an array of clock
> settings defining the N, M, P parameters for well known frequencies
> used by the Aspeed SoC.
>
> Signed-off-by: Cédric Le Goater <clg at kaod.org>
> ---
>  drivers/clk/aspeed/clk_ast2500.c | 38 ++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)

Reviewed-by: Simon Glass <sjg at chromium.org>