[U-Boot] [PATCH v2 20/33] drivers: qe: add TFABOOT support

[Rajesh Bhagat]

Adds TFABOOT support and allows to pick QE firmware
on basis of boot source.

Signed-off-by: Pankit Garg <pankit.garg at nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
---
Change in v2: None

 drivers/qe/qe.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 7654df8008..d7e3a1b923 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -17,9 +17,17 @@
 #include <asm/arch/immap_ls102xa.h>
 #endif
 
+#ifdef CONFIG_TFABOOT
+#include <mmc.h>
+/* required to include IFC and QSPI base address */
+#include <asm/armv8/mmu.h>
+#include <asm/arch/cpu.h>
+#include <environment.h>
+#else
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #include <mmc.h>
 #endif
+#endif
 
 #define MPC85xx_DEVDISR_QE_DISABLE	0x1
 
@@ -170,6 +178,33 @@ void qe_put_snum(u8 snum)
 	}
 }
 
+#ifdef CONFIG_TFABOOT
+void qe_init(uint qe_base)
+{
+	enum boot_src src = get_boot_src();
+
+	/* Init the QE IMMR base */
+	qe_immr = (qe_map_t *)qe_base;
+
+	if (src == BOOT_SOURCE_IFC_NOR) {
+		/*
+		 * Upload microcode to IRAM for those SOCs
+		 * which do not have ROM in QE.
+		 */
+		qe_upload_firmware((const void *)(CONFIG_SYS_QE_FW_ADDR +
+				   CONFIG_SYS_FSL_IFC_BASE));
+
+		/* enable the microcode in IRAM */
+		out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+	}
+
+	gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
+	gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
+
+	qe_sdma_init();
+	qe_snums_init();
+}
+#else
 void qe_init(uint qe_base)
 {
 	/* Init the QE IMMR base */
@@ -192,8 +227,53 @@ void qe_init(uint qe_base)
 	qe_snums_init();
 }
 #endif
+#endif
 
 #ifdef CONFIG_U_QE
+#ifdef CONFIG_TFABOOT
+void u_qe_init(void)
+{
+	enum boot_src src = get_boot_src();
+
+	qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
+
+	void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
+
+	if (src == BOOT_SOURCE_IFC_NOR) {
+		addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_IFC_BASE);
+	}
+	if (src == BOOT_SOURCE_QSPI_NOR) {
+		addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_QSPI_BASE);
+	}
+	if (src == BOOT_SOURCE_SD_MMC) {
+		int dev = CONFIG_SYS_MMC_ENV_DEV;
+		u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+		u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
+
+		if (mmc_initialize(gd->bd)) {
+			printf("%s: mmc_initialize() failed\n", __func__);
+			return;
+		}
+		addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+		struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+
+		if (!mmc) {
+			free(addr);
+			printf("\nMMC cannot find device for ucode\n");
+		} else {
+			printf("\nMMC read: dev # %u, block # %u,\
+			       count %u ...\n", dev, blk, cnt);
+			mmc_init(mmc);
+			(void)mmc->block_dev.block_read(&mmc->block_dev, blk,
+							cnt, addr);
+		}
+	}
+	if (!u_qe_upload_firmware(addr))
+		out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+	if (src == BOOT_SOURCE_SD_MMC)
+		free(addr);
+}
+#else
 void u_qe_init(void)
 {
 	qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
@@ -229,6 +309,7 @@ void u_qe_init(void)
 #endif
 }
 #endif
+#endif
 
 #ifdef CONFIG_U_QE
 void u_qe_resume(void)
-- 
2.17.1