[U-Boot] [PATCH v2 1/7] net: Remove the Faraday ftgmac100 controller driver
Cédric Le Goater
clg at kaod.org
Tue Oct 9 21:34:11 UTC 2018
On 10/9/18 11:19 PM, Joe Hershberger wrote:
> On Tue, Oct 9, 2018 at 4:10 PM Cédric Le Goater <clg at kaod.org> wrote:
>>
>> Hello Joe,
>>
>> On 10/9/18 10:44 PM, Joe Hershberger wrote:
>>> On Tue, Oct 9, 2018 at 11:20 AM Simon Glass <sjg at chromium.org> wrote:
>>>>
>>>> Hi Cedric,
>>>>
>>>> On 2 October 2018 at 09:48, Cédric Le Goater <clg at kaod.org> wrote:
>>>>> On 10/2/18 1:22 PM, Simon Glass wrote:
>>>>>> On 1 October 2018 at 01:53, Cédric Le Goater <clg at kaod.org> wrote:
>>>>>>> There are too many changes in the following patch fixing support for
>>>>>>> the Faraday ftgmac100 controller. To ease the review, remove the whole
>>>>>>> file which is not compiled anymore today (no Kconfig option for the
>>>>>>> driver).
>>>>>>>
>>>>>>> Signed-off-by: Cédric Le Goater <clg at kaod.org>
>>>>>>> ---
>>>>>>> drivers/net/ftgmac100.h | 242 -----------------
>>>>>>> include/netdev.h | 1 -
>>>>>>> drivers/net/ftgmac100.c | 582 ----------------------------------------
>>>>>>> drivers/net/Makefile | 1 -
>>>>>>> 4 files changed, 826 deletions(-)
>>>>>>> delete mode 100644 drivers/net/ftgmac100.h
>>>>>>> delete mode 100644 drivers/net/ftgmac100.c
>>>>>>
>>>>>> Reviewed-by: Simon Glass <sjg at chromium.org>
>>>>>>
>>>>>> Assuming Joe is happy to remove this and start again? While it is
>>>>>> easier to review, it does remove commit history which is bad.
>>>>>
>>>>> yes.
>>>
>>> I have to believe there is a decent amount that is the same, no? I
>>> would prefer not to break git blame unless completely necessary.
>>
>> OK.
>>
>>>>> The changes are so numerous that it is really difficult to understand
>>>>> what the resulting driver looks like and splitting the changes would
>>>>> have been nightmarish. So I took the short path as the driver was not
>>>>> compiled anymore, but this is questionable.
>>>
>>> How many changes are we talking about here?
>>
>> below is a merge of patch one and two. If you think it's fine, I will
>> send a v3 with a couple more cleanups on the Aspeed AST2500 DTS file.
>
> Can you try to separate the cosmetic changes from the substantive ones?
I will in v3.
Thanks,
C.
> Thanks,
> -Joe
>
>>
>> Thanks,
>>
>> C.
>>
>>>
>>>>>
>>>>> I can also resend without the initial removal patch but wouldn't it
>>>>> invalidate the review at the same time ?
>>>>
>>>> Yes but it is not hard to re-review in this case.
>>>>
>>>> Regards,
>>>> Simon
>>>
>>> Thanks,
>>> -Joe
>>>
>>
>>
>> From 634d9707525f7a243835f84d5beb9b0e1a673d32 Mon Sep 17 00:00:00 2001
>> From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg at kaod.org>
>> Date: Fri, 7 Sep 2018 19:15:57 +0200
>> Subject: [PATCH] net: fix support for the Faraday ftgmac100 controller
>> MIME-Version: 1.0
>> Content-Type: text/plain; charset=UTF-8
>> Content-Transfer-Encoding: 8bit
>>
>> The driver is based on the previous one and adds the same support for
>> the Faraday ftgmac100 controller with MAC and MDIO bus support for
>> RGMII/RMII modes. Driver model support was added as well as some
>> enhancements and fixes.
>>
>> Signed-off-by: Cédric Le Goater <clg at kaod.org>
>> ---
>> drivers/net/ftgmac100.h | 158 ++++-----
>> include/netdev.h | 1 -
>> drivers/net/ftgmac100.c | 742 +++++++++++++++++++---------------------
>> drivers/net/Kconfig | 26 ++
>> 4 files changed, 459 insertions(+), 468 deletions(-)
>>
>> diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h
>> index ffbe1f3e3fa7..9a789e4d5bee 100644
>> --- a/drivers/net/ftgmac100.h
>> +++ b/drivers/net/ftgmac100.h
>> @@ -70,48 +70,48 @@ struct ftgmac100 {
>> /*
>> * Interrupt status register & interrupt enable register
>> */
>> -#define FTGMAC100_INT_RPKT_BUF (1 << 0)
>> -#define FTGMAC100_INT_RPKT_FIFO (1 << 1)
>> -#define FTGMAC100_INT_NO_RXBUF (1 << 2)
>> -#define FTGMAC100_INT_RPKT_LOST (1 << 3)
>> -#define FTGMAC100_INT_XPKT_ETH (1 << 4)
>> -#define FTGMAC100_INT_XPKT_FIFO (1 << 5)
>> -#define FTGMAC100_INT_NO_NPTXBUF (1 << 6)
>> -#define FTGMAC100_INT_XPKT_LOST (1 << 7)
>> -#define FTGMAC100_INT_AHB_ERR (1 << 8)
>> -#define FTGMAC100_INT_PHYSTS_CHG (1 << 9)
>> -#define FTGMAC100_INT_NO_HPTXBUF (1 << 10)
>> +#define FTGMAC100_INT_RPKT_BUF BIT(0)
>> +#define FTGMAC100_INT_RPKT_FIFO BIT(1)
>> +#define FTGMAC100_INT_NO_RXBUF BIT(2)
>> +#define FTGMAC100_INT_RPKT_LOST BIT(3)
>> +#define FTGMAC100_INT_XPKT_ETH BIT(4)
>> +#define FTGMAC100_INT_XPKT_FIFO BIT(5)
>> +#define FTGMAC100_INT_NO_NPTXBUF BIT(6)
>> +#define FTGMAC100_INT_XPKT_LOST BIT(7)
>> +#define FTGMAC100_INT_AHB_ERR BIT(8)
>> +#define FTGMAC100_INT_PHYSTS_CHG BIT(9)
>> +#define FTGMAC100_INT_NO_HPTXBUF BIT(10)
>>
>> /*
>> * Interrupt timer control register
>> */
>> #define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0)
>> #define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4)
>> -#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7)
>> +#define FTGMAC100_ITC_RXINT_TIME_SEL BIT(7)
>> #define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8)
>> #define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12)
>> -#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15)
>> +#define FTGMAC100_ITC_TXINT_TIME_SEL BIT(15)
>>
>> /*
>> * Automatic polling timer control register
>> */
>> #define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
>> -#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
>> +#define FTGMAC100_APTC_RXPOLL_TIME_SEL BIT(4)
>> #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
>> -#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
>> +#define FTGMAC100_APTC_TXPOLL_TIME_SEL BIT(12)
>>
>> /*
>> * DMA burst length and arbitration control register
>> */
>> #define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0)
>> #define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3)
>> -#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6)
>> +#define FTGMAC100_DBLAC_RX_THR_EN BIT(6)
>> #define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8)
>> #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10)
>> #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12)
>> #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16)
>> #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20)
>> -#define FTGMAC100_DBLAC_IFG_INC (1 << 23)
>> +#define FTGMAC100_DBLAC_IFG_INC BIT(23)
>>
>> /*
>> * DMA FIFO status register
>> @@ -122,12 +122,12 @@ struct ftgmac100 {
>> #define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf)
>> #define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3)
>> #define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf)
>> -#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26)
>> -#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27)
>> -#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28)
>> -#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29)
>> -#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30)
>> -#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31)
>> +#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY BIT(26)
>> +#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY BIT(27)
>> +#define FTGMAC100_DMAFIFOS_RXDMA_GRANT BIT(28)
>> +#define FTGMAC100_DMAFIFOS_TXDMA_GRANT BIT(29)
>> +#define FTGMAC100_DMAFIFOS_RXDMA_REQ BIT(30)
>> +#define FTGMAC100_DMAFIFOS_TXDMA_REQ BIT(31)
>>
>> /*
>> * Receive buffer size register
>> @@ -137,26 +137,26 @@ struct ftgmac100 {
>> /*
>> * MAC control register
>> */
>> -#define FTGMAC100_MACCR_TXDMA_EN (1 << 0)
>> -#define FTGMAC100_MACCR_RXDMA_EN (1 << 1)
>> -#define FTGMAC100_MACCR_TXMAC_EN (1 << 2)
>> -#define FTGMAC100_MACCR_RXMAC_EN (1 << 3)
>> -#define FTGMAC100_MACCR_RM_VLAN (1 << 4)
>> -#define FTGMAC100_MACCR_HPTXR_EN (1 << 5)
>> -#define FTGMAC100_MACCR_LOOP_EN (1 << 6)
>> -#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7)
>> -#define FTGMAC100_MACCR_FULLDUP (1 << 8)
>> -#define FTGMAC100_MACCR_GIGA_MODE (1 << 9)
>> -#define FTGMAC100_MACCR_CRC_APD (1 << 10)
>> -#define FTGMAC100_MACCR_RX_RUNT (1 << 12)
>> -#define FTGMAC100_MACCR_JUMBO_LF (1 << 13)
>> -#define FTGMAC100_MACCR_RX_ALL (1 << 14)
>> -#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15)
>> -#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16)
>> -#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17)
>> -#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18)
>> -#define FTGMAC100_MACCR_FAST_MODE (1 << 19)
>> -#define FTGMAC100_MACCR_SW_RST (1 << 31)
>> +#define FTGMAC100_MACCR_TXDMA_EN BIT(0)
>> +#define FTGMAC100_MACCR_RXDMA_EN BIT(1)
>> +#define FTGMAC100_MACCR_TXMAC_EN BIT(2)
>> +#define FTGMAC100_MACCR_RXMAC_EN BIT(3)
>> +#define FTGMAC100_MACCR_RM_VLAN BIT(4)
>> +#define FTGMAC100_MACCR_HPTXR_EN BIT(5)
>> +#define FTGMAC100_MACCR_LOOP_EN BIT(6)
>> +#define FTGMAC100_MACCR_ENRX_IN_HALFTX BIT(7)
>> +#define FTGMAC100_MACCR_FULLDUP BIT(8)
>> +#define FTGMAC100_MACCR_GIGA_MODE BIT(9)
>> +#define FTGMAC100_MACCR_CRC_APD BIT(10)
>> +#define FTGMAC100_MACCR_RX_RUNT BIT(12)
>> +#define FTGMAC100_MACCR_JUMBO_LF BIT(13)
>> +#define FTGMAC100_MACCR_RX_ALL BIT(14)
>> +#define FTGMAC100_MACCR_HT_MULTI_EN BIT(15)
>> +#define FTGMAC100_MACCR_RX_MULTIPKT BIT(16)
>> +#define FTGMAC100_MACCR_RX_BROADPKT BIT(17)
>> +#define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18)
>> +#define FTGMAC100_MACCR_FAST_MODE BIT(19)
>> +#define FTGMAC100_MACCR_SW_RST BIT(31)
>>
>> /*
>> * PHY control register
>> @@ -165,8 +165,8 @@ struct ftgmac100 {
>> #define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f)
>> #define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16)
>> #define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21)
>> -#define FTGMAC100_PHYCR_MIIRD (1 << 26)
>> -#define FTGMAC100_PHYCR_MIIWR (1 << 27)
>> +#define FTGMAC100_PHYCR_MIIRD BIT(26)
>> +#define FTGMAC100_PHYCR_MIIWR BIT(27)
>>
>> /*
>> * PHY data register
>> @@ -182,23 +182,23 @@ struct ftgmac100_txdes {
>> unsigned int txdes1;
>> unsigned int txdes2; /* not used by HW */
>> unsigned int txdes3; /* TXBUF_BADR */
>> -} __attribute__ ((aligned(16)));
>> +} __aligned(16);
>>
>> #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
>> -#define FTGMAC100_TXDES0_EDOTR (1 << 15)
>> -#define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
>> -#define FTGMAC100_TXDES0_LTS (1 << 28)
>> -#define FTGMAC100_TXDES0_FTS (1 << 29)
>> -#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
>> +#define FTGMAC100_TXDES0_EDOTR BIT(15)
>> +#define FTGMAC100_TXDES0_CRC_ERR BIT(19)
>> +#define FTGMAC100_TXDES0_LTS BIT(28)
>> +#define FTGMAC100_TXDES0_FTS BIT(29)
>> +#define FTGMAC100_TXDES0_TXDMA_OWN BIT(31)
>>
>> #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
>> -#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16)
>> -#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17)
>> -#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18)
>> -#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19)
>> -#define FTGMAC100_TXDES1_LLC (1 << 22)
>> -#define FTGMAC100_TXDES1_TX2FIC (1 << 30)
>> -#define FTGMAC100_TXDES1_TXIC (1 << 31)
>> +#define FTGMAC100_TXDES1_INS_VLANTAG BIT(16)
>> +#define FTGMAC100_TXDES1_TCP_CHKSUM BIT(17)
>> +#define FTGMAC100_TXDES1_UDP_CHKSUM BIT(18)
>> +#define FTGMAC100_TXDES1_IP_CHKSUM BIT(19)
>> +#define FTGMAC100_TXDES1_LLC BIT(22)
>> +#define FTGMAC100_TXDES1_TX2FIC BIT(30)
>> +#define FTGMAC100_TXDES1_TXIC BIT(31)
>>
>> /*
>> * Receive descriptor, aligned to 16 bytes
>> @@ -208,23 +208,23 @@ struct ftgmac100_rxdes {
>> unsigned int rxdes1;
>> unsigned int rxdes2; /* not used by HW */
>> unsigned int rxdes3; /* RXBUF_BADR */
>> -} __attribute__ ((aligned(16)));
>> +} __aligned(16);
>>
>> #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff)
>> -#define FTGMAC100_RXDES0_EDORR (1 << 15)
>> -#define FTGMAC100_RXDES0_MULTICAST (1 << 16)
>> -#define FTGMAC100_RXDES0_BROADCAST (1 << 17)
>> -#define FTGMAC100_RXDES0_RX_ERR (1 << 18)
>> -#define FTGMAC100_RXDES0_CRC_ERR (1 << 19)
>> -#define FTGMAC100_RXDES0_FTL (1 << 20)
>> -#define FTGMAC100_RXDES0_RUNT (1 << 21)
>> -#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22)
>> -#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23)
>> -#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24)
>> -#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
>> -#define FTGMAC100_RXDES0_LRS (1 << 28)
>> -#define FTGMAC100_RXDES0_FRS (1 << 29)
>> -#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
>> +#define FTGMAC100_RXDES0_EDORR BIT(15)
>> +#define FTGMAC100_RXDES0_MULTICAST BIT(16)
>> +#define FTGMAC100_RXDES0_BROADCAST BIT(17)
>> +#define FTGMAC100_RXDES0_RX_ERR BIT(18)
>> +#define FTGMAC100_RXDES0_CRC_ERR BIT(19)
>> +#define FTGMAC100_RXDES0_FTL BIT(20)
>> +#define FTGMAC100_RXDES0_RUNT BIT(21)
>> +#define FTGMAC100_RXDES0_RX_ODD_NB BIT(22)
>> +#define FTGMAC100_RXDES0_FIFO_FULL BIT(23)
>> +#define FTGMAC100_RXDES0_PAUSE_OPCODE BIT(24)
>> +#define FTGMAC100_RXDES0_PAUSE_FRAME BIT(25)
>> +#define FTGMAC100_RXDES0_LRS BIT(28)
>> +#define FTGMAC100_RXDES0_FRS BIT(29)
>> +#define FTGMAC100_RXDES0_RXPKT_RDY BIT(31)
>>
>> #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
>> #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
>> @@ -232,11 +232,11 @@ struct ftgmac100_rxdes {
>> #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
>> #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
>> #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
>> -#define FTGMAC100_RXDES1_LLC (1 << 22)
>> -#define FTGMAC100_RXDES1_DF (1 << 23)
>> -#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24)
>> -#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25)
>> -#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
>> -#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)
>> +#define FTGMAC100_RXDES1_LLC BIT(22)
>> +#define FTGMAC100_RXDES1_DF BIT(23)
>> +#define FTGMAC100_RXDES1_VLANTAG_AVAIL BIT(24)
>> +#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR BIT(25)
>> +#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26)
>> +#define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27)
>>
>> #endif /* __FTGMAC100_H */
>> diff --git a/include/netdev.h b/include/netdev.h
>> index 55001625fb92..0a1a3a2d8da2 100644
>> --- a/include/netdev.h
>> +++ b/include/netdev.h
>> @@ -43,7 +43,6 @@ int ethoc_initialize(u8 dev_num, int base_addr);
>> int fec_initialize (bd_t *bis);
>> int fecmxc_initialize(bd_t *bis);
>> int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
>> -int ftgmac100_initialize(bd_t *bits);
>> int ftmac100_initialize(bd_t *bits);
>> int ftmac110_initialize(bd_t *bits);
>> void gt6426x_eth_initialize(bd_t *bis);
>> diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
>> index c996f5f4a167..4596385d68cf 100644
>> --- a/drivers/net/ftgmac100.c
>> +++ b/drivers/net/ftgmac100.c
>> @@ -7,265 +7,165 @@
>> *
>> * (C) Copyright 2010 Andes Technology
>> * Macpaul Lin <macpaul at andestech.com>
>> + *
>> + * Copyright (C) 2018, IBM Corporation.
>> */
>>
>> -#include <config.h>
>> -#include <common.h>
>> -#include <malloc.h>
>> +#include <clk.h>
>> +#include <dm.h>
>> +#include <miiphy.h>
>> #include <net.h>
>> -#include <asm/io.h>
>> -#include <asm/dma-mapping.h>
>> -#include <linux/mii.h>
>> +#include <linux/io.h>
>> +#include <linux/iopoll.h>
>>
>> #include "ftgmac100.h"
>>
>> -#define ETH_ZLEN 60
>> -#define CFG_XBUF_SIZE 1536
>> +/* Min frame ethernet frame size without FCS */
>> +#define ETH_ZLEN 60
>>
>> -/* RBSR - hw default init value is also 0x640 */
>> -#define RBSR_DEFAULT_VALUE 0x640
>> +/* Receive Buffer Size Register - HW default is 0x640 */
>> +#define FTGMAC100_RBSR_DEFAULT 0x640
>>
>> /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
>> -#define PKTBUFSTX 4 /* must be power of 2 */
>> +#define PKTBUFSTX 4
>>
>> -struct ftgmac100_data {
>> - ulong txdes_dma;
>> - struct ftgmac100_txdes *txdes;
>> - ulong rxdes_dma;
>> - struct ftgmac100_rxdes *rxdes;
>> - int tx_index;
>> - int rx_index;
>> - int phy_addr;
>> -};
>> +/* Timeout for transmit */
>> +#define FTGMAC100_TX_TIMEOUT_MS 1000
>> +
>> +/* Timeout for a mdio read/write operation */
>> +#define FTGMAC100_MDIO_TIMEOUT_USEC 10000
>>
>> /*
>> - * struct mii_bus functions
>> + * MDC clock cycle threshold
>> + *
>> + * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
>> */
>> -static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr,
>> - int regnum)
>> -{
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> - int phycr;
>> - int i;
>> -
>> - phycr = readl(&ftgmac100->phycr);
>> +#define MDC_CYCTHR 0x34
>>
>> - /* preserve MDC cycle threshold */
>> - phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
>> +/**
>> + * struct ftgmac100_data - private data for the FTGMAC100 driver
>> + *
>> + * @iobase: The base address of the hardware registers
>> + * @txdes: The array of transmit descriptors
>> + * @rxdes: The array of receive descriptors
>> + * @tx_index: Transmit descriptor index in @txdes
>> + * @rx_index: Receive descriptor index in @rxdes
>> + * @phyaddr: The PHY interface address to use
>> + * @phydev: The PHY device backing the MAC
>> + * @bus: The mdio bus
>> + * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
>> + * @max_speed: Maximum speed of Ethernet connection supported by MAC
>> + * @clks: The bulk of clocks assigned to the device in the DT
>> + */
>> +struct ftgmac100_data {
>> + struct ftgmac100 *iobase;
>>
>> - phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
>> - | FTGMAC100_PHYCR_REGAD(regnum)
>> - | FTGMAC100_PHYCR_MIIRD;
>> + struct ftgmac100_txdes txdes[PKTBUFSTX];
>> + struct ftgmac100_rxdes rxdes[PKTBUFSRX];
>> + int tx_index;
>> + int rx_index;
>>
>> - writel(phycr, &ftgmac100->phycr);
>> + u32 phyaddr;
>> + struct phy_device *phydev;
>> + struct mii_dev *bus;
>> + u32 phy_mode;
>> + u32 max_speed;
>>
>> - for (i = 0; i < 10; i++) {
>> - phycr = readl(&ftgmac100->phycr);
>> + struct clk_bulk clks;
>> +};
>>
>> - if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
>> - int data;
>> +static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
>> + int reg_addr)
>> +{
>> + struct ftgmac100_data *priv = bus->priv;
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>> + int phycr;
>> + int data;
>> + int ret;
>>
>> - data = readl(&ftgmac100->phydata);
>> - return FTGMAC100_PHYDATA_MIIRDATA(data);
>> - }
>> + phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
>> + FTGMAC100_PHYCR_PHYAD(phy_addr) |
>> + FTGMAC100_PHYCR_REGAD(reg_addr) |
>> + FTGMAC100_PHYCR_MIIRD;
>> + writel(phycr, &ftgmac100->phycr);
>>
>> - mdelay(10);
>> + ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
>> + !(phycr & FTGMAC100_PHYCR_MIIRD),
>> + FTGMAC100_MDIO_TIMEOUT_USEC);
>> + if (ret) {
>> + pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
>> + priv->phydev->dev->name, phy_addr, reg_addr);
>> + return ret;
>> }
>>
>> - debug("mdio read timed out\n");
>> - return -1;
>> + data = readl(&ftgmac100->phydata);
>> +
>> + return FTGMAC100_PHYDATA_MIIRDATA(data);
>> }
>>
>> -static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr,
>> - int regnum, u16 value)
>> +static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
>> + int reg_addr, u16 value)
>> {
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> + struct ftgmac100_data *priv = bus->priv;
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>> int phycr;
>> int data;
>> - int i;
>> -
>> - phycr = readl(&ftgmac100->phycr);
>> -
>> - /* preserve MDC cycle threshold */
>> - phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
>> -
>> - phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
>> - | FTGMAC100_PHYCR_REGAD(regnum)
>> - | FTGMAC100_PHYCR_MIIWR;
>> + int ret;
>>
>> + phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
>> + FTGMAC100_PHYCR_PHYAD(phy_addr) |
>> + FTGMAC100_PHYCR_REGAD(reg_addr) |
>> + FTGMAC100_PHYCR_MIIWR;
>> data = FTGMAC100_PHYDATA_MIIWDATA(value);
>>
>> writel(data, &ftgmac100->phydata);
>> writel(phycr, &ftgmac100->phycr);
>>
>> - for (i = 0; i < 10; i++) {
>> - phycr = readl(&ftgmac100->phycr);
>> -
>> - if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) {
>> - debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \
>> - "phy_addr: %x\n", phy_addr);
>> - return 0;
>> - }
>> -
>> - mdelay(1);
>> + ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
>> + !(phycr & FTGMAC100_PHYCR_MIIWR),
>> + FTGMAC100_MDIO_TIMEOUT_USEC);
>> + if (ret) {
>> + pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
>> + priv->phydev->dev->name, phy_addr, reg_addr);
>> }
>>
>> - debug("mdio write timed out\n");
>> - return -1;
>> + return ret;
>> }
>>
>> -int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value)
>> +static int ftgmac100_mdio_init(struct ftgmac100_data *priv, int dev_id)
>> {
>> - *value = ftgmac100_mdiobus_read(dev , addr, reg);
>> -
>> - if (*value == -1)
>> - return -1;
>> -
>> - return 0;
>> -}
>> -
>> -int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value)
>> -{
>> - if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1)
>> - return -1;
>> -
>> - return 0;
>> -}
>> -
>> -static int ftgmac100_phy_reset(struct eth_device *dev)
>> -{
>> - struct ftgmac100_data *priv = dev->priv;
>> - int i;
>> - u16 status, adv;
>> -
>> - adv = ADVERTISE_CSMA | ADVERTISE_ALL;
>> -
>> - ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv);
>> + struct mii_dev *bus;
>> + int ret;
>>
>> - printf("%s: Starting autonegotiation...\n", dev->name);
>> + bus = mdio_alloc();
>> + if (!bus)
>> + return -ENOMEM;
>>
>> - ftgmac100_phy_write(dev, priv->phy_addr,
>> - MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
>> + bus->read = ftgmac100_mdio_read;
>> + bus->write = ftgmac100_mdio_write;
>> + bus->priv = priv;
>>
>> - for (i = 0; i < 100000 / 100; i++) {
>> - ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
>> -
>> - if (status & BMSR_ANEGCOMPLETE)
>> - break;
>> - mdelay(1);
>> + ret = mdio_register_seq(bus, dev_id);
>> + if (ret) {
>> + free(bus);
>> + return ret;
>> }
>>
>> - if (status & BMSR_ANEGCOMPLETE) {
>> - printf("%s: Autonegotiation complete\n", dev->name);
>> - } else {
>> - printf("%s: Autonegotiation timed out (status=0x%04x)\n",
>> - dev->name, status);
>> - return 0;
>> - }
>> + priv->bus = bus;
>>
>> - return 1;
>> + return 0;
>> }
>>
>> -static int ftgmac100_phy_init(struct eth_device *dev)
>> +static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
>> {
>> - struct ftgmac100_data *priv = dev->priv;
>> -
>> - int phy_addr;
>> - u16 phy_id, status, adv, lpa, stat_ge;
>> - int media, speed, duplex;
>> - int i;
>> -
>> - /* Check if the PHY is up to snuff... */
>> - for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) {
>> -
>> - ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id);
>> -
>> - /*
>> - * When it is unable to found PHY,
>> - * the interface usually return 0xffff or 0x0000
>> - */
>> - if (phy_id != 0xffff && phy_id != 0x0) {
>> - printf("%s: found PHY at 0x%02x\n",
>> - dev->name, phy_addr);
>> - priv->phy_addr = phy_addr;
>> - break;
>> - }
>> - }
>> -
>> - if (phy_id == 0xffff || phy_id == 0x0) {
>> - printf("%s: no PHY present\n", dev->name);
>> - return 0;
>> - }
>> -
>> - ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
>> -
>> - if (!(status & BMSR_LSTATUS)) {
>> - /* Try to re-negotiate if we don't have link already. */
>> - ftgmac100_phy_reset(dev);
>> -
>> - for (i = 0; i < 100000 / 100; i++) {
>> - ftgmac100_phy_read(dev, priv->phy_addr,
>> - MII_BMSR, &status);
>> - if (status & BMSR_LSTATUS)
>> - break;
>> - udelay(100);
>> - }
>> - }
>> -
>> - if (!(status & BMSR_LSTATUS)) {
>> - printf("%s: link down\n", dev->name);
>> - return 0;
>> - }
>> -
>> -#ifdef CONFIG_FTGMAC100_EGIGA
>> - /* 1000 Base-T Status Register */
>> - ftgmac100_phy_read(dev, priv->phy_addr,
>> - MII_STAT1000, &stat_ge);
>> -
>> - speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF)
>> - ? 1 : 0);
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>> + struct phy_device *phydev = priv->phydev;
>> + u32 maccr;
>>
>> - duplex = ((stat_ge & LPA_1000FULL)
>> - ? 1 : 0);
>> -
>> - if (speed) { /* Speed is 1000 */
>> - printf("%s: link up, 1000bps %s-duplex\n",
>> - dev->name, duplex ? "full" : "half");
>> - return 0;
>> + if (!phydev->link) {
>> + dev_err(phydev->dev, "No link\n");
>> + return -EREMOTEIO;
>> }
>> -#endif
>> -
>> - ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv);
>> - ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa);
>> -
>> - media = mii_nway_result(lpa & adv);
>> - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0);
>> - duplex = (media & ADVERTISE_FULL) ? 1 : 0;
>> -
>> - printf("%s: link up, %sMbps %s-duplex\n",
>> - dev->name, speed ? "100" : "10", duplex ? "full" : "half");
>> -
>> - return 1;
>> -}
>> -
>> -static int ftgmac100_update_link_speed(struct eth_device *dev)
>> -{
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> - struct ftgmac100_data *priv = dev->priv;
>> -
>> - unsigned short stat_fe;
>> - unsigned short stat_ge;
>> - unsigned int maccr;
>> -
>> -#ifdef CONFIG_FTGMAC100_EGIGA
>> - /* 1000 Base-T Status Register */
>> - ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge);
>> -#endif
>> -
>> - ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe);
>> -
>> - if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */
>> - return 0;
>>
>> /* read MAC control register and clear related bits */
>> maccr = readl(&ftgmac100->maccr) &
>> @@ -273,173 +173,130 @@ static int ftgmac100_update_link_speed(struct eth_device *dev)
>> FTGMAC100_MACCR_FAST_MODE |
>> FTGMAC100_MACCR_FULLDUP);
>>
>> -#ifdef CONFIG_FTGMAC100_EGIGA
>> - if (stat_ge & LPA_1000FULL) {
>> - /* set gmac for 1000BaseTX and Full Duplex */
>> - maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP;
>> - }
>> -
>> - if (stat_ge & LPA_1000HALF) {
>> - /* set gmac for 1000BaseTX and Half Duplex */
>> + if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000)
>> maccr |= FTGMAC100_MACCR_GIGA_MODE;
>> - }
>> -#endif
>> -
>> - if (stat_fe & BMSR_100FULL) {
>> - /* set MII for 100BaseTX and Full Duplex */
>> - maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP;
>> - }
>> -
>> - if (stat_fe & BMSR_10FULL) {
>> - /* set MII for 10BaseT and Full Duplex */
>> - maccr |= FTGMAC100_MACCR_FULLDUP;
>> - }
>>
>> - if (stat_fe & BMSR_100HALF) {
>> - /* set MII for 100BaseTX and Half Duplex */
>> + if (phydev->speed == 100)
>> maccr |= FTGMAC100_MACCR_FAST_MODE;
>> - }
>>
>> - if (stat_fe & BMSR_10HALF) {
>> - /* set MII for 10BaseT and Half Duplex */
>> - /* we have already clear these bits, do nothing */
>> - ;
>> - }
>> + if (phydev->duplex)
>> + maccr |= FTGMAC100_MACCR_FULLDUP;
>>
>> /* update MII config into maccr */
>> writel(maccr, &ftgmac100->maccr);
>>
>> - return 1;
>> + return 0;
>> }
>>
>> -/*
>> - * Reset MAC
>> - */
>> -static void ftgmac100_reset(struct eth_device *dev)
>> +static int ftgmac100_phy_init(struct ftgmac100_data *priv, void *dev)
>> {
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> + struct phy_device *phydev;
>> + int ret;
>> +
>> + phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->phy_mode);
>> + if (!phydev)
>> + return -ENODEV;
>> +
>> + phydev->supported &= PHY_GBIT_FEATURES;
>> + if (priv->max_speed) {
>> + ret = phy_set_supported(phydev, priv->max_speed);
>> + if (ret)
>> + return ret;
>> + }
>> + phydev->advertising = phydev->supported;
>> + priv->phydev = phydev;
>> + phy_config(phydev);
>> +
>> + return 0;
>> +}
>>
>> - debug("%s()\n", __func__);
>> +static void ftgmac100_reset(struct ftgmac100_data *priv)
>> +{
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>>
>> - writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr);
>> + setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
>>
>> while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
>> ;
>> }
>>
>> -/*
>> - * Set MAC address
>> - */
>> -static void ftgmac100_set_mac(struct eth_device *dev,
>> - const unsigned char *mac)
>> +static int ftgmac100_set_mac(struct ftgmac100_data *priv,
>> + const unsigned char *mac)
>> {
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>> unsigned int maddr = mac[0] << 8 | mac[1];
>> unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
>>
>> - debug("%s(%x %x)\n", __func__, maddr, laddr);
>> -
>> writel(maddr, &ftgmac100->mac_madr);
>> writel(laddr, &ftgmac100->mac_ladr);
>> -}
>>
>> -static void ftgmac100_set_mac_from_env(struct eth_device *dev)
>> -{
>> - eth_env_get_enetaddr("ethaddr", dev->enetaddr);
>> -
>> - ftgmac100_set_mac(dev, dev->enetaddr);
>> + return 0;
>> }
>>
>> -/*
>> - * disable transmitter, receiver
>> - */
>> -static void ftgmac100_halt(struct eth_device *dev)
>> +static void ftgmac100_stop(struct udevice *dev)
>> {
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> -
>> - debug("%s()\n", __func__);
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>>
>> writel(0, &ftgmac100->maccr);
>> +
>> + phy_shutdown(priv->phydev);
>> }
>>
>> -static int ftgmac100_init(struct eth_device *dev, bd_t *bd)
>> +static int ftgmac100_start(struct udevice *dev)
>> {
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> - struct ftgmac100_data *priv = dev->priv;
>> - struct ftgmac100_txdes *txdes;
>> - struct ftgmac100_rxdes *rxdes;
>> + struct eth_pdata *plat = dev_get_platdata(dev);
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>> + struct phy_device *phydev = priv->phydev;
>> unsigned int maccr;
>> - void *buf;
>> + ulong start, end;
>> + int ret;
>> int i;
>>
>> - debug("%s()\n", __func__);
>> -
>> - if (!priv->txdes) {
>> - txdes = dma_alloc_coherent(
>> - sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma);
>> - if (!txdes)
>> - panic("ftgmac100: out of memory\n");
>> - memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
>> - priv->txdes = txdes;
>> - }
>> - txdes = priv->txdes;
>> -
>> - if (!priv->rxdes) {
>> - rxdes = dma_alloc_coherent(
>> - sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma);
>> - if (!rxdes)
>> - panic("ftgmac100: out of memory\n");
>> - memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
>> - priv->rxdes = rxdes;
>> - }
>> - rxdes = priv->rxdes;
>> + ftgmac100_reset(priv);
>>
>> /* set the ethernet address */
>> - ftgmac100_set_mac_from_env(dev);
>> + ftgmac100_set_mac(priv, plat->enetaddr);
>>
>> /* disable all interrupts */
>> writel(0, &ftgmac100->ier);
>>
>> - /* initialize descriptors */
>> + /* initialize descriptor tables */
>> priv->tx_index = 0;
>> priv->rx_index = 0;
>>
>> - txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
>> - rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
>> -
>> for (i = 0; i < PKTBUFSTX; i++) {
>> - /* TXBUF_BADR */
>> - if (!txdes[i].txdes2) {
>> - buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
>> - if (!buf)
>> - panic("ftgmac100: out of memory\n");
>> - txdes[i].txdes3 = virt_to_phys(buf);
>> - txdes[i].txdes2 = (uint)buf;
>> - }
>> - txdes[i].txdes1 = 0;
>> + priv->txdes[i].txdes3 = 0;
>> + priv->txdes[i].txdes0 = 0;
>> }
>> + priv->txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
>> +
>> + start = (ulong)&priv->txdes[0];
>> + end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
>> + flush_dcache_range(start, end);
>>
>> for (i = 0; i < PKTBUFSRX; i++) {
>> - /* RXBUF_BADR */
>> - if (!rxdes[i].rxdes2) {
>> - buf = net_rx_packets[i];
>> - rxdes[i].rxdes3 = virt_to_phys(buf);
>> - rxdes[i].rxdes2 = (uint)buf;
>> - }
>> - rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
>> + priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
>> + priv->rxdes[i].rxdes0 = 0;
>> }
>> + priv->rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
>> +
>> + start = (ulong)&priv->rxdes[0];
>> + end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
>> + flush_dcache_range(start, end);
>>
>> /* transmit ring */
>> - writel(priv->txdes_dma, &ftgmac100->txr_badr);
>> + writel((u32)priv->txdes, &ftgmac100->txr_badr);
>>
>> /* receive ring */
>> - writel(priv->rxdes_dma, &ftgmac100->rxr_badr);
>> + writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
>>
>> /* poll receive descriptor automatically */
>> writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
>>
>> /* config receive buffer size register */
>> - writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr);
>> + writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
>>
>> /* enable transmitter, receiver */
>> maccr = FTGMAC100_MACCR_TXMAC_EN |
>> @@ -453,130 +310,239 @@ static int ftgmac100_init(struct eth_device *dev, bd_t *bd)
>>
>> writel(maccr, &ftgmac100->maccr);
>>
>> - if (!ftgmac100_phy_init(dev)) {
>> - if (!ftgmac100_update_link_speed(dev))
>> - return -1;
>> + ret = phy_startup(phydev);
>> + if (ret) {
>> + dev_err(phydev->dev, "Could not start PHY\n");
>> + return ret;
>> + }
>> +
>> + ret = ftgmac100_phy_adjust_link(priv);
>> + if (ret) {
>> + dev_err(phydev->dev, "Could not adjust link\n");
>> + return ret;
>> }
>>
>> + printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
>> + phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
>> +
>> return 0;
>> }
>>
>> -/*
>> - * Get a data block via Ethernet
>> - */
>> -static int ftgmac100_recv(struct eth_device *dev)
>> +static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
>> +{
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> + struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
>> + ulong des_start = (ulong)curr_des;
>> + ulong des_end = des_start +
>> + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
>> +
>> + /* Release buffer to DMA and flush descriptor */
>> + curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
>> + flush_dcache_range(des_start, des_end);
>> +
>> + /* Move to next descriptor */
>> + priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
>> +
>> + return 0;
>> +}
>> +
>> +static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
>> {
>> - struct ftgmac100_data *priv = dev->priv;
>> - struct ftgmac100_rxdes *curr_des;
>> - unsigned short rxlen;
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> + struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
>> + int length;
>> + ulong des_start = (ulong)curr_des;
>> + ulong des_end = des_start +
>> + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
>> + ulong data_start = curr_des->rxdes3;
>> + ulong data_end;
>>
>> - curr_des = &priv->rxdes[priv->rx_index];
>> + invalidate_dcache_range(des_start, des_end);
>>
>> if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
>> - return -1;
>> + return -EAGAIN;
>>
>> if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
>> FTGMAC100_RXDES0_CRC_ERR |
>> FTGMAC100_RXDES0_FTL |
>> FTGMAC100_RXDES0_RUNT |
>> FTGMAC100_RXDES0_RX_ODD_NB)) {
>> - return -1;
>> + return -EAGAIN;
>> }
>>
>> - rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
>> + length = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
>>
>> - debug("%s(): RX buffer %d, %x received\n",
>> - __func__, priv->rx_index, rxlen);
>> + /* Invalidate received data */
>> + data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
>> + invalidate_dcache_range(data_start, data_end);
>> + *packetp = (uchar *)data_start;
>>
>> - /* invalidate d-cache */
>> - dma_map_single((void *)curr_des->rxdes2, rxlen, DMA_FROM_DEVICE);
>> -
>> - /* pass the packet up to the protocol layers. */
>> - net_process_received_packet((void *)curr_des->rxdes2, rxlen);
>> -
>> - /* release buffer to DMA */
>> - curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
>> -
>> - priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
>> -
>> - return 0;
>> + return length;
>> }
>>
>> -/*
>> - * Send a data block via Ethernet
>> - */
>> -static int ftgmac100_send(struct eth_device *dev, void *packet, int length)
>> +static int ftgmac100_send(struct udevice *dev, void *packet, int length)
>> {
>> - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> - struct ftgmac100_data *priv = dev->priv;
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> + struct ftgmac100 *ftgmac100 = priv->iobase;
>> struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
>> + ulong des_start = (ulong)curr_des;
>> + ulong des_end = des_start +
>> + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
>> + ulong data_start;
>> + ulong data_end;
>> + ulong start;
>> +
>> + invalidate_dcache_range(des_start, des_end);
>>
>> if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
>> - debug("%s(): no TX descriptor available\n", __func__);
>> - return -1;
>> + dev_err(dev, "no TX descriptor available\n");
>> + return -EPERM;
>> }
>>
>> debug("%s(%x, %x)\n", __func__, (int)packet, length);
>>
>> length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
>>
>> - memcpy((void *)curr_des->txdes2, (void *)packet, length);
>> - dma_map_single((void *)curr_des->txdes2, length, DMA_TO_DEVICE);
>> + curr_des->txdes3 = (unsigned int)packet;
>> +
>> + /* Flush data to be sent */
>> + data_start = curr_des->txdes3;
>> + data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
>> + flush_dcache_range(data_start, data_end);
>>
>> - /* only one descriptor on TXBUF */
>> + /* Only one segment on TXBUF */
>> curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
>> curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
>> - FTGMAC100_TXDES0_LTS |
>> - FTGMAC100_TXDES0_TXBUF_SIZE(length) |
>> - FTGMAC100_TXDES0_TXDMA_OWN ;
>> + FTGMAC100_TXDES0_LTS |
>> + FTGMAC100_TXDES0_TXBUF_SIZE(length) |
>> + FTGMAC100_TXDES0_TXDMA_OWN;
>>
>> - /* start transmit */
>> + /* Flush modified buffer descriptor */
>> + flush_dcache_range(des_start, des_end);
>> +
>> + /* Start transmit */
>> writel(1, &ftgmac100->txpd);
>>
>> + /* Wait until packet is transmitted */
>> + start = get_timer(0);
>> + while (get_timer(start) < FTGMAC100_TX_TIMEOUT_MS) {
>> + invalidate_dcache_range(des_start, des_end);
>> + if (!(curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN))
>> + break;
>> + udelay(10);
>> + }
>> +
>> + if (get_timer(start) >= FTGMAC100_TX_TIMEOUT_MS) {
>> + dev_err(dev, "transmit timeout\n");
>> + return -ETIMEDOUT;
>> + }
>> +
>> debug("%s(): packet sent\n", __func__);
>>
>> + /* Move to next descriptor */
>> priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
>>
>> return 0;
>> }
>>
>> -int ftgmac100_initialize(bd_t *bd)
>> +static int ftgmac100_write_hwaddr(struct udevice *dev)
>> {
>> - struct eth_device *dev;
>> - struct ftgmac100_data *priv;
>> + struct eth_pdata *pdata = dev_get_platdata(dev);
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>>
>> - dev = malloc(sizeof *dev);
>> - if (!dev) {
>> - printf("%s(): failed to allocate dev\n", __func__);
>> - goto out;
>> - }
>> + return ftgmac100_set_mac(priv, pdata->enetaddr);
>> +}
>>
>> - /* Transmit and receive descriptors should align to 16 bytes */
>> - priv = memalign(16, sizeof(struct ftgmac100_data));
>> - if (!priv) {
>> - printf("%s(): failed to allocate priv\n", __func__);
>> - goto free_dev;
>> +static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
>> +{
>> + struct eth_pdata *pdata = dev_get_platdata(dev);
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> + const char *phy_mode;
>> +
>> + pdata->iobase = devfdt_get_addr(dev);
>> + pdata->phy_interface = -1;
>> + phy_mode = dev_read_string(dev, "phy-mode");
>> + if (phy_mode)
>> + pdata->phy_interface = phy_get_interface_by_name(phy_mode);
>> + if (pdata->phy_interface == -1) {
>> + dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
>> + return -EINVAL;
>> }
>>
>> - memset(dev, 0, sizeof(*dev));
>> - memset(priv, 0, sizeof(*priv));
>> + pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
>>
>> - strcpy(dev->name, "FTGMAC100");
>> - dev->iobase = CONFIG_FTGMAC100_BASE;
>> - dev->init = ftgmac100_init;
>> - dev->halt = ftgmac100_halt;
>> - dev->send = ftgmac100_send;
>> - dev->recv = ftgmac100_recv;
>> - dev->priv = priv;
>> + return clk_get_bulk(dev, &priv->clks);
>> +}
>> +
>> +static int ftgmac100_probe(struct udevice *dev)
>> +{
>> + struct eth_pdata *pdata = dev_get_platdata(dev);
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> + int ret;
>>
>> - eth_register(dev);
>> + priv->iobase = (struct ftgmac100 *)pdata->iobase;
>> + priv->phy_mode = pdata->phy_interface;
>> + priv->max_speed = pdata->max_speed;
>> + priv->phyaddr = 0;
>>
>> - ftgmac100_reset(dev);
>> + ret = clk_enable_bulk(&priv->clks);
>> + if (ret)
>> + goto out;
>>
>> - return 1;
>> + ret = ftgmac100_mdio_init(priv, dev->seq);
>> + if (ret) {
>> + dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
>> + goto out;
>> + }
>> +
>> + ret = ftgmac100_phy_init(priv, dev);
>> + if (ret) {
>> + dev_err(dev, "Failed to initialize PHY: %d\n", ret);
>> + goto out;
>> + }
>>
>> -free_dev:
>> - free(dev);
>> out:
>> + if (ret)
>> + clk_release_bulk(&priv->clks);
>> +
>> + return ret;
>> +}
>> +
>> +static int ftgmac100_remove(struct udevice *dev)
>> +{
>> + struct ftgmac100_data *priv = dev_get_priv(dev);
>> +
>> + free(priv->phydev);
>> + mdio_unregister(priv->bus);
>> + mdio_free(priv->bus);
>> + clk_release_bulk(&priv->clks);
>> +
>> return 0;
>> }
>> +
>> +static const struct eth_ops ftgmac100_ops = {
>> + .start = ftgmac100_start,
>> + .send = ftgmac100_send,
>> + .recv = ftgmac100_recv,
>> + .stop = ftgmac100_stop,
>> + .free_pkt = ftgmac100_free_pkt,
>> + .write_hwaddr = ftgmac100_write_hwaddr,
>> +};
>> +
>> +static const struct udevice_id ftgmac100_ids[] = {
>> + { .compatible = "faraday,ftgmac100" },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(ftgmac100) = {
>> + .name = "ftgmac100",
>> + .id = UCLASS_ETH,
>> + .of_match = ftgmac100_ids,
>> + .ofdata_to_platdata = ftgmac100_ofdata_to_platdata,
>> + .probe = ftgmac100_probe,
>> + .remove = ftgmac100_remove,
>> + .ops = &ftgmac100_ops,
>> + .priv_auto_alloc_size = sizeof(struct ftgmac100_data),
>> + .platdata_auto_alloc_size = sizeof(struct eth_pdata),
>> + .flags = DM_FLAG_ALLOC_PRIV_DMA,
>> +};
>> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
>> index 5441da47d13e..3efdc5dc2fae 100644
>> --- a/drivers/net/Kconfig
>> +++ b/drivers/net/Kconfig
>> @@ -186,6 +186,32 @@ config FTMAC100
>> help
>> This MAC is present in Andestech SoCs.
>>
>> +config FTGMAC100
>> + bool "Ftgmac100 Ethernet Support"
>> + depends on DM_ETH
>> + select PHYLIB
>> + help
>> + This driver supports the Faraday's FTGMAC100 Gigabit SoC
>> + Ethernet controller that can be found on Aspeed SoCs (which
>> + include NCSI).
>> +
>> + It is fully compliant with IEEE 802.3 specification for
>> + 10/100 Mbps Ethernet and IEEE 802.3z specification for 1000
>> + Mbps Ethernet and includes Reduced Media Independent
>> + Interface (RMII) and Reduced Gigabit Media Independent
>> + Interface (RGMII) interfaces. It adopts an AHB bus interface
>> + and integrates a link list DMA engine with direct M-Bus
>> + accesses for transmitting and receiving packets. It has
>> + independent TX/RX fifos, supports half and full duplex (1000
>> + Mbps mode only supports full duplex), flow control for full
>> + duplex and backpressure for half duplex.
>> +
>> + The FTGMAC100 also implements IP, TCP, UDP checksum offloads
>> + and supports IEEE 802.1Q VLAN tag insertion and removal. It
>> + offers high-priority transmit queue for QoS and CoS
>> + applications.
>> +
>> +
>> config MVGBE
>> bool "Marvell Orion5x/Kirkwood network interface support"
>> depends on KIRKWOOD || ORION5X
>> --
>> 2.17.1
>>
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