[U-Boot] [PATCH V2] arm: mx5: Add LDB clock config code

[Marek Vasut]

Add code to configure PLL4, from which the LDB clock are directly
derived.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Stefano Babic <sbabic at denx.de>
---
V2: Enable config_ldb_clk() for MX53 only by adding ifdef
---
 arch/arm/include/asm/arch-mx5/clock.h |  1 +
 arch/arm/mach-imx/mx5/clock.c         | 29 +++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
index 0ecbdeede5..6f5ca5888a 100644
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -38,6 +38,7 @@ enum mxc_clock {
 	MXC_NFC_CLK,
 	MXC_PERIPH_CLK,
 	MXC_I2C_CLK,
+	MXC_LDB_CLK,
 };
 
 u32 imx_get_uartclk(void);
diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c
index 427cb12415..2fabdd2eae 100644
--- a/arch/arm/mach-imx/mx5/clock.c
+++ b/arch/arm/mach-imx/mx5/clock.c
@@ -838,6 +838,31 @@ static int config_ddr_clk(u32 emi_clk)
 	return 0;
 }
 
+#ifdef CONFIG_MX53
+static int config_ldb_clk(u32 ref, u32 freq)
+{
+	int ret = 0;
+	struct pll_param pll_param;
+
+	memset(&pll_param, 0, sizeof(struct pll_param));
+
+	ret = calc_pll_params(ref, freq, &pll_param);
+	if (ret != 0) {
+		printf("Error:Can't find pll parameters: %d\n",
+			ret);
+		return ret;
+	}
+
+	return config_pll_clk(PLL4_CLOCK, &pll_param);
+}
+#else
+static int config_ldb_clk(u32 ref, u32 freq)
+{
+	/* Platform not supported */
+	return -EINVAL;
+}
+#endif
+
 /*
  * This function assumes the expected core clock has to be changed by
  * modifying the PLL. This is NOT true always but for most of the times,
@@ -879,6 +904,10 @@ int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
 		if (config_nfc_clk(freq))
 			return -EINVAL;
 		break;
+	case MXC_LDB_CLK:
+		if (config_ldb_clk(ref, freq))
+			return -EINVAL;
+		break;
 	default:
 		printf("Warning:Unsupported or invalid clock type\n");
 	}
-- 
2.18.0