[U-Boot] [PATCH] riscv: dts: Sync to Linux Kernel ae350 dts.
Bin Meng
bmeng.cn at gmail.com
Tue Oct 16 01:43:17 UTC 2018
Hi Rick,
On Tue, Oct 16, 2018 at 9:25 AM Rick Chen <rickchen36 at gmail.com> wrote:
>
> Bin Meng <bmeng.cn at gmail.com> 於 2018年10月8日 週一 下午1:49寫道：
> >
> > Hi Rick,
> >
> > On Mon, Oct 8, 2018 at 1:33 PM Andes <uboot at andestech.com> wrote:
> > >
> > > From: Rick Chen <rick at andestech.com>
> > >
> > > Use same dts to boot U-Boot and Kernel.
> > >
> > > Following are the change notes :
> > > 1 Remove early printk bootargs.
> > > 2 Timer frequency are changed to 60MHz.
> > > 3 Add dma, snd, lcd, virtio nodes which are used
> > > in kernel drivers. They does not been used by U-Boot.
> > > 4 Change spi irq from 3 to 4.
> > >
> > > Signed-off-by: Rick Chen <rick at andestech.com>
> > > Cc: Greentime Hu <greentime at andestech.com>
> > > ---
> > > arch/riscv/dts/ae350.dts | 107 ++++++++++++++++++++++++++++++++++++++++-------
> > > 1 file changed, 92 insertions(+), 15 deletions(-)
> > >
> > > diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts
> > > index 4717ae8..e48c298 100644
> > > --- a/arch/riscv/dts/ae350.dts
> > > +++ b/arch/riscv/dts/ae350.dts
> > > @@ -12,15 +12,14 @@
> > > };
> > >
> > > chosen {
> > > - bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
> > > + bootargs = "console=ttyS0,38400n8 debug loglevel=7";
> > > stdout-path = "uart0:38400n8";
> > > };
> > >
> > > cpus {
> > > #address-cells = <1>;
> > > #size-cells = <0>;
> > > - timebase-frequency = <10000000>;
> > > -
> > > + timebase-frequency = <60000000>;
> > > CPU0: cpu at 0 {
> > > device_type = "cpu";
> > > reg = <0>;
> > > @@ -29,7 +28,8 @@
> > > riscv,isa = "rv64imafdc";
> > > mmu-type = "riscv,sv39";
> > > clock-frequency = <60000000>;
> > > -
> > > + d-cache-size = <0x8000>;
> > > + d-cache-line-size = <32>;
> > > CPU0_intc: interrupt-controller {
> > > #interrupt-cells = <1>;
> > > interrupt-controller;
> > > @@ -48,13 +48,6 @@
> > > #size-cells = <2>;
> > > compatible = "andestech,riscv-ae350-soc";
> > > ranges;
> > > - };
> > > -
> > > - plmt0 at e6000000 {
> > > - compatible = "riscv,plmt0";
> > > - interrupts-extended = <&CPU0_intc 7>;
> > > - reg = <0x0 0xe6000000 0x0 0x100000>;
> > > - };
> > >
> > > plic0: interrupt-controller at e4000000 {
> > > compatible = "riscv,plic0";
> > > @@ -62,7 +55,7 @@
> > > #interrupt-cells = <2>;
> > > interrupt-controller;
> > > reg = <0x0 0xe4000000 0x0 0x2000000>;
> > > - riscv,ndev=<31>;
> > > + riscv,ndev=<71>;
> > > interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
> > > };
> > >
> > > @@ -76,6 +69,13 @@
> > > interrupts-extended = <&CPU0_intc 3>;
> > > };
> > >
> > > + plmt0 at e6000000 {
> > > + compatible = "riscv,plmt0";
> > > + interrupts-extended = <&CPU0_intc 7>;
> > > + reg = <0x0 0xe6000000 0x0 0x100000>;
> > > + };
> > > + };
> > > +
> > > spiclk: virt_100mhz {
> > > #clock-cells = <0>;
> > > compatible = "fixed-clock";
> > > @@ -85,7 +85,7 @@
> > > timer0: timer at f0400000 {
> > > compatible = "andestech,atcpit100";
> > > reg = <0x0 0xf0400000 0x0 0x1000>;
> > > - clock-frequency = <40000000>;
> > > + clock-frequency = <60000000>;
> > > interrupts = <3 4>;
> > > interrupt-parent = <&plic0>;
> > > };
> > > @@ -119,11 +119,89 @@
> > > interrupt-parent = <&plic0>;
> > > };
> > >
> > > + dma0: dma at f0c00000 {
> > > + compatible = "andestech,atcdmac300";
> > > + reg = <0x0 0xf0c00000 0x0 0x1000>;
> > > + interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
> > > + dma-channels = <8>;
> > > + interrupt-parent = <&plic0>;
> > > + };
> > > +
> > > + lcd0: lcd at e0200000 {
> > > + compatible = "andestech,atflcdc100";
> > > + reg = <0x0 0xe0200000 0x0 0x1000>;
> > > + interrupts = <20 4>;
> > > + interrupt-parent = <&plic0>;
> > > + };
> > > +
> > > smc0: smc at e0400000 {
> > > compatible = "andestech,atfsmc020";
> > > reg = <0x0 0xe0400000 0x0 0x1000>;
> > > };
> > >
> > > + snd0: snd at f0d00000 {
> > > + compatible = "andestech,atfac97";
> > > + reg = <0x0 0xf0d00000 0x0 0x1000>;
> > > + interrupts = <17 4>;
> > > + interrupt-parent = <&plic0>;
> > > + };
> > > +
> > > + virtio_mmio at fe007000 {
> > > + interrupts = <0x17 0x4>;
> > > + interrupt-parent = <0x2>;
> > > + reg = <0x0 0xfe007000 0x0 0x1000>;
> > > + compatible = "virtio,mmio";
> > > + };
> > > +
> > > + virtio_mmio at fe006000 {
> > > + interrupts = <0x16 0x4>;
> > > + interrupt-parent = <0x2>;
> > > + reg = <0x0 0xfe006000 0x0 0x1000>;
> > > + compatible = "virtio,mmio";
> > > + };
> > > +
> > > + virtio_mmio at fe005000 {
> > > + interrupts = <0x15 0x4>;
> > > + interrupt-parent = <0x2>;
> > > + reg = <0x0 0xfe005000 0x0 0x1000>;
> > > + compatible = "virtio,mmio";
> > > + };
> > > +
> > > + virtio_mmio at fe004000 {
> > > + interrupts = <0x14 0x4>;
> > > + interrupt-parent = <0x2>;
> > > + reg = <0x0 0xfe004000 0x0 0x1000>;
> > > + compatible = "virtio,mmio";
> > > + };
> > > +
> > > + virtio_mmio at fe003000 {
> > > + interrupts = <0x13 0x4>;
> > > + interrupt-parent = <0x2>;
> > > + reg = <0x0 0xfe003000 0x0 0x1000>;
> > > + compatible = "virtio,mmio";
> > > + };
> > > +
> > > + virtio_mmio at fe002000 {
> > > + interrupts = <0x12 0x4>;
> > > + interrupt-parent = <0x2>;
> > > + reg = <0x0 0xfe002000 0x0 0x1000>;
> > > + compatible = "virtio,mmio";
> > > + };
> > > +
> > > + virtio_mmio at fe001000 {
> > > + interrupts = <0x11 0x4>;
> > > + interrupt-parent = <0x2>;
> > > + reg = <0x0 0xfe001000 0x0 0x1000>;
> > > + compatible = "virtio,mmio";
> > > + };
> > > +
> > > + virtio_mmio at fe000000 {
> > > + interrupts = <0x10 0x4>;
> > > + interrupt-parent = <0x2>;
> > > + reg = <0x0 0xfe000000 0x0 0x1000>;
> > > + compatible = "virtio,mmio";
> > > + };
> > > +
> >
> > Do these virtio devices exist on the real hardware?
>
> Hi Bin
>
> No.
> These virtio nodes does not exist on the read board.
> It is required on Andes' QEMU ae350 board.
>
So it is a special target, which matches some hardware components plus
some "virtual" components like VirtIO?
BTW: where is the Linux AE350 DTS file? I do not see it in the Linux tree.
Regards,
Bin
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