[U-Boot] [PATCH v6 25/34] pinctrl: Add pinctrl driver for i.MX8
Anatolij Gustschin
agust at denx.de
Thu Oct 18 12:28:28 UTC 2018
From: Peng Fan <peng.fan at nxp.com>
Add pinctrl driver for i.MX8. The pads configuration is controlled
by SCU, so need to ask SCU to configure pads through scfw API.
Add pinctrl-scu to invoke sc_pad_set to configure pads.
Add a new flag IMX8_USE_SCU to differentiate i.MX8 from other platforms
which could directly configure pads from Acore side.
Add CONFIG_PINCTRL_IMX8 as the built gate.
Signed-off-by: Peng Fan <peng.fan at nxp.com>
Reviewed-by: Anatolij Gustschin <agust at denx.de>
Cc: Stefano Babic <sbabic at denx.de>
---
drivers/pinctrl/nxp/Kconfig | 18 +++
drivers/pinctrl/nxp/Makefile | 2 +
drivers/pinctrl/nxp/pinctrl-imx.c | 209 ++++++++++++++++-------------
drivers/pinctrl/nxp/pinctrl-imx.h | 16 +++
drivers/pinctrl/nxp/pinctrl-imx8.c | 40 ++++++
drivers/pinctrl/nxp/pinctrl-scu.c | 66 +++++++++
6 files changed, 258 insertions(+), 93 deletions(-)
create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8.c
create mode 100644 drivers/pinctrl/nxp/pinctrl-scu.c
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index b668359a0b..799d1d2465 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -1,6 +1,9 @@
config PINCTRL_IMX
bool
+config PINCTRL_IMX_SCU
+ bool
+
config PINCTRL_IMX5
bool "IMX5 pinctrl driver"
depends on ARCH_MX5 && PINCTRL_FULL
@@ -56,3 +59,18 @@ config PINCTRL_IMX7ULP
is different from the linux one, this is a simple implementation,
only parses the 'fsl,pins' property and configure related
registers.
+
+config PINCTRL_IMX8
+ bool "IMX8 pinctrl driver"
+ depends on ARCH_IMX8 && PINCTRL_FULL
+ select DEVRES
+ select PINCTRL_IMX
+ select PINCTRL_IMX_SCU
+ help
+ Say Y here to enable the imx8 pinctrl driver
+
+ This provides a simple pinctrl driver for i.MX8 SoC familiy.
+ This feature depends on device tree configuration. This driver
+ is different from the linux one, this is a simple implementation,
+ only parses the 'fsl,pins' property and configures related
+ registers.
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index c763948376..310b3b3a2e 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_PINCTRL_IMX5) += pinctrl-imx5.o
obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o
obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
+obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
+obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o
diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c
index 36e1e8983c..04ea82aba5 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx.c
@@ -28,7 +28,9 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
dev_dbg(dev, "%s: %s\n", __func__, config->name);
- if (info->flags & SHARE_MUX_CONF_REG)
+ if (info->flags & IMX8_USE_SCU)
+ pin_size = SHARE_IMX8_PIN_SIZE;
+ else if (info->flags & SHARE_MUX_CONF_REG)
pin_size = SHARE_FSL_PIN_SIZE;
else
pin_size = FSL_PIN_SIZE;
@@ -58,112 +60,127 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
npins = size / pin_size;
- /*
- * Refer to linux documentation for details:
- * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
- */
- for (i = 0; i < npins; i++) {
- mux_reg = pin_data[j++];
-
- if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
- mux_reg = -1;
-
- if (info->flags & SHARE_MUX_CONF_REG) {
- conf_reg = mux_reg;
- } else {
- conf_reg = pin_data[j++];
- if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
- conf_reg = -1;
- }
+ if (info->flags & IMX8_USE_SCU) {
+ imx_pinctrl_scu_conf_pins(info, pin_data, npins);
+ } else {
+ /*
+ * Refer to linux documentation for details:
+ * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+ */
+ for (i = 0; i < npins; i++) {
+ mux_reg = pin_data[j++];
- if ((mux_reg == -1) || (conf_reg == -1)) {
- dev_err(dev, "Error mux_reg or conf_reg\n");
- devm_kfree(dev, pin_data);
- return -EINVAL;
- }
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
- input_reg = pin_data[j++];
- mux_mode = pin_data[j++];
- input_val = pin_data[j++];
- config_val = pin_data[j++];
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ conf_reg = mux_reg;
+ } else {
+ conf_reg = pin_data[j++];
+ if (!(info->flags & ZERO_OFFSET_VALID) &&
+ !conf_reg)
+ conf_reg = -1;
+ }
- dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, "
- "mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n",
- mux_reg, conf_reg, input_reg, mux_mode, input_val,
- config_val);
+ if ((mux_reg == -1) || (conf_reg == -1)) {
+ dev_err(dev, "Error mux_reg or conf_reg\n");
+ devm_kfree(dev, pin_data);
+ return -EINVAL;
+ }
- if (config_val & IMX_PAD_SION)
- mux_mode |= IOMUXC_CONFIG_SION;
+ input_reg = pin_data[j++];
+ mux_mode = pin_data[j++];
+ input_val = pin_data[j++];
+ config_val = pin_data[j++];
- config_val &= ~IMX_PAD_SION;
+ dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, "
+ "input_reg 0x%x, mux_mode 0x%x, "
+ "input_val 0x%x, config_val 0x%x\n",
+ mux_reg, conf_reg, input_reg, mux_mode,
+ input_val, config_val);
- /* Set Mux */
- if (info->flags & SHARE_MUX_CONF_REG) {
- clrsetbits_le32(info->base + mux_reg, info->mux_mask,
- mux_mode << mux_shift);
- } else {
- writel(mux_mode, info->base + mux_reg);
- }
+ if (config_val & IMX_PAD_SION)
+ mux_mode |= IOMUXC_CONFIG_SION;
- dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg,
- mux_mode);
+ config_val &= ~IMX_PAD_SION;
- /*
- * Set select input
- *
- * If the select input value begins with 0xff, it's a quirky
- * select input and the value should be interpreted as below.
- * 31 23 15 7 0
- * | 0xff | shift | width | select |
- * It's used to work around the problem that the select
- * input for some pin is not implemented in the select
- * input register but in some general purpose register.
- * We encode the select input value, width and shift of
- * the bit field into input_val cell of pin function ID
- * in device tree, and then decode them here for setting
- * up the select input bits in general purpose register.
- */
+ /* Set Mux */
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ clrsetbits_le32(info->base + mux_reg,
+ info->mux_mask,
+ mux_mode << mux_shift);
+ } else {
+ writel(mux_mode, info->base + mux_reg);
+ }
+
+ dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n",
+ mux_reg, mux_mode);
- if (input_val >> 24 == 0xff) {
- u32 val = input_val;
- u8 select = val & 0xff;
- u8 width = (val >> 8) & 0xff;
- u8 shift = (val >> 16) & 0xff;
- u32 mask = ((1 << width) - 1) << shift;
- /*
- * The input_reg[i] here is actually some IOMUXC general
- * purpose register, not regular select input register.
- */
- val = readl(info->base + input_reg);
- val &= ~mask;
- val |= select << shift;
- writel(val, info->base + input_reg);
- } else if (input_reg) {
/*
- * Regular select input register can never be at offset
- * 0, and we only print register value for regular case.
+ * Set select input
+ *
+ * If the select input value begins with 0xff,
+ * it's a quirky select input and the value should
+ * be interpreted as below.
+ * 31 23 15 7 0
+ * | 0xff | shift | width | select |
+ * It's used to work around the problem that the
+ * select input for some pin is not implemented in
+ * the select input register but in some general
+ * purpose register. We encode the select input
+ * value, width and shift of the bit field into
+ * input_val cell of pin function ID in device tree,
+ * and then decode them here for setting up the select
+ * input bits in general purpose register.
*/
- if (info->input_sel_base)
- writel(input_val, info->input_sel_base +
- input_reg);
- else
- writel(input_val, info->base + input_reg);
-
- dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n",
- input_reg, input_val);
- }
- /* Set config */
- if (!(config_val & IMX_NO_PAD_CTL)) {
- if (info->flags & SHARE_MUX_CONF_REG) {
- clrsetbits_le32(info->base + conf_reg,
- ~info->mux_mask, config_val);
- } else {
- writel(config_val, info->base + conf_reg);
+ if (input_val >> 24 == 0xff) {
+ u32 val = input_val;
+ u8 select = val & 0xff;
+ u8 width = (val >> 8) & 0xff;
+ u8 shift = (val >> 16) & 0xff;
+ u32 mask = ((1 << width) - 1) << shift;
+ /*
+ * The input_reg[i] here is actually some
+ * IOMUXC general purpose register, not
+ * regular select input register.
+ */
+ val = readl(info->base + input_reg);
+ val &= ~mask;
+ val |= select << shift;
+ writel(val, info->base + input_reg);
+ } else if (input_reg) {
+ /*
+ * Regular select input register can never be
+ * at offset 0, and we only print register
+ * value for regular case.
+ */
+ if (info->input_sel_base)
+ writel(input_val,
+ info->input_sel_base +
+ input_reg);
+ else
+ writel(input_val,
+ info->base + input_reg);
+
+ dev_dbg(dev, "select_input: offset 0x%x val "
+ "0x%x\n", input_reg, input_val);
}
- dev_dbg(dev, "write config: offset 0x%x val 0x%x\n",
- conf_reg, config_val);
+ /* Set config */
+ if (!(config_val & IMX_NO_PAD_CTL)) {
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ clrsetbits_le32(info->base + conf_reg,
+ ~info->mux_mask,
+ config_val);
+ } else {
+ writel(config_val,
+ info->base + conf_reg);
+ }
+
+ dev_dbg(dev, "write config: offset 0x%x val "
+ "0x%x\n", conf_reg, config_val);
+ }
}
}
@@ -193,6 +210,9 @@ int imx_pinctrl_probe(struct udevice *dev,
priv->dev = dev;
priv->info = info;
+ if (info->flags & IMX8_USE_SCU)
+ return 0;
+
addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
&size);
@@ -238,6 +258,9 @@ int imx_pinctrl_remove(struct udevice *dev)
struct imx_pinctrl_priv *priv = dev_get_priv(dev);
struct imx_pinctrl_soc_info *info = priv->info;
+ if (info->flags & IMX8_USE_SCU)
+ return 0;
+
if (info->input_sel_base)
unmap_sysmem(info->input_sel_base);
if (info->base)
diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h
index b0032455b7..947975ee72 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx.h
+++ b/drivers/pinctrl/nxp/pinctrl-imx.h
@@ -40,13 +40,29 @@ extern const struct pinctrl_ops imx_pinctrl_ops;
#define FSL_PIN_SIZE 24
#define SHARE_FSL_PIN_SIZE 20
+/* Each pin on imx8qm/qxp consists of 2 u32 PIN_FUNC_ID and 1 u32 CONFIG */
+#define SHARE_IMX8_PIN_SIZE 12
+
#define SHARE_MUX_CONF_REG 0x1
#define ZERO_OFFSET_VALID 0x2
#define CONFIG_IBE_OBE 0x4
+#define IMX8_USE_SCU 0x8
#define IOMUXC_CONFIG_SION (0x1 << 4)
int imx_pinctrl_probe(struct udevice *dev, struct imx_pinctrl_soc_info *info);
int imx_pinctrl_remove(struct udevice *dev);
+
+#ifdef CONFIG_PINCTRL_IMX_SCU
+int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info,
+ u32 *pin_data, int npins);
+#else
+static inline int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info,
+ u32 *pin_data, int npins)
+{
+ return 0;
+}
+#endif
+
#endif /* __DRIVERS_PINCTRL_IMX_H */
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8.c b/drivers/pinctrl/nxp/pinctrl-imx8.c
new file mode 100644
index 0000000000..0738da0ebe
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx8.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct imx_pinctrl_soc_info imx8_pinctrl_soc_info = {
+ .flags = IMX8_USE_SCU,
+};
+
+static int imx8_pinctrl_probe(struct udevice *dev)
+{
+ struct imx_pinctrl_soc_info *info =
+ (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+ return imx_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id imx8_pinctrl_match[] = {
+ { .compatible = "fsl,imx8qxp-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(imx8_pinctrl) = {
+ .name = "imx8_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(imx8_pinctrl_match),
+ .probe = imx8_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+ .ops = &imx_pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/pinctrl/nxp/pinctrl-scu.c b/drivers/pinctrl/nxp/pinctrl-scu.c
new file mode 100644
index 0000000000..aa11075e0a
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-scu.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <linux/bitops.h>
+#include <asm/io.h>
+#include <asm/arch/sci/sci.h>
+#include <misc.h>
+
+#include "pinctrl-imx.h"
+
+#define PADRING_IFMUX_EN_SHIFT 31
+#define PADRING_IFMUX_EN_MASK BIT(31)
+#define PADRING_GP_EN_SHIFT 30
+#define PADRING_GP_EN_MASK BIT(30)
+#define PADRING_IFMUX_SHIFT 27
+#define PADRING_IFMUX_MASK GENMASK(29, 27)
+
+static int imx_pinconf_scu_set(struct imx_pinctrl_soc_info *info, u32 pad,
+ u32 mux, u32 val)
+{
+ int ret;
+
+ /*
+ * Mux should be done in pmx set, but we do not have a good api
+ * to handle that in scfw, so config it in pad conf func
+ */
+
+ val |= PADRING_IFMUX_EN_MASK;
+ val |= PADRING_GP_EN_MASK;
+ val |= (mux << PADRING_IFMUX_SHIFT) & PADRING_IFMUX_MASK;
+
+ ret = sc_pad_set(-1, pad, val);
+ if (ret)
+ printf("%s %d\n", __func__, ret);
+
+ return 0;
+}
+
+int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info, u32 *pin_data,
+ int npins)
+{
+ int pin_id, mux, config_val;
+ int i, j = 0;
+ int ret;
+
+ /*
+ * Refer to linux documentation for details:
+ * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+ */
+ for (i = 0; i < npins; i++) {
+ pin_id = pin_data[j++];
+ mux = pin_data[j++];
+ config_val = pin_data[j++];
+
+ ret = imx_pinconf_scu_set(info, pin_id, mux, config_val);
+ if (ret)
+ printf("Set pin %d, mux %d, val %d, error\n", pin_id,
+ mux, config_val);
+ }
+
+ return 0;
+}
--
2.17.1
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