[U-Boot] [PATCH 23/30] riscv: do not blindly modify the mstatus CSR

[Rick Chen]

> > >
> > > The mstatus CSR includes WPRI (writes preserve values, reads ignore
> > > values) fields and must therefore not be set to zero without
> > > preserving these fields. It is not apparent why mstatus is set to zero
> > > here since it is not required for u-boot to run. Remove it.
> >
> > nits: U-Boot
> >
> > >
> > > This instruction and others encode zero as an immediate.  RISC-V has
> > > the zero register for this purpose. Replace the immediates with the
> > > zero register.
> > >
> > > Signed-off-by: Lukas Auer <lukas.auer at aisec.fraunhofer.de>
> > > ---
> > >
> > >  arch/riscv/cpu/start.S | 7 +++----
> > >  1 file changed, 3 insertions(+), 4 deletions(-)
> > >
> >
> > Reviewed-by: Bin Meng <bmeng.cn at gmail.com>

Reviewed-by: Rick Chen <rick at andestech.com>