[U-Boot] [PATCH v2 0/6] sunxi: extend SPL header to propagate DRAM size and H6 3GiB DRAM support

[Icenowy Zheng]

This series tries to solve three issues we currently have on
Allwinner boards:
- The DRAM sizing routine can only cope with power-of-two sized DRAM.
- The DRAM sizing routine steps through all DRAM, possibly hitting secure
  memory.
- The SPL header versioning is quite strict and tends to break every time
  we need to update it.
- On some Allwinner SoCs the maximum supported DRAM size of the DRAM
  controller is bigger than the accessible DRAM size of the CPU.

So Andre Przywara adapted something along the lines of semantic
versioning[1], where we can add backwards-compatible changes to the SPL
header without breaking every tool.

The second patch and the third patches introduces the version schema and
does necessary refactors, then the fourth and the fifth patches prepare
for 3GiB memory support. The sixth patch finally enables the SPL header
to store the the DRAM size, and let U-Boot binary check which range is
accessible when picking the data.

The first patch is a prepare for the other patches, as without it newly
introduced code will make H6 SPL overflow, which makes the patchset not
possible to test, as the only available 3GiB DRAM device now is the
3GiB version of Pine H64 sample.

Andre Przywara (3):
  sunxi: Extend SPL header versioning
  sunxi: board.c: refactor SPL header checks
  sunxi: store DRAM size in SPL header

Icenowy Zheng (3):
  sunxi: disable Pine A64 model detection code on other boards
  sunxi: map DRAM part with 3G size
  sunxi: add Kconfig option for the maximum accessible DRAM

 arch/arm/include/asm/arch-sunxi/spl.h | 22 +++++---
 arch/arm/mach-sunxi/Kconfig           | 18 +++++++
 arch/arm/mach-sunxi/board.c           |  2 +-
 board/sunxi/board.c                   | 74 ++++++++++++++++++++++-----
 configs/pine64_plus_defconfig         |  1 +
 5 files changed, 97 insertions(+), 20 deletions(-)

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2.18.1