[U-Boot] [PATCH v2 0/6] sunxi: extend SPL header to propagate DRAM size and H6 3GiB DRAM support

[Maxime Ripard]

On Thu, Oct 25, 2018 at 05:23:01PM +0800, Icenowy Zheng wrote:
> This series tries to solve three issues we currently have on
> Allwinner boards:
> - The DRAM sizing routine can only cope with power-of-two sized DRAM.
> - The DRAM sizing routine steps through all DRAM, possibly hitting secure
>   memory.
> - The SPL header versioning is quite strict and tends to break every time
>   we need to update it.
> - On some Allwinner SoCs the maximum supported DRAM size of the DRAM
>   controller is bigger than the accessible DRAM size of the CPU.
> 
> So Andre Przywara adapted something along the lines of semantic
> versioning[1], where we can add backwards-compatible changes to the SPL
> header without breaking every tool.
> 
> The second patch and the third patches introduces the version schema and
> does necessary refactors, then the fourth and the fifth patches prepare
> for 3GiB memory support. The sixth patch finally enables the SPL header
> to store the the DRAM size, and let U-Boot binary check which range is
> accessible when picking the data.
> 
> The first patch is a prepare for the other patches, as without it newly
> introduced code will make H6 SPL overflow, which makes the patchset not
> possible to test, as the only available 3GiB DRAM device now is the
> 3GiB version of Pine H64 sample.

For the whole series,
Acked-by: Maxime Ripard <maxime.ripard at bootlin.com>

Thanks!
Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com