[U-Boot] [RESEND PATCHv4 2/9] armv8: lx2160a: add MMU table entries for PCIe

[Bin Meng]

On Mon, Mar 25, 2019 at 10:24 AM Z.q. Hou <zhiqiang.hou at nxp.com> wrote:
>
> From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
>
> The lx2160a have up to 6 PCIe controllers and have different
> address and size of PCIe region.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> ---
> V4:
>  - No change
>
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c            | 12 ++++++++++++
>  arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |  2 ++
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  | 14 +++++++++++++-
>  3 files changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index 978d46b32f..2805e5f6f2 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -257,6 +257,18 @@ static struct mm_region final_map[] = {
>           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
>           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
>         },
> +#endif
> +#ifdef CONFIG_ARCH_LX2160A
> +       { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
> +         SYS_PCIE5_PHYS_SIZE,
> +         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> +         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
> +       },
> +       { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
> +         SYS_PCIE6_PHYS_SIZE,
> +         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> +         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
> +       },
>  #endif
>         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
>           CONFIG_SYS_FSL_WRIOP1_SIZE,
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
> index 89124cdb0e..bdeb62576c 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
> @@ -44,6 +44,8 @@
>  #define CONFIG_SYS_PCIE2_PHYS_SIZE     0x800000000
>  #define CONFIG_SYS_PCIE3_PHYS_SIZE     0x800000000
>  #define CONFIG_SYS_PCIE4_PHYS_SIZE     0x800000000
> +#define SYS_PCIE5_PHYS_SIZE            0x800000000
> +#define SYS_PCIE6_PHYS_SIZE            0x800000000

Why are these macros not CONFIG_ prefixed?

>  #endif
>  #define CONFIG_SYS_FSL_WRIOP1_BASE     0x4300000000
>  #define CONFIG_SYS_FSL_WRIOP1_SIZE     0x100000000
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> index 9fab88ab2f..c9aa0cad71 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> @@ -167,7 +167,19 @@
>  #define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
>  #define CONFIG_SYS_PCIE3_ADDR                  (CONFIG_SYS_IMMR + 0x2600000)
>  #define CONFIG_SYS_PCIE4_ADDR                  (CONFIG_SYS_IMMR + 0x2700000)
> -#ifdef CONFIG_ARCH_LS1088A
> +#ifdef CONFIG_ARCH_LX2160A
> +#define SYS_PCIE5_ADDR                         (CONFIG_SYS_IMMR + 0x2800000)
> +#define SYS_PCIE6_ADDR                         (CONFIG_SYS_IMMR + 0x2900000)

ditto.

> +#endif
> +
> +#ifdef CONFIG_ARCH_LX2160A
> +#define CONFIG_SYS_PCIE1_PHYS_ADDR             0x8000000000ULL
> +#define CONFIG_SYS_PCIE2_PHYS_ADDR             0x8800000000ULL
> +#define CONFIG_SYS_PCIE3_PHYS_ADDR             0x9000000000ULL
> +#define CONFIG_SYS_PCIE4_PHYS_ADDR             0x9800000000ULL
> +#define SYS_PCIE5_PHYS_ADDR                    0xa000000000ULL
> +#define SYS_PCIE6_PHYS_ADDR                    0xa800000000ULL
> +#elif CONFIG_ARCH_LS1088A
>  #define CONFIG_SYS_PCIE1_PHYS_ADDR             0x2000000000ULL
>  #define CONFIG_SYS_PCIE2_PHYS_ADDR             0x2800000000ULL
>  #define CONFIG_SYS_PCIE3_PHYS_ADDR             0x3000000000ULL
> --

Regards,
Bin