[U-Boot] [RESEND PATCHv4 2/9] armv8: lx2160a: add MMU table entries for PCIe

[Prabhakar Kushwaha]

> -----Original Message-----
> From: Z.q. Hou
> Sent: Monday, March 25, 2019 7:54 AM
> To: u-boot at lists.denx.de; albert.u.boot at aribaud.net; Priyanka Jain
> <priyanka.jain at nxp.com>; York Sun <york.sun at nxp.com>;
> sriram.dash at nxp.com; yamada.masahiro at socionext.com; Prabhakar
> Kushwaha <prabhakar.kushwaha at nxp.com>; Mingkai Hu
> <mingkai.hu at nxp.com>; M.h. Lian <minghuan.lian at nxp.com>;
> bmeng.cn at gmail.com
> Cc: Z.q. Hou <zhiqiang.hou at nxp.com>
> Subject: [RESEND PATCHv4 2/9] armv8: lx2160a: add MMU table entries for PCIe
> 
> From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> 
> The lx2160a have up to 6 PCIe controllers and have different address and size of
> PCIe region.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> ---
> V4:
>  - No change
> 
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c            | 12 ++++++++++++
>  arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |  2 ++
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  | 14 +++++++++++++-
>  3 files changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index 978d46b32f..2805e5f6f2 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -257,6 +257,18 @@ static struct mm_region final_map[] = {
>  	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
>  	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
>  	},
> +#endif
> +#ifdef CONFIG_ARCH_LX2160A

Request to avoid SoC name in #ifdef. Use #ifdef SYS_PCIE5_PHYS_ADDR,

--pk