[U-Boot] [PATCH v5 098/101] x86: apl: Add Kconfig and Makefile

[Bin Meng]

Hi Simon,

On Mon, Nov 25, 2019 at 12:12 PM Simon Glass <sjg at chromium.org> wrote:
>
> Add basic plumbing to allow Apollo Lake support to be used.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> Changes in v5:
> - Enable SMP
>
> Changes in v4:
> - Enable HAVE_X86_FIT
> - Enable INTEL_GPIO
> - Switch over to use pinctrl for pad init/config
> - Use existing VBT Kconfig option
> - apollolake -> Apollo Lake
>
> Changes in v3:
> - Add MMC, video, USB configs
> - Add an APL_SPI_FLASH_BOOT option to enable non-mmap boot
> - Fix the incorrect value of CPU_ADDR_BITS
>
> Changes in v2: None
>
>  arch/x86/Kconfig                |  1 +
>  arch/x86/cpu/Makefile           |  1 +
>  arch/x86/cpu/apollolake/Kconfig | 87 +++++++++++++++++++++++++++++++++
>  3 files changed, 89 insertions(+)
>  create mode 100644 arch/x86/cpu/apollolake/Kconfig
>
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index ae96e69f86..54ad934172 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -106,6 +106,7 @@ source "board/google/Kconfig"
>  source "board/intel/Kconfig"
>
>  # platform-specific options below
> +source "arch/x86/cpu/apollolake/Kconfig"
>  source "arch/x86/cpu/baytrail/Kconfig"
>  source "arch/x86/cpu/braswell/Kconfig"
>  source "arch/x86/cpu/broadwell/Kconfig"
> diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
> index 0e90a38dc5..5b40838e60 100644
> --- a/arch/x86/cpu/Makefile
> +++ b/arch/x86/cpu/Makefile
> @@ -41,6 +41,7 @@ extra-y += call32.o
>  endif
>
>  obj-y += intel_common/
> +obj-$(CONFIG_INTEL_APOLLOLAKE) += apollolake/
>  obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
>  obj-$(CONFIG_INTEL_BRASWELL) += braswell/
>  obj-$(CONFIG_INTEL_BROADWELL) += broadwell/
> diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig
> new file mode 100644
> index 0000000000..7dc50d1729
> --- /dev/null
> +++ b/arch/x86/cpu/apollolake/Kconfig
> @@ -0,0 +1,87 @@
> +# SPDX-License-Identifier: GPL-2.0
> +#
> +# Copyright 2019 Google LLC
> +#
> +
> +config INTEL_APOLLOLAKE
> +       bool
> +       select FSP_VERSION2
> +       select HAVE_FSP
> +       select ARCH_MISC_INIT
> +       select USE_CAR
> +       select INTEL_PMC
> +       select TPL_X86_TSC_TIMER_NATIVE
> +       select SPL_PCH_SUPPORT
> +       select TPL_PCH_SUPPORT
> +       select PCH_SUPPORT
> +       select P2SB
> +       imply ENABLE_MRC_CACHE
> +       imply AHCI_PCI
> +       imply SCSI
> +       imply SCSI_AHCI
> +       imply SPI_FLASH
> +       imply USB
> +       imply USB_EHCI_HCD
> +       imply TPL
> +       imply SPL
> +       imply TPL_X86_16BIT_INIT
> +       imply TPL_OF_PLATDATA
> +       imply ACPI_PMC
> +       imply MMC
> +       imply DM_MMC
> +       imply MMC_PCI
> +       imply MMC_SDHCI
> +       imply CMD_MMC
> +       imply VIDEO_FSP
> +       imply PINCTRL_INTEL
> +       imply PINCTRL_INTEL_APL
> +       imply HAVE_VBT
> +       imply HAVE_X86_FIT
> +       imply INTEL_GPIO
> +       imply SMP
> +
> +if INTEL_APOLLOLAKE
> +
> +config DCACHE_RAM_BASE
> +       default 0xfef00000
> +
> +config DCACHE_RAM_SIZE
> +       default 0xc0000
> +
> +config DCACHE_RAM_MRC_VAR_SIZE
> +       default 0xb0000
> +
> +config CPU_SPECIFIC_OPTIONS
> +       def_bool y
> +       select SMM_TSEG

SMM_TSEG isn't defined anywhere?

> +       select X86_RAMTEST
> +
> +config SMM_TSEG_SIZE
> +       hex
> +       default 0x800000
> +
> +config MMCONF_BASE_ADDRESS
> +       hex
> +       default 0xe0000000
> +
> +config TPL_SIZE_LIMIT
> +       default 0x7800
> +
> +config CPU_ADDR_BITS
> +       default 39
> +
> +config APL_SPI_FLASH_BOOT
> +       bool "Support booting with SPI-flash driver instead memory-mapped SPI"
> +       select TPL_SPI_FLASH_SUPPORT
> +       select TPL_SPI_SUPPORT
> +       help
> +         If you want to set BOOT_FROM_FAST_SPI_FLASH to true, enable this
> +         option. It enables SPI and SPI flash in TPL. Without the this only
> +         available boot method is to use memory-mapped SPI. Since this is
> +         actually fast and produces a TPL which is 7KB smaller, it is the
> +         default.
> +
> +config VBT_ADDR
> +       default 0xff3f1000
> +
> +endif
> --

Regards,
Bin