[PATCH 0/4] Fixes for RISC-V U-Boot SPL / OpenSBI boot flow

[Lukas Auer]

Rick's recent patch series, which adds support for U-Boot SPL to the
Andes platform, brought several problems of the current U-Boot SPL boot
flow on RISC-V to light. Discussion on the relevant parts starts at [1].

The problem showed itself in the form of code corruption. At start,
OpenSBI relocates itself to its link address. This allows it to be
loaded independently of the link address. In the case that the link
address ranges of U-Boot SPL and OpenSBI overlap, code corruption occurs
if the relocation starts while some harts are still running U-Boot SPL.
This series prevents this problem by specifying the hart that performs
the relocation and then making sure that it is the last hart to enter
OpenSBI, allowing relocation to be completed safely. A recent version of
OpenSBI is required for the changes to work.

This patch series resolves the problems associated with the use case of
overlapping link address ranges. However, it is still recommended to
select non-overlapping ranges for U-Boot SPL and OpenSBI.

[1]: https://lists.denx.de/pipermail/u-boot/2019-November/389385.html


Lukas Auer (4):
  spl: opensbi: specify main hart as preferred boot hart
  riscv: add functions for reading the IPI status
  riscv: add option to wait for ack from secondary harts in smp
    functions
  spl: opensbi: wait for ack from secondary harts before entering
    OpenSBI

 arch/riscv/cpu/start.S        |  2 ++
 arch/riscv/include/asm/smp.h  |  3 ++-
 arch/riscv/lib/andes_plic.c   |  9 ++++++++
 arch/riscv/lib/bootm.c        |  2 +-
 arch/riscv/lib/sbi_ipi.c      | 11 +++++++++
 arch/riscv/lib/sifive_clint.c |  9 ++++++++
 arch/riscv/lib/smp.c          | 43 +++++++++++++++++++++++++++--------
 arch/riscv/lib/spl.c          |  2 +-
 common/spl/spl_opensbi.c      | 13 ++++++++++-
 include/opensbi.h             | 18 ++++++++++++++-
 10 files changed, 98 insertions(+), 14 deletions(-)

-- 
2.21.0