[U-Boot] [EXT] Re: [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode

Xiaowei Bao xiaowei.bao at nxp.com
Wed Dec 4 03:23:32 CET 2019



> -----Original Message-----
> From: Ramon Fried <rfried.dev at gmail.com>
> Sent: 2019年12月4日 4:01
> To: Xiaowei Bao <xiaowei.bao at nxp.com>
> Cc: Ramon Fried <ramon.fried at gmail.com>; Hongbo Wang
> <hongbo.wang at nxp.com>; u-boot at lists.denx.de; York Sun
> <york.sun at nxp.com>; Z.q. Hou <zhiqiang.hou at nxp.com>; Mingkai Hu
> <mingkai.hu at nxp.com>
> Subject: Re: [U-Boot] [EXT] Re: [PATCHv2 1/2] PCI: layerscape: Add Support
> for ls2088 PCIe EP mode
> 
> On Tue, Dec 3, 2019 at 4:32 AM Xiaowei Bao <xiaowei.bao at nxp.com> wrote:
> >
> > Hi Ramon,
> >
> > Do you have any comments about this? Thanks a lot.
> >
> > Best regards
> > Xiaowei
> >
> > From: Xiaowei Bao
> > Sent: 2019年11月26日 10:52
> > To: Ramon Fried <ramon.fried at gmail.com>
> > Cc: Bin Meng <bmeng.cn at gmail.com>; Simon Glass <sjg at chromium.org>;
> > M.h. Lian <minghuan.lian at nxp.com>; Z.q. Hou <zhiqiang.hou at nxp.com>;
> > Mingkai Hu <mingkai.hu at nxp.com>; Hongbo Wang
> <hongbo.wang at nxp.com>;
> > York Sun <york.sun at nxp.com>; u-boot at lists.denx.de
> > Subject: RE: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add
> > Support for ls2088 PCIe EP mode
> >
> > H Ramon,
> >
> > Thanks for your comments.
> > If we reimplement the PCIe EP driver base on PCIe UCLASS, we must test it
> in u-boot, but I have no idea how to test the actual device, do I need to
> implement our own test case, how to verify the cadence-ep actual device?
> >
> I'm not sure I understand what you're trying to achieve and why you're
> referring to the cadence.
> You're developing a driver, just test it against a client (IE. a real PCIe
> root-complex).
> The cadence is irrelevant, it's just another implementation of endpoint driver.

Thanks for your comments, do you mean that we can use the 'pci' and 'md' command
of u-boot to test the EP device when the controller which work as a EP device connect 
to a RC port, we can access the BAR base on the "pci header" command, yes? but if I want
to test memory access from EP to RC, what should I do, because there is not a command
which similar to 'pci' to test.

Another issue is that, due to the history reason of Layerscape PCIe controller driver, the
EP and RC codes are combined, if I separate the EP and RC code, there will have many
duplicate code.

Thanks
Xiaowei 


 
> Thanks,
> Ramon.
> > Best regards
> > Xiaowei
> > U-Boot at lists.denx.de
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