[PATCH v6 056/102] x86: Add an option to control the position of U-Boot

[Simon Glass]

The existing work-around for positioning U-Boot in the ROM when it
actually runs from RAM still exists and there is not obvious way to change
this.

Add a proper Kconfig option to handle this case. This also adds a new bool
property to indicate whether CONFIG_SYS_TEXT_BASE exists.

Signed-off-by: Simon Glass <sjg at chromium.org>
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
---

Changes in v6: None
Changes in v5: None
Changes in v4:
- Rename option to HAVE_SYS_TEXT_BASE

Changes in v3: None
Changes in v2: None

 Kconfig                                |  9 ++++++---
 arch/x86/Kconfig                       |  5 +++++
 arch/x86/dts/u-boot.dtsi               | 18 +++---------------
 configs/chromebook_samus_tpl_defconfig |  1 +
 configs/qemu-x86_64_defconfig          |  1 +
 5 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/Kconfig b/Kconfig
index 92fc4fc135..46a31f45b9 100644
--- a/Kconfig
+++ b/Kconfig
@@ -545,9 +545,14 @@ config SYS_EXTRA_OPTIONS
 	  configuration to Kconfig. Since this option will be removed sometime,
 	  new boards should not use this option.
 
-config SYS_TEXT_BASE
+config HAVE_SYS_TEXT_BASE
+	bool
 	depends on !NIOS2 && !XTENSA
 	depends on !EFI_APP
+	default y
+
+config SYS_TEXT_BASE
+	depends on HAVE_SYS_TEXT_BASE
 	default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
 	default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S
 	default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I
@@ -556,8 +561,6 @@ config SYS_TEXT_BASE
 	help
 	  The address in memory that U-Boot will be running from, initially.
 
-
-
 config SYS_CLK_FREQ
 	depends on ARC || ARCH_SUNXI || MPC83xx
 	int "CPU clock frequency"
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 64f167306b..9d7ff3c07a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -899,4 +899,9 @@ config CACHE_QOS_SIZE_PER_BIT
 	depends on INTEL_CAR_CQOS
 	default 0x20000 # 128 KB
 
+config X86_OFFSET_U_BOOT
+	hex "Offset of U-Boot in ROM image"
+	depends on HAVE_SYS_TEXT_BASE
+	default SYS_TEXT_BASE
+
 endmenu
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 14e3c13072..d84c64880a 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -50,7 +50,7 @@
 	u-boot-spl-dtb {
 	};
 	u-boot {
-		offset = <CONFIG_SYS_TEXT_BASE>;
+		offset = <CONFIG_X86_OFFSET_U_BOOT>;
 	};
 #elif defined(CONFIG_SPL)
 	u-boot-spl-with-ucode-ptr {
@@ -60,23 +60,11 @@
 		type = "u-boot-dtb-with-ucode";
 	};
 	u-boot {
-		/*
-		 * TODO(sjg at chromium.org):
-		 * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
-		 * for boards with textbase in SDRAM we cannot do this. Just use
-		 * an assumed-valid value (1MB before the end of flash) here so
-		 * that we can actually build an image for coreboot, etc.
-		 * We need a better solution, perhaps a separate Kconfig.
-		 */
-#if CONFIG_SYS_TEXT_BASE == 0x1110000
-		offset = <0xfff00000>;
-#else
-		offset = <CONFIG_SYS_TEXT_BASE>;
-#endif
+		offset = <CONFIG_X86_OFFSET_U_BOOT>;
 	};
 #else
 	u-boot-with-ucode-ptr {
-		offset = <CONFIG_SYS_TEXT_BASE>;
+		offset = <CONFIG_X86_OFFSET_U_BOOT>;
 	};
 #endif
 #ifdef CONFIG_HAVE_MICROCODE
diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig
index 5ef2ecb1c4..74b7e9a207 100644
--- a/configs/chromebook_samus_tpl_defconfig
+++ b/configs/chromebook_samus_tpl_defconfig
@@ -16,6 +16,7 @@ CONFIG_HAVE_REFCODE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_SPL_TEXT_BASE=0xffe70000
+CONFIG_X86_OFFSET_U_BOOT=0xfff00000
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_SHOW_BOOT_PROGRESS=y
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index b88a4c57fe..a37ec4d0d6 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -13,6 +13,7 @@ CONFIG_SMP=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_X86_OFFSET_U_BOOT=0xfff00000
 CONFIG_SPL_TEXT_BASE=0xfffd0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BUILD_ROM=y
-- 
2.24.0.393.g34dc348eaf-goog