[PATCH v6 098/102] x86: apl: Add P2SB driver

[Simon Glass]

Hi Bin,

On Sun, 8 Dec 2019 at 01:39, Bin Meng <bmeng.cn at gmail.com> wrote:
>
> Hi Simon,
>
> On Sat, Dec 7, 2019 at 12:54 PM Simon Glass <sjg at chromium.org> wrote:
> >
> > Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports
> > various child devices. It supposed both device tree and of-platdata.
> >
> > Signed-off-by: Simon Glass <sjg at chromium.org>
> > ---
> >
> > Changes in v6: None
> > Changes in v5: None
> > Changes in v4:
> > - Detect zero mmio address
> > - Use BIT() macro bit more
> > - apollolake -> Apollo Lake
> >
> > Changes in v3:
> > - Use pci_get_devfn()
> >
> > Changes in v2: None
> >
> >  arch/x86/cpu/apollolake/Makefile |   1 +
> >  arch/x86/cpu/apollolake/p2sb.c   | 167 +++++++++++++++++++++++++++++++
> >  2 files changed, 168 insertions(+)
> >  create mode 100644 arch/x86/cpu/apollolake/p2sb.c
> >
> > diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
> > index edde122f75..dc6df15dab 100644
> > --- a/arch/x86/cpu/apollolake/Makefile
> > +++ b/arch/x86/cpu/apollolake/Makefile
> > @@ -15,6 +15,7 @@ endif
> >  obj-y += hostbridge.o
> >  obj-y += itss.o
> >  obj-y += lpc.o
> > +obj-y += p2sb.o
> >  obj-y += pch.o
> >  obj-y += pmc.o
> >  obj-y += uart.o
> > diff --git a/arch/x86/cpu/apollolake/p2sb.c b/arch/x86/cpu/apollolake/p2sb.c
> > new file mode 100644
> > index 0000000000..0a5deaf4a0
> > --- /dev/null
> > +++ b/arch/x86/cpu/apollolake/p2sb.c
> > @@ -0,0 +1,167 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Primary-to-Sideband Bridge
> > + *
> > + * Copyright 2019 Google LLC
> > + */
> > +
> > +#define LOG_CATEGORY UCLASS_P2SB
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <dt-structs.h>
> > +#include <p2sb.h>
> > +#include <spl.h>
> > +#include <asm/pci.h>
> > +
> > +struct p2sb_platdata {
> > +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> > +       struct dtd_intel_apl_p2sb dtplat;
> > +#endif
> > +       ulong mmio_base;
> > +       pci_dev_t bdf;
> > +};
> > +
> > +/* PCI config space registers */
> > +#define HPTC_OFFSET            0x60
> > +#define HPTC_ADDR_ENABLE_BIT   BIT(7)
> > +
> > +/* High Performance Event Timer Configuration */
> > +#define P2SB_HPTC                              0x60
> > +#define P2SB_HPTC_ADDRESS_ENABLE               BIT(7)
> > +
> > +/*
> > + * ADDRESS_SELECT            ENCODING_RANGE
> > + *      0                 0xfed0 0000 - 0xfed0 03ff
> > + *      1                 0xfed0 1000 - 0xfed0 13ff
> > + *      2                 0xfed0 2000 - 0xfed0 23ff
> > + *      3                 0xfed0 3000 - 0xfed0 33ff
> > + */
> > +#define P2SB_HPTC_ADDRESS_SELECT_0             (0 << 0)
> > +#define P2SB_HPTC_ADDRESS_SELECT_1             (1 << 0)
> > +#define P2SB_HPTC_ADDRESS_SELECT_2             (2 << 0)
> > +#define P2SB_HPTC_ADDRESS_SELECT_3             (3 << 0)
> > +
> > +/*
> > + * apl_p2sb_early_init() - Enable decoding for HPET range
> > + *
> > + * This is needed for FspMemoryInit to store and retrieve a global data
> > + * pointer
>
> Looks my comment in the v5 series was not addressed.
> See https://lists.denx.de/pipermail/u-boot/2019-December/392392.html

OK. I am not really sure what the FSP is doing here, but it apparently
does need HPET set up.

I'll update the comment to just say it is needed by FSP-M.

Regards,
Simon