[PATCH] i2c: i2c_cdns: fix write timeout on fifo boundary

Heiko Schocher hs at denx.de
Wed Dec 11 11:43:51 CET 2019


Hello Michael,

Am 09.12.2019 um 19:16 schrieb Michael Auchter:
> This fixes an issue that would cause I2C writes to timeout when the
> number of bytes is a multiple of the FIFO depth (i.e. 16 bytes).
> 
> Within the transfer loop, after writing the data register with a new
> byte to transfer, if the transfer size equals the FIFO depth, the loop
> pauses until the INTERRUPT_COMP bit asserts to indicate data has been
> sent. This same check is performed after the loop as well to ensure data
> has been transferred prior to returning.
> 
> In the case where the amount of data to be written is a multiple of the
> FIFO depth, the transfer loop would wait for the INTERRUPT_COMP bit to
> assert after writing the final byte, and then wait for this bit to
> assert once more. However, since the transfer has finished at this
> point, no new data has been written to the data register, and hence
> INTERRUPT_COMP will never assert.
> 
> Fix this by only waiting for INTERRUPT_COMP in the transfer loop if
> there's still data to be written.
> 
> Signed-off-by: Michael Auchter <michael.auchter at ni.com>
> ---
>   drivers/i2c/i2c-cdns.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Thanks!

Applied to u-boot-i2c master

bye,
Heiko
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: hs at denx.de


More information about the U-Boot mailing list