[PATCHv2 1/2] arm: socfpga: stratix10: Enable SMMU access

[Tan, Ley Foon]

> -----Original Message-----
> From: thor.thayer at linux.intel.com <thor.thayer at linux.intel.com>
> Sent: Saturday, December 7, 2019 3:48 AM
> To: marex at denx.de; simon.k.r.goldschmidt at gmail.com; Tan, Ley Foon
> <ley.foon.tan at intel.com>
> Cc: albert.u.boot at aribaud.net; Ang, Chee Hong
> <chee.hong.ang at intel.com>; Chee, Tien Fong <tien.fong.chee at intel.com>;
> u-boot at lists.denx.de; Thor Thayer <thor.thayer at linux.intel.com>
> Subject: [PATCHv2 1/2] arm: socfpga: stratix10: Enable SMMU access
> 
> From: Thor Thayer <thor.thayer at linux.intel.com>
> 
> Enable TCU access through the Stratix10 CCU so that the SMMU can access
> the SDRAM.
> 
> Signed-off-by: Thor Thayer <thor.thayer at linux.intel.com>

Reviewed-by: Ley Foon Tan <ley.foon.tan at intel.com>

> ---
> v2 Rebase patch on top of pending patchset
>    [PATCH v8 00/19] Add Intel Agilex SoC support
>    https://patchwork.ozlabs.org/cover/1201373/
> ---
>  arch/arm/mach-socfpga/include/mach/firewall.h |  7 +++++++
>  drivers/ddr/altera/sdram_s10.c                | 14 ++++++++++++++
>  2 files changed, 21 insertions(+)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h
> b/arch/arm/mach-socfpga/include/mach/firewall.h
> index 516bd1c0e1ec..430341bea14c 100644
> --- a/arch/arm/mach-socfpga/include/mach/firewall.h
> +++ b/arch/arm/mach-socfpga/include/mach/firewall.h
> @@ -95,6 +95,13 @@ struct socfpga_firwall_l4_sys {
> 
>  #define CCU_IOM_MPRT_ADMASK_MEM_RAM0		0x18628
> 
> +#define CCU_TCU_MPRT_ADBASE_MEMSPACE0		0x2c520
> +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1A		0x2c540
> +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1B		0x2c560
> +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1C		0x2c580
> +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1D		0x2c5a0
> +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1E		0x2c5c0
> +
>  #define CCU_ADMASK_P_MASK			BIT(0)
>  #define CCU_ADMASK_NS_MASK			BIT(1)
> 
> diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
> index fcab3ae3e4ba..a7bf82e4e5ce 100644
> --- a/drivers/ddr/altera/sdram_s10.c
> +++ b/drivers/ddr/altera/sdram_s10.c
> @@ -104,6 +104,20 @@ int sdram_mmr_init_full(struct udevice *dev)
> 
> 	clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE
> 1E),
>  		     CCU_ADBASE_DI_MASK);
> 
> +	/* Enable access to DDR from TCU */
> +
> 	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE
> 0),
> +		     CCU_ADBASE_DI_MASK);
> +
> 	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE
> 1A),
> +		     CCU_ADBASE_DI_MASK);
> +
> 	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE
> 1B),
> +		     CCU_ADBASE_DI_MASK);
> +
> 	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE
> 1C),
> +		     CCU_ADBASE_DI_MASK);
> +
> 	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE
> 1D),
> +		     CCU_ADBASE_DI_MASK);
> +
> 	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE
> 1E),
> +		     CCU_ADBASE_DI_MASK);
> +
>  	/* this enables nonsecure access to DDR */
>  	/* mpuregion0addr_limit */
>  	FW_MPU_DDR_SCR_WRITEL(0xFFFF0000,
> FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
> --
> 2.7.4