[PATCH 6/6] Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage
Yangbo Lu
yangbo.lu at nxp.com
Thu Dec 19 11:59:30 CET 2019
The eSDHC reference clocks should be provided by speed.c in arch/.
And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to
select which clock to use. Because we can make the driver to select
the periperhal clock which is better (provides higher frequency)
automatically if its value is provided by speed.c.
This patch is to drop this option and make driver to select clock
automatically. Also fix peripheral clock calculation issue in
fsl_lsch2_speed.c/fsl_lsch3_speed.c.
Signed-off-by: Yangbo Lu <yangbo.lu at nxp.com>
---
.../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 29 +++++++-------------
.../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 22 +++++++--------
drivers/mmc/Kconfig | 9 ------
drivers/mmc/fsl_esdhc.c | 32 +++++++++++++++-------
4 files changed, 42 insertions(+), 50 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 25e9a49..fec2318 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -125,7 +125,6 @@ void get_sys_info(struct sys_info *sys_info)
}
#endif
-#ifdef CONFIG_FSL_ESDHC
#define HWA_CGA_M2_CLK_SEL 0x00000007
#define HWA_CGA_M2_CLK_SHIFT 0
#if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB)
@@ -148,11 +147,10 @@ void get_sys_info(struct sys_info *sys_info)
break;
#endif
default:
- printf("Error: Unknown peripheral clock select!\n");
+ printf("Error: Unknown cluster group A mux 2 clock select!\n");
break;
}
#endif
-#endif
#if defined(CONFIG_FSL_IFC)
sys_info->freq_localbus = sys_info->freq_systembus /
@@ -179,28 +177,21 @@ unsigned long get_qman_freq(void)
int get_clocks(void)
{
struct sys_info sys_info;
-
+#ifdef CONFIG_FSL_ESDHC
+ u32 clock = 0;
+#endif
get_sys_info(&sys_info);
gd->cpu_clk = sys_info.freq_processor[0];
gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
gd->mem_clk = sys_info.freq_ddrbus;
-
#ifdef CONFIG_FSL_ESDHC
-#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
-#if defined(CONFIG_TARGET_LS1046ARDB)
- gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
-#endif
-#if defined(CONFIG_TARGET_LS1043ARDB)
- gd->arch.sdhc_clk = sys_info.freq_cga_m2;
-#endif
-#if defined(CONFIG_TARGET_LS1012ARDB)
- gd->arch.sdhc_clk = sys_info.freq_systembus;
-#endif
-#else
- gd->arch.sdhc_clk = (sys_info.freq_systembus /
- CONFIG_SYS_FSL_PCLK_DIV) /
- CONFIG_SYS_FSL_SDHC_CLK_DIV;
+#if defined(CONFIG_ARCH_LS1012A)
+ clock = sys_info.freq_systembus;
+#elif defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ clock = sys_info.freq_cga_m2;
#endif
+ gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
+ gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
#endif
if (gd->cpu_clk != 0)
return 0;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index 4b047a3..bd8b9cb 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -160,14 +160,14 @@ void get_sys_info(struct sys_info *sys_info)
break;
}
#endif
-#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A)
- sys_info->freq_cga_m2 = sys_info->freq_systembus;
-#endif
}
int get_clocks(void)
{
struct sys_info sys_info;
+#ifdef CONFIG_FSL_ESDHC
+ u32 clock = 0;
+#endif
get_sys_info(&sys_info);
gd->cpu_clk = sys_info.freq_processor[0];
gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
@@ -175,18 +175,16 @@ int get_clocks(void)
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
gd->arch.mem2_clk = sys_info.freq_ddrbus2;
#endif
-#if defined(CONFIG_FSL_ESDHC)
-#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
-#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
- gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
-#endif
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
- gd->arch.sdhc_clk = sys_info.freq_cga_m2;
+
+#ifdef CONFIG_FSL_ESDHC
+#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
+ clock = sys_info.freq_cga_m2;
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A)
+ clock = sys_info.freq_systembus;
#endif
-#else
+ gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
#endif
-#endif /* defined(CONFIG_FSL_ESDHC) */
if (gd->cpu_clk != 0)
return 0;
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 85fd190..f0d33d1 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -711,19 +711,10 @@ endif
config FSL_ESDHC
bool "Freescale/NXP eSDHC controller support"
- select FSL_ESDHC_USE_PERIPHERAL_CLK if MMC_HS200_SUPPORT || MMC_UHS_SUPPORT
help
This selects support for the eSDHC (Enhanced Secure Digital Host
Controller) found on numerous Freescale/NXP SoCs.
-config FSL_ESDHC_USE_PERIPHERAL_CLK
- bool "enable ESDHC peripheral clock support"
- depends on FSL_ESDHC
- help
- eSDHC supports two reference clocks (platform clock and peripheral clock).
- Peripheral clock which could provide higher clock frequency is required to
- be used for tuning of SD UHS mode and eMMC HS200/HS400 modes.
-
config FSL_ESDHC_IMX
bool "Freescale/NXP i.MX eSDHC controller support"
help
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 8655503..112f115 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -81,6 +81,7 @@ struct fsl_esdhc_plat {
struct fsl_esdhc_priv {
struct fsl_esdhc *esdhc_regs;
unsigned int sdhc_clk;
+ bool is_sdhc_per_clk;
unsigned int clock;
#if !CONFIG_IS_ENABLED(DM_MMC)
struct mmc *mmc;
@@ -523,7 +524,6 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
}
-#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
{
struct fsl_esdhc *regs = priv->esdhc_regs;
@@ -550,18 +550,18 @@ static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
mdelay(1);
}
}
-#endif
static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
{
struct fsl_esdhc *regs = priv->esdhc_regs;
-#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
- /* Select to use peripheral clock */
- esdhc_clock_control(priv, false);
- esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS);
- esdhc_clock_control(priv, true);
-#endif
+ if (priv->is_sdhc_per_clk) {
+ /* Select to use peripheral clock */
+ esdhc_clock_control(priv, false);
+ esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS);
+ esdhc_clock_control(priv, true);
+ }
+
/* Set the clock speed */
if (priv->clock != mmc->clock)
set_sysctl(priv, mmc, mmc->clock);
@@ -779,6 +779,8 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
priv->sdhc_clk = cfg->sdhc_clk;
+ if (gd->arch.sdhc_per_clk)
+ priv->is_sdhc_per_clk = true;
mmc_cfg = &plat->cfg;
@@ -817,7 +819,11 @@ int fsl_esdhc_mmc_init(bd_t *bis)
cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
- cfg->sdhc_clk = gd->arch.sdhc_clk;
+ /* Prefer peripheral clock which provides higher frequency. */
+ if (gd->arch.sdhc_per_clk)
+ cfg->sdhc_clk = gd->arch.sdhc_per_clk;
+ else
+ cfg->sdhc_clk = gd->arch.sdhc_clk;
return fsl_esdhc_initialize(bis, cfg);
}
#else /* DM_MMC */
@@ -839,7 +845,13 @@ static int fsl_esdhc_probe(struct udevice *dev)
#endif
priv->dev = dev;
- priv->sdhc_clk = gd->arch.sdhc_clk;
+ if (gd->arch.sdhc_per_clk) {
+ priv->sdhc_clk = gd->arch.sdhc_per_clk;
+ priv->is_sdhc_per_clk = true;
+ } else {
+ priv->sdhc_clk = gd->arch.sdhc_clk;
+ }
+
if (priv->sdhc_clk <= 0) {
dev_err(dev, "Unable to get clk for %s\n", dev->name);
return -EINVAL;
--
2.7.4
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