[U-Boot] [PATCH] imx: sync with kernel device tree for Phycore SoM
Parthiban Nallathambi
parthitce at gmail.com
Fri Dec 20 16:49:16 CET 2019
Hello Stefano,
Ping on this patch.
On 11/5/19 2:37 AM, Peng Fan wrote:
>> Subject: [PATCH] imx: sync with kernel device tree for Phycore SoM
>>
>> Sync the Linux Kernel 5.4-rc6 device tree for Phytec Phycore SoM and Segin
>> board based on imx6UL and imx6ULL.
>>
>> Changes includes Phytec naming convention for the devicetree files.
>>
>> Signed-off-by: Parthiban Nallathambi <parthitce at gmail.com>
>
> Acked-by: Peng Fan <peng.fan at nxp.com>
>
>> ---
>> arch/arm/dts/Makefile | 4 +-
>> arch/arm/dts/imx6ul-phycore-segin.dts | 81 ----
>> ...on.dtsi => imx6ul-phytec-phycore-som.dtsi} | 130 +++----
>> .../dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 93 +++++
>> .../dts/imx6ul-phytec-segin-peb-eval-01.dtsi | 57 +++
>> arch/arm/dts/imx6ul-phytec-segin.dtsi | 346
>> ++++++++++++++++++
>> arch/arm/dts/imx6ull-phycore-segin.dts | 70 ----
>> arch/arm/dts/imx6ull-phytec-phycore-som.dtsi | 24
>> ++ .../dts/imx6ull-phytec-segin-ff-rdk-emmc.dts | 93
>> +++++ .../dts/imx6ull-phytec-segin-peb-eval-01.dtsi | 19 +
>> arch/arm/dts/imx6ull-phytec-segin.dtsi | 38 ++
>> board/phytec/pcl063/MAINTAINERS | 12 +-
>> configs/phycore_pcl063_defconfig | 3 +-
>> configs/phycore_pcl063_ull_defconfig | 2 +-
>> 14 files changed, 732 insertions(+), 240 deletions(-) delete mode 100644
>> arch/arm/dts/imx6ul-phycore-segin.dts
>> rename arch/arm/dts/{pcl063-common.dtsi =>
>> imx6ul-phytec-phycore-som.dtsi} (56%) create mode 100644
>> arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
>> create mode 100644 arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
>> create mode 100644 arch/arm/dts/imx6ul-phytec-segin.dtsi
>> delete mode 100644 arch/arm/dts/imx6ull-phycore-segin.dts
>> create mode 100644 arch/arm/dts/imx6ull-phytec-phycore-som.dtsi
>> create mode 100644 arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
>> create mode 100644 arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
>> create mode 100644 arch/arm/dts/imx6ull-phytec-segin.dtsi
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
>> 47978e7685..935b661284 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -621,14 +621,14 @@ dtb-$(CONFIG_MX6UL) += \
>> imx6ul-9x9-evk.dtb \
>> imx6ul-9x9-evk.dtb \
>> imx6ul-liteboard.dtb \
>> - imx6ul-phycore-segin.dtb \
>> + imx6ul-phytec-segin-ff-rdk-nand.dtb \
>> imx6ul-pico-hobbit.dtb \
>> imx6ul-pico-pi.dtb
>>
>> dtb-$(CONFIG_MX6ULL) += \
>> imx6ull-14x14-evk.dtb \
>> imx6ull-colibri.dtb \
>> - imx6ull-phycore-segin.dtb \
>> + imx6ull-phytec-segin-ff-rdk-emmc.dtb \
>> imx6ull-dart-6ul.dtb \
>> imx6ulz-14x14-evk.dtb
>>
>> diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts
>> b/arch/arm/dts/imx6ul-phycore-segin.dts
>> deleted file mode 100644
>> index 7d68bf8430..0000000000
>> --- a/arch/arm/dts/imx6ul-phycore-segin.dts
>> +++ /dev/null
>> @@ -1,81 +0,0 @@
>> -// SPDX-License-Identifier: GPL-2.0+
>> -/*
>> - * Copyright (C) 2018 Collabora Ltd.
>> - *
>> - * Based on dts[i] from Phytec barebox port:
>> - * Copyright (C) 2016 PHYTEC Messtechnik GmbH
>> - * Author: Christian Hemp <c.hemp at phytec.de>
>> - *
>> - * The code contained herein is licensed under the GNU General Public
>> - * License. You may obtain a copy of the GNU General Public License
>> - * Version 2 or later at the following locations:
>> - *
>> - *
>> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.o
>> pensource.org%2Flicenses%2Fgpl-license.html&data=02%7C01%7Cpeng
>> .fan%40nxp.com%7Cb5436c55ac684a693cf308d76157d5a3%7C686ea1d3bc
>> 2b4c6fa92cd99c5c301635%7C0%7C1%7C637084902183324601&sdata
>> =3jSUWElygGkm68v%2BnCz%2BoNJDlFgqGFQ5TtHXR3ZrkhE%3D&reser
>> ved=0
>> - *
>> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.g
>> nu.org%2Fcopyleft%2Fgpl.html&data=02%7C01%7Cpeng.fan%40nxp.co
>> m%7Cb5436c55ac684a693cf308d76157d5a3%7C686ea1d3bc2b4c6fa92cd99
>> c5c301635%7C0%7C1%7C637084902183324601&sdata=iUmn4qiL0Oyl
>> PygYqMtZB2MNoToAhppXpwdHwFFBdyQ%3D&reserved=0
>> - */
>> -
>> -/dts-v1/;
>> -
>> -#include "imx6ul.dtsi"
>> -#include "pcl063-common.dtsi"
>> -
>> -/ {
>> - model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
>> - compatible = "phytec,phyboard-imx6ul-segin", "phytec,imx6ul-pcl063",
>> - "fsl,imx6ul";
>> -};
>> -
>> -&gpmi {
>> - status = "okay";
>> -};
>> -
>> -&i2c1 {
>> - i2c_rtc: rtc at 68 {
>> - compatible = "microcrystal,rv4162";
>> - reg = <0x68>;
>> - status = "okay";
>> - };
>> -};
>> -
>> -&uart5 {
>> - pinctrl-names = "default";
>> - pinctrl-0 = <&pinctrl_uart5>;
>> - uart-has-rtscts;
>> - status = "okay";
>> -};
>> -
>> -&usbotg1 {
>> - pinctrl-names = "default";
>> - pinctrl-0 = <&pinctrl_usb_otg1_id>;
>> - dr_mode = "otg";
>> - srp-disable;
>> - hnp-disable;
>> - adp-disable;
>> - status = "okay";
>> -};
>> -
>> -&usbotg2 {
>> - dr_mode = "host";
>> - disable-over-current;
>> - status = "okay";
>> -};
>> -
>> -&iomuxc {
>> - pinctrl-names = "default";
>> -
>> - pinctrl_uart5: uart5grp {
>> - fsl,pins = <
>> - MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
>> - MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
>> - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
>> - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
>> - >;
>> - };
>> -
>> - pinctrl_usb_otg1_id: usbotg1idgrp {
>> - fsl,pins = <
>> - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>> - >;
>> - };
>> -
>> -};
>> diff --git a/arch/arm/dts/pcl063-common.dtsi
>> b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
>> similarity index 56%
>> rename from arch/arm/dts/pcl063-common.dtsi rename to
>> arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
>> index b88dde2fb0..c2a7c78779 100644
>> --- a/arch/arm/dts/pcl063-common.dtsi
>> +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
>> @@ -1,22 +1,35 @@
>> -// SPDX-License-Identifier: GPL-2.0+
>> +// SPDX-License-Identifier: GPL-2.0
>> /*
>> - * Copyright (C) 2018 Collabora Ltd.
>> - *
>> - * Based on dts[i] from Phytec barebox port:
>> * Copyright (C) 2016 PHYTEC Messtechnik GmbH
>> * Author: Christian Hemp <c.hemp at phytec.de>
>> */
>>
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/pwm/pwm.h>
>> +
>> / {
>> - model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
>> + model = "PHYTEC phyCORE-i.MX6 UltraLite";
>> compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
>>
>> + chosen {
>> + stdout-path = &uart1;
>> + };
>> +
>> memory {
>> + device_type = "memory";
>> reg = <0x80000000 0x20000000>;
>> };
>>
>> - chosen {
>> - stdout-path = &uart1;
>> + gpio_leds_som: leds {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_gpioleds_som>;
>> + compatible = "gpio-leds";
>> +
>> + phycore-green {
>> + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "heartbeat";
>> + };
>> };
>> };
>>
>> @@ -24,16 +37,21 @@
>> pinctrl-names = "default";
>> pinctrl-0 = <&pinctrl_enet1>;
>> phy-mode = "rmii";
>> - phy-handle = <ðphy0>;
>> - status = "okay";
>> + phy-handle = <ðphy1>;
>> + status = "disabled";
>>
>> mdio: mdio {
>> #address-cells = <1>;
>> #size-cells = <0>;
>>
>> - ethphy0: ethernet-phy at 1 {
>> + ethphy1: ethernet-phy at 1 {
>> reg = <1>;
>> + interrupt-parent = <&gpio1>;
>> + interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
>> micrel,led-mode = <1>;
>> + clocks = <&clks IMX6UL_CLK_ENET_REF>;
>> + clock-names = "rmii-ref";
>> + status = "disabled";
>> };
>> };
>> };
>> @@ -42,89 +60,61 @@
>> pinctrl-names = "default";
>> pinctrl-0 = <&pinctrl_gpmi_nand>;
>> nand-on-flash-bbt;
>> - fsl,no-blockmark-swap;
>> status = "disabled";
>> -
>> - #address-cells = <1>;
>> - #size-cells = <1>;
>> -
>> - partition at 0 {
>> - label = "uboot";
>> - reg = <0x0 0x400000>;
>> - };
>> -
>> - partition at 400000 {
>> - label = "uboot-env";
>> - reg = <0x400000 0x100000>;
>> - };
>> -
>> - partition at 500000 {
>> - label = "root";
>> - reg = <0x500000 0x0>;
>> - };
>> };
>>
>> &i2c1 {
>> - clock-frequency = <100000>;
>> - pinctrl-names = "default", "gpio";
>> + pinctrl-names = "default";
>> pinctrl-0 = <&pinctrl_i2c1>;
>> - pinctrl-1 = <&pinctrl_i2c1_gpio>;
>> - scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
>> - sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
>> + clock-frequency = <100000>;
>> status = "okay";
>>
>> eeprom at 52 {
>> - compatible = "cat,24c32";
>> + compatible = "catalyst,24c32", "atmel,24c32";
>> reg = <0x52>;
>> };
>> };
>>
>> -&uart1 {
>> - pinctrl-names = "default";
>> - pinctrl-0 = <&pinctrl_uart1>;
>> +&snvs_poweroff {
>> status = "okay";
>> };
>>
>> -&usdhc1 {
>> +&uart1 {
>> pinctrl-names = "default";
>> - pinctrl-0 = <&pinctrl_usdhc1>;
>> - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
>> - bus-width = <0x4>;
>> - pinctrl-0 = <&pinctrl_usdhc1>;
>> - no-1-8-v;
>> + pinctrl-0 = <&pinctrl_uart1>;
>> status = "okay";
>> };
>>
>> &usdhc2 {
>> - u-boot,dm-spl;
>> - u-boot,dm-pre-reloc;
>> pinctrl-names = "default";
>> pinctrl-0 = <&pinctrl_usdhc2>;
>> bus-width = <8>;
>> no-1-8-v;
>> non-removable;
>> - keep-power-in-suspend;
>> status = "disabled";
>> };
>>
>> &iomuxc {
>> - pinctrl-names = "default";
>> -
>> pinctrl_enet1: enet1grp {
>> fsl,pins = <
>> - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
>> - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
>> + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010
>> + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10010
>> MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
>> MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
>> MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
>> MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
>> - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
>> - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
>> - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
>> - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1
>> 0x4001b031
>> + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
>> + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
>> + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
>> + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1
>> 0x4001b010
>> + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059
>> >;
>> };
>>
>> + pinctrl_gpioleds_som: gpioledssomgrp {
>> + fsl,pins = <MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04
>> 0x0b0b0>;
>> + };
>> +
>> pinctrl_gpmi_nand: gpminandgrp {
>> fsl,pins = <
>> MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
>> @@ -147,35 +137,15 @@
>>
>> pinctrl_i2c1: i2cgrp {
>> fsl,pins = <
>> - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL
>> 0x4001b8b0
>> - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA
>> 0x4001b8b0
>> - >;
>> - };
>> -
>> - pinctrl_i2c1_gpio: i2c1grp_gpio {
>> - fsl,pins = <
>> - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
>> - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
>> + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
>> + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
>> >;
>> };
>>
>> pinctrl_uart1: uart1grp {
>> fsl,pins = <
>> - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
>> - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>> - >;
>> - };
>> -
>> - pinctrl_usdhc1: usdhc1grp {
>> - fsl,pins = <
>> - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
>> - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
>> - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
>> - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
>> - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
>> - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>> - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
>> -
>> + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
>> + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>> >;
>> };
>>
>> @@ -191,7 +161,7 @@
>> MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
>> MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
>> MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>> - MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170f9
>> >;
>> };
>> +
>> };
>> diff --git a/arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
>> b/arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
>> new file mode 100644
>> index 0000000000..699dfcbf9a
>> --- /dev/null
>> +++ b/arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
>> @@ -0,0 +1,93 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2016 PHYTEC Messtechnik GmbH
>> + * Author: Christian Hemp <c.hemp at phytec.de> */
>> +
>> +/dts-v1/;
>> +#include "imx6ul.dtsi"
>> +#include "imx6ul-phytec-phycore-som.dtsi"
>> +#include "imx6ul-phytec-segin.dtsi"
>> +#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
>> +
>> +/ {
>> + model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with
>> NAND";
>> + compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10",
>> + "phytec,imx6ul-pcl063", "fsl,imx6ul"; };
>> +
>> +&adc1 {
>> + status = "okay";
>> +};
>> +
>> +&can1 {
>> + status = "okay";
>> +};
>> +
>> +&tlv320 {
>> + status = "okay";
>> +};
>> +
>> +&ecspi3 {
>> + status = "okay";
>> +};
>> +
>> +ðphy1 {
>> + status = "okay";
>> +};
>> +
>> +ðphy2 {
>> + status = "okay";
>> +};
>> +
>> +&fec1 {
>> + status = "okay";
>> +};
>> +
>> +&fec2 {
>> + status = "okay";
>> +};
>> +
>> +&gpmi {
>> + status = "okay";
>> +};
>> +
>> +&i2c_rtc {
>> + status = "okay";
>> +};
>> +
>> +®_can1_en {
>> + status = "okay";
>> +};
>> +
>> +®_sound_1v8 {
>> + status = "okay";
>> +};
>> +
>> +®_sound_3v3 {
>> + status = "okay";
>> +};
>> +
>> +&sai2 {
>> + status = "okay";
>> +};
>> +
>> +&sound {
>> + status = "okay";
>> +};
>> +
>> +&uart5 {
>> + status = "okay";
>> +};
>> +
>> +&usbotg1 {
>> + status = "okay";
>> +};
>> +
>> +&usbotg2 {
>> + status = "okay";
>> +};
>> +
>> +&usdhc1 {
>> + status = "okay";
>> +};
>> diff --git a/arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
>> b/arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
>> new file mode 100644
>> index 0000000000..2f3fd32a11
>> --- /dev/null
>> +++ b/arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
>> @@ -0,0 +1,57 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2016 PHYTEC Messtechnik
>> + * Author: Christian Hemp <c.hemp at phytec.de> */
>> +
>> +#include <dt-bindings/input/input.h>
>> +
>> +/ {
>> + gpio_keys: gpio-keys {
>> + compatible = "gpio-key";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_gpio_keys>;
>> + status = "disabled";
>> +
>> + power {
>> + label = "Power Button";
>> + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
>> + linux,code = <KEY_POWER>;
>> + wakeup-source;
>> + };
>> + };
>> +
>> + user_leds: user-leds {
>> + compatible = "gpio-leds";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_user_leds>;
>> + status = "disabled";
>> +
>> + user-led1 {
>> + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "gpio";
>> + default-state = "on";
>> + };
>> +
>> + user-led2 {
>> + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "gpio";
>> + default-state = "on";
>> + };
>> + };
>> +};
>> +
>> +&iomuxc {
>> + pinctrl_gpio_keys: gpio_keysgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79
>> + >;
>> + };
>> +
>> + pinctrl_user_leds: user_ledsgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x79
>> + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79
>> + >;
>> + };
>> +};
>> diff --git a/arch/arm/dts/imx6ul-phytec-segin.dtsi
>> b/arch/arm/dts/imx6ul-phytec-segin.dtsi
>> new file mode 100644
>> index 0000000000..8d5f8dc6ad
>> --- /dev/null
>> +++ b/arch/arm/dts/imx6ul-phytec-segin.dtsi
>> @@ -0,0 +1,346 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2016 PHYTEC Messtechnik GmbH
>> + * Author: Christian Hemp <c.hemp at phytec.de> */
>> +
>> +/ {
>> + model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite";
>> + compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063",
>> +"fsl,imx6ul";
>> +
>> + aliases {
>> + rtc0 = &i2c_rtc;
>> + rtc1 = &snvs_rtc;
>> + };
>> +
>> + reg_sound_1v8: regulator-1v8 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "i2s-audio-1v8";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + status = "disabled";
>> + };
>> +
>> + reg_sound_3v3: regulator-3v3 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "i2s-audio-3v3";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + status = "disabled";
>> + };
>> +
>> + reg_can1_en: regulator-can1 {
>> + compatible = "regulator-fixed";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&princtrl_flexcan1_en>;
>> + regulator-name = "Can";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + status = "disabled";
>> + };
>> +
>> + reg_adc1_vref_3v3: regulator-vref-3v3 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vref-3v3";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + };
>> +
>> + sound: sound {
>> + compatible = "simple-audio-card";
>> + simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
>> + simple-audio-card,format = "i2s";
>> + simple-audio-card,bitclock-master = <&dailink_master>;
>> + simple-audio-card,frame-master = <&dailink_master>;
>> + simple-audio-card,widgets =
>> + "Line", "Line In",
>> + "Line", "Line Out",
>> + "Speaker", "Speaker";
>> + simple-audio-card,routing =
>> + "Line Out", "LLOUT",
>> + "Line Out", "RLOUT",
>> + "Speaker", "SPOP",
>> + "Speaker", "SPOM",
>> + "LINE1L", "Line In",
>> + "LINE1R", "Line In";
>> + status = "disabled";
>> +
>> + simple-audio-card,cpu {
>> + sound-dai = <&sai2>;
>> + };
>> +
>> + dailink_master: simple-audio-card,codec {
>> + sound-dai = <&tlv320>;
>> + clocks = <&clks IMX6UL_CLK_SAI2>;
>> + };
>> + };
>> +
>> +};
>> +
>> +&adc1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_adc1>;
>> + vref-supply = <®_adc1_vref_3v3>;
>> + /*
>> + * driver can not separate a specific channel so we request 4 channels
>> + * here - we need only the fourth channel
>> + */
>> + num-channels = <4>;
>> + status = "disabled";
>> +};
>> +
>> +&can1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_flexcan1>;
>> + xceiver-supply = <®_can1_en>;
>> + status = "disabled";
>> +};
>> +
>> +&clks {
>> + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
>> + assigned-clock-rates = <786432000>;
>> +};
>> +
>> +&ecspi3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_ecspi3>;
>> + cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
>> + status = "disabled";
>> +};
>> +
>> +&fec2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_enet2>;
>> + phy-mode = "rmii";
>> + phy-handle = <ðphy2>;
>> + status = "disabled";
>> +};
>> +
>> +&i2c1 {
>> + tlv320: codec at 18 {
>> + compatible = "ti,tlv320aic3007";
>> + #sound-dai-cells = <0>;
>> + reg = <0x18>;
>> + AVDD-supply = <®_sound_3v3>;
>> + IOVDD-supply = <®_sound_3v3>;
>> + DRVDD-supply = <®_sound_3v3>;
>> + DVDD-supply = <®_sound_1v8>;
>> + status = "disabled";
>> + };
>> +
>> + stmpe: touchscreen at 44 {
>> + compatible = "st,stmpe811";
>> + reg = <0x44>;
>> + interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
>> + interrupt-parent = <&gpio5>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_stmpe>;
>> + status = "disabled";
>> +
>> + touchscreen {
>> + compatible = "st,stmpe-ts";
>> + st,sample-time = <4>;
>> + st,mod-12b = <1>;
>> + st,ref-sel = <0>;
>> + st,adc-freq = <1>;
>> + st,ave-ctrl = <1>;
>> + st,touch-det-delay = <2>;
>> + st,settling = <2>;
>> + st,fraction-z = <7>;
>> + st,i-drive = <1>;
>> + touchscreen-inverted-x = <1>;
>> + touchscreen-inverted-y = <1>;
>> + };
>> + };
>> +
>> + i2c_rtc: rtc at 68 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_rtc_int>;
>> + compatible = "microcrystal,rv4162";
>> + reg = <0x68>;
>> + interrupt-parent = <&gpio5>;
>> + interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
>> + status = "disabled";
>> + };
>> +};
>> +
>> +&mdio {
>> + ethphy2: ethernet-phy at 2 {
>> + reg = <2>;
>> + micrel,led-mode = <1>;
>> + clocks = <&clks IMX6UL_CLK_ENET2_REF>;
>> + clock-names = "rmii-ref";
>> + status = "disabled";
>> + };
>> +};
>> +
>> +&pwm3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pwm3>;
>> + status = "disabled";
>> +};
>> +
>> +&sai2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_sai2>;
>> + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
>> + <&clks IMX6UL_CLK_SAI2>;
>> + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
>> + assigned-clock-rates = <0>, <19200000>;
>> + fsl,sai-mclk-direction-output;
>> + status = "disabled";
>> +};
>> +
>> +&uart5 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart5>;
>> + uart-has-rtscts;
>> + status = "disabled";
>> +};
>> +
>> +&usbotg1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usb_otg1_id>;
>> + dr_mode = "otg";
>> + status = "disabled";
>> +};
>> +
>> +&usbotg2 {
>> + dr_mode = "host";
>> + disable-over-current;
>> + status = "disabled";
>> +};
>> +
>> +&usdhc1 {
>> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> + pinctrl-0 = <&pinctrl_usdhc1>;
>> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
>> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>> + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
>> + no-1-8-v;
>> + keep-power-in-suspend;
>> + wakeup-source;
>> + status = "disabled";
>> +};
>> +
>> +&iomuxc {
>> + pinctrl_adc1: adc1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
>> + >;
>> + };
>> +
>> + pinctrl_ecspi3: ecspi3grp {
>> + fsl,pins = <
>> + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
>> + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
>> + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
>> + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
>> + >;
>> + };
>> +
>> + pinctrl_enet2: enet2grp {
>> + fsl,pins = <
>> + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
>> + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
>> + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
>> + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
>> + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
>> + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
>> + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
>> + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2
>> 0x4001b010
>> + >;
>> + };
>> +
>> + pinctrl_flexcan1: flexcan1 {
>> + fsl,pins = <
>> + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
>> + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
>> + >;
>> + };
>> +
>> + princtrl_flexcan1_en: flexcan1engrp {
>> + fsl,pins = <
>> + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_pwm3: pwm3grp {
>> + fsl,pins = <
>> + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0
>> + >;
>> + };
>> +
>> + pinctrl_rtc_int: rtcintgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_sai2: sai2grp {
>> + fsl,pins = <
>> + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
>> + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
>> + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
>> + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
>> + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
>> + >;
>> + };
>> +
>> + pinctrl_stmpe: stmpegrp {
>> + fsl,pins = <
>> + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_uart5: uart5grp {
>> + fsl,pins = <
>> + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
>> + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
>> + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
>> + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_usb_otg1_id: usbotg1idgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1: usdhc1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>> + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>> + >;
>> + };
>> +};
>> diff --git a/arch/arm/dts/imx6ull-phycore-segin.dts
>> b/arch/arm/dts/imx6ull-phycore-segin.dts
>> deleted file mode 100644
>> index 6df3ad2e4a..0000000000
>> --- a/arch/arm/dts/imx6ull-phycore-segin.dts
>> +++ /dev/null
>> @@ -1,70 +0,0 @@
>> -// SPDX-License-Identifier: GPL-2.0+
>> -/*
>> - * Copyright (C) 2019 Parthiban Nallathambi <parthitce at gmail.com>
>> - */
>> -
>> -/dts-v1/;
>> -
>> -#include "imx6ull.dtsi"
>> -#include "pcl063-common.dtsi"
>> -
>> -/ {
>> - model = "Phytec phyBOARD-i.MX6ULL-Segin SBC";
>> - compatible = "phytec,phyboard-imx6ull-segin", "phytec,imx6ull-pcl063",
>> - "fsl,imx6ull";
>> -};
>> -
>> -&i2c1 {
>> - i2c_rtc: rtc at 68 {
>> - compatible = "microcrystal,rv4162";
>> - reg = <0x68>;
>> - status = "okay";
>> - };
>> -};
>> -
>> -&uart5 {
>> - pinctrl-names = "default";
>> - pinctrl-0 = <&pinctrl_uart5>;
>> - uart-has-rtscts;
>> - status = "okay";
>> -};
>> -
>> -&usdhc2 {
>> - status = "okay";
>> -};
>> -
>> -&usbotg1 {
>> - pinctrl-names = "default";
>> - pinctrl-0 = <&pinctrl_usb_otg1_id>;
>> - dr_mode = "otg";
>> - srp-disable;
>> - hnp-disable;
>> - adp-disable;
>> - status = "okay";
>> -};
>> -
>> -&usbotg2 {
>> - dr_mode = "host";
>> - disable-over-current;
>> - status = "okay";
>> -};
>> -
>> -&iomuxc {
>> - pinctrl-names = "default";
>> -
>> - pinctrl_uart5: uart5grp {
>> - fsl,pins = <
>> - MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
>> - MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
>> - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
>> - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
>> - >;
>> - };
>> -
>> - pinctrl_usb_otg1_id: usbotg1idgrp {
>> - fsl,pins = <
>> - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>> - >;
>> - };
>> -
>> -};
>> diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dtsi
>> b/arch/arm/dts/imx6ull-phytec-phycore-som.dtsi
>> new file mode 100644
>> index 0000000000..56cd16e5a7
>> --- /dev/null
>> +++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dtsi
>> @@ -0,0 +1,24 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (C) 2019 PHYTEC Messtechnik GmbH
>> + * Author: Stefan Riedmueller <s.riedmueller at phytec.de> */
>> +
>> +#include "imx6ul-phytec-phycore-som.dtsi"
>> +
>> +/ {
>> + model = "PHYTEC phyCORE-i.MX6 ULL";
>> + compatible = "phytec,imx6ull-pcl063", "fsl,imx6ull"; };
>> +
>> +&iomuxc {
>> + /delete-node/ gpioledssomgrp;
>> +};
>> +
>> +&iomuxc_snvs {
>> + pinctrl_gpioleds_som: gpioledssomgrp {
>> + fsl,pins = <
>> + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
>> + >;
>> + };
>> +};
>> diff --git a/arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
>> b/arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
>> new file mode 100644
>> index 0000000000..9648d4ecaf
>> --- /dev/null
>> +++ b/arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
>> @@ -0,0 +1,93 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (C) 2019 PHYTEC Messtechnik GmbH
>> + * Author: Stefan Riedmueller <s.riedmueller at phytec.de> */
>> +
>> +/dts-v1/;
>> +#include "imx6ull.dtsi"
>> +#include "imx6ull-phytec-phycore-som.dtsi"
>> +#include "imx6ull-phytec-segin.dtsi"
>> +#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
>> +
>> +/ {
>> + model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with
>> eMMC";
>> + compatible = "phytec,imx6ull-pbacd10-emmc",
>> "phytec,imx6ull-pbacd10",
>> + "phytec,imx6ull-pcl063","fsl,imx6ull";
>> +};
>> +
>> +&adc1 {
>> + status = "okay";
>> +};
>> +
>> +&can1 {
>> + status = "okay";
>> +};
>> +
>> +&tlv320 {
>> + status = "okay";
>> +};
>> +
>> +&ecspi3 {
>> + status = "okay";
>> +};
>> +
>> +ðphy1 {
>> + status = "okay";
>> +};
>> +
>> +ðphy2 {
>> + status = "okay";
>> +};
>> +
>> +&fec1 {
>> + status = "okay";
>> +};
>> +
>> +&fec2 {
>> + status = "okay";
>> +};
>> +
>> +&i2c_rtc {
>> + status = "okay";
>> +};
>> +
>> +®_can1_en {
>> + status = "okay";
>> +};
>> +
>> +®_sound_1v8 {
>> + status = "okay";
>> +};
>> +
>> +®_sound_3v3 {
>> + status = "okay";
>> +};
>> +
>> +&sai2 {
>> + status = "okay";
>> +};
>> +
>> +&sound {
>> + status = "okay";
>> +};
>> +
>> +&uart5 {
>> + status = "okay";
>> +};
>> +
>> +&usbotg1 {
>> + status = "okay";
>> +};
>> +
>> +&usbotg2 {
>> + status = "okay";
>> +};
>> +
>> +&usdhc1 {
>> + status = "okay";
>> +};
>> +
>> +&usdhc2 {
>> + status = "okay";
>> +};
>> diff --git a/arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
>> b/arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
>> new file mode 100644
>> index 0000000000..ff08d95a1a
>> --- /dev/null
>> +++ b/arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
>> @@ -0,0 +1,19 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (C) 2019 PHYTEC Messtechnik GmbH
>> + * Author: Stefan Riedmueller <s.riedmueller at phytec.de> */
>> +
>> +#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
>> +
>> +&iomuxc {
>> + /delete-node/ gpio_keysgrp;
>> +};
>> +
>> +&iomuxc_snvs {
>> + pinctrl_gpio_keys: gpio_keysgrp {
>> + fsl,pins = <
>> + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79
>> + >;
>> + };
>> +};
>> diff --git a/arch/arm/dts/imx6ull-phytec-segin.dtsi
>> b/arch/arm/dts/imx6ull-phytec-segin.dtsi
>> new file mode 100644
>> index 0000000000..c1595fc785
>> --- /dev/null
>> +++ b/arch/arm/dts/imx6ull-phytec-segin.dtsi
>> @@ -0,0 +1,38 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (C) 2019 PHYTEC Messtechnik GmbH
>> + * Author: Stefan Riedmueller <s.riedmueller at phytec.de> */
>> +
>> +#include "imx6ul-phytec-segin.dtsi"
>> +
>> +/ {
>> + model = "PHYTEC phyBOARD-Segin i.MX6 ULL";
>> + compatible = "phytec,imx6ull-pbacd-10",
>> +"phytec,imx6ull-pcl063","fsl,imx6ull";
>> +};
>> +
>> +&iomuxc {
>> + /delete-node/ flexcan1engrp;
>> + /delete-node/ rtcintgrp;
>> + /delete-node/ stmpegrp;
>> +};
>> +
>> +&iomuxc_snvs {
>> + princtrl_flexcan1_en: flexcan1engrp {
>> + fsl,pins = <
>> + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_rtc_int: rtcintgrp {
>> + fsl,pins = <
>> + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_stmpe: stmpegrp {
>> + fsl,pins = <
>> + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
>> + >;
>> + };
>> +};
>> diff --git a/board/phytec/pcl063/MAINTAINERS
>> b/board/phytec/pcl063/MAINTAINERS index 710b9680d4..02be541cc0
>> 100644
>> --- a/board/phytec/pcl063/MAINTAINERS
>> +++ b/board/phytec/pcl063/MAINTAINERS
>> @@ -2,10 +2,14 @@ PCL063 BOARD
>> M: Martyn Welch <martyn.welch at collabora.com>
>> M: Parthiban Nallathambi <parthitce at gmail.com>
>> S: Maintained
>> -F: arch/arm/dts/imx6ul-pcl063.dtsi
>> -F: arch/arm/dts/imx6ul-phycore-segin.dts
>> -F: arch/arm/dts/imx6ull-phycore-segin.dts
>> -F: arch/arm/dts/pcl063-common.dtsi
>> +F: arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
>> +F: arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
>> +F: arch/arm/dts/imx6ul-phytec-segin.dtsi
>> +F: arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
>> +F: arch/arm/dts/imx6ull-phytec-phycore-som.dtsi
>> +F: arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
>> +F: arch/arm/dts/imx6ull-phytec-segin.dtsi
>> +F: arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
>> F: arch/arm/dts/imx6ull-u-boot.dtsi
>> F: board/phytec/pcl063/
>> F: configs/phycore_pcl063_defconfig
>> diff --git a/configs/phycore_pcl063_defconfig
>> b/configs/phycore_pcl063_defconfig
>> index 4fdcf67efe..95959abcd7 100644
>> --- a/configs/phycore_pcl063_defconfig
>> +++ b/configs/phycore_pcl063_defconfig
>> @@ -27,13 +27,12 @@ CONFIG_CMD_MTD=y
>> CONFIG_CMD_USB=y
>> CONFIG_CMD_USB_SDP=y
>> CONFIG_CMD_CACHE=y
>> -CONFIG_CMD_NANDBCB=y
>> CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
>> CONFIG_MTDPARTS_DEFAULT="gpmi-nand:4m(uboot),1m(env),-(root)"
>> CONFIG_CMD_UBI=y
>> # CONFIG_ISO_PARTITION is not set
>> CONFIG_OF_CONTROL=y
>> -CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phycore-segin"
>> +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phytec-segin-ff-rdk-nand"
>> CONFIG_DM_I2C_GPIO=y
>> CONFIG_SYS_I2C_MXC=y
>> CONFIG_FSL_USDHC=y
>> diff --git a/configs/phycore_pcl063_ull_defconfig
>> b/configs/phycore_pcl063_ull_defconfig
>> index b516248a5f..11e1054ce7 100644
>> --- a/configs/phycore_pcl063_ull_defconfig
>> +++ b/configs/phycore_pcl063_ull_defconfig
>> @@ -28,7 +28,7 @@ CONFIG_CMD_USB_SDP=y
>> CONFIG_CMD_CACHE=y
>> # CONFIG_ISO_PARTITION is not set
>> CONFIG_OF_CONTROL=y
>> -CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phycore-segin"
>> +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phytec-segin-ff-rdk-emmc"
>> CONFIG_DM_I2C_GPIO=y
>> CONFIG_SYS_I2C_MXC=y
>> CONFIG_FSL_USDHC=y
>> --
>> 2.21.0
>
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