[PATCH] arm: dts: k3-j721e: ddr: Update to 0.2 version of DDR config tool

[Lokesh Vutla]

Update the ddr settings to use the DDR reg config tool rev 0.2.0.
This reduces the aging count(in DDRSS_CTL_274_DATA reg) to 15 in-order
to avoid DSS underflow errors.

Signed-off-by: Lokesh Vutla <lokeshvutla at ti.com>
Signed-off-by: Kevin Scholz <k-scholz at ti.com>
---
 arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi
index 135b6193a9..5ac32a0ffa 100644
--- a/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi
+++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- * This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.1.0
- * This file was generated on 09/06/2019
+ * This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.2.0
+ * This file was generated on 10/09/2019
 */
 
 #define DDRSS_PLL_FHS_CNT 10
@@ -283,7 +283,7 @@
 #define DDRSS_CTL_271_DATA 0x1FFF1000
 #define DDRSS_CTL_272_DATA 0x01FF0000
 #define DDRSS_CTL_273_DATA 0x000101FF
-#define DDRSS_CTL_274_DATA 0xFFFF0B00
+#define DDRSS_CTL_274_DATA 0x0FFF0B00
 #define DDRSS_CTL_275_DATA 0x01010001
 #define DDRSS_CTL_276_DATA 0x01010101
 #define DDRSS_CTL_277_DATA 0x01180101
-- 
2.23.0