[U-Boot] arm: Round the dma_alloc_coherent memory size to cache line aligned

[Tom Rini]

On Fri, Jan 04, 2019 at 09:24:14AM +0000, Ye Li wrote:

> When running usb dwc3 gadget driver, we meet random USB enumeration failure in fastboot.
> The root cause is a cache coherence issue. When it happens, the ctrl_req in
> gadget driver is allocated at 0xfe932f40, and the usb_composite_dev (cdev)
> is allocated at 0xfe932f60. So after we submit the setup request (cache flushed) to USB
> controller, any accessing to usb_composite_dev variable will cause the cache line refill, then
> when setup transfer is completed, reading the setup data in ctrl_req will gets old value from
> cache not from memory.
> 
> The ctrl_req is allocated by API dma_alloc_coherent, but u-boot don't have cohernet memory.
> so it still needs cache maintain operations before/after HW accessing. Since the cache flush or
> invalidate bases on cache line, so when the allocated memory size is not cache line aligned,
> potentially it may meet such issue.
> 
> This patch modifies the dma_alloc_coherent API to round the size to cache line aligned.
> 
> Signed-off-by: Ye Li <ye.li at nxp.com>
> Reviewed-by: Peng Fan <peng.fan at nxp.com>

Applied to u-boot/master, thanks!

-- 
Tom
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