[U-Boot] [PATCH 0/7] mmc: sunxi: Enable DM_MMC

Jagan Teki jagan at amarulasolutions.com
Mon Jan 14 10:10:37 UTC 2019


On Mon, Jan 14, 2019 at 3:05 PM Priit Laes <plaes at plaes.org> wrote:
>
> On Fri, Jan 11, 2019 at 11:34:07PM +0530, Jagan Teki wrote:
> > I thought of waiting this till CLK framework gets Mainline,
> > but migration deadline for DM_MMC and BLK seems expiring in
> > next release. So instead of doing so huddle  and make some last
> > minute changes, I have managed to add CLK, Reset code for mmc
> > driver via driver data.
>
> U-Boot 2019.01-rc3-00084-g0ce29380cf (Jan 14 2019 - 11:22:13 +0200) Allwinner Technology
>
> CPU:   Allwinner A20 (SUN7I)
> Model: Olimex A20-OLinuXino-LIME2-eMMC
> I2C:   ready
> DRAM:  1 GiB
> MMC:   mmc at 1c0f000: 0, mmc at 1c11000: 1
> Loading Environment from FAT... Card did not respond to voltage select!
>
> eMMC seems to be broken:
> => mmc list
> mmc at 1c0f000: 0
> mmc at 1c11000: 1
> => mmc dev 1
> => mmc dev 0
> MMC: no card present
> => mmc part
> MMC: no card present
> => mmc info
> MMC: no card present

Can you try this
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 33f1ec5e5a..7fab88c47f 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -648,7 +648,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
        gate_reg = (void *)ccu_reg + priv->variant->gate_offset;
        setbits_le32(gate_reg, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));

-       if ((!IS_ENABLED(CONFIG_MACH_SUN4I)) && priv->variant->has_reset) {
+       if ((!IS_ENABLED(CONFIG_MACH_SUN7I)) && priv->variant->has_reset) {
                reset_reg = (void *)ccu_reg + priv->variant->reset_offset;
                setbits_le32(reset_reg, BIT(priv->mmc_no +
                             priv->variant->reset_start_bit));

>
> Setting up a 640x480 dvi console (overscan 0x0)
> In:    serial
> Out:   vga
> Err:   vga
> Allwinner mUSB OTG (Peripheral)
> SCSI:  SATA link 0 timeout.
> AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
> flags: ncq stag pm led clo only pmp pio slum part ccc apst
>
> Net:   sunxi_set_gate: (CLK#66) unhandled
> eth0: ethernet at 1c50000
>
>
> And also CLK#66 message

This is expected, looking EMAC clock from dw driver, will handle in
next series. to be noted we enable print.


More information about the U-Boot mailing list