[U-Boot] [PATCH 2/2] MSCC: Remove reset.c

[Daniel Schwierzeck]

Am 15.01.19 um 17:33 schrieb Horatiu Vultur:
> Remove reset.c because it is not used anymore. It is superseed by
> sysreset driver.
> 
> Signed-off-by: Horatiu Vultur <horatiu.vultur at microchip.com>
> ---
>  arch/mips/mach-mscc/Makefile           |  2 +-
>  arch/mips/mach-mscc/include/mach/ddr.h | 18 ++++++++++++-
>  arch/mips/mach-mscc/reset.c            | 47 ----------------------------------
>  3 files changed, 18 insertions(+), 49 deletions(-)
>  delete mode 100644 arch/mips/mach-mscc/reset.c
> 
> diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
> index f5b6968..349e889 100644
> --- a/arch/mips/mach-mscc/Makefile
> +++ b/arch/mips/mach-mscc/Makefile
> @@ -2,6 +2,6 @@
>  
>  CFLAGS_cpu.o += -finline-limit=64000
>  
> -obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
> +obj-y += cpu.o dram.o phy.o lowlevel_init.o
>  obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o gpio.o
>  obj-$(CONFIG_SOC_OCELOT) += gpio.o
> diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h
> index 7552acb..a2d20db 100644
> --- a/arch/mips/mach-mscc/include/mach/ddr.h
> +++ b/arch/mips/mach-mscc/include/mach/ddr.h
> @@ -415,6 +415,22 @@ static inline void hal_vcoreiii_ddr_reset_release(void)
>  	sleep_100ns(10000);
>  }
>  
> +static void ocelot_restart(void)
> +{
> +	register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
> +	(void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
> +
> +	/* Make sure VCore is NOT protected from reset */
> +	clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT);
> +
> +	/* Change to SPI bitbang for SPI reset workaround... */
> +	writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) |
> +	       ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE);
> +
> +	/* Do the global reset */
> +	writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST);
> +}
> +
>  /*
>   * DDR memory sanity checking failed, tally and do hard reset
>   *
> @@ -443,7 +459,7 @@ static inline void hal_vcoreiii_ddr_failed(void)
>  	 * MIPS CPU (and the cache), and the CPU will start executing
>  	 * from the reset vector.
>  	 */
> -	reset = KSEG0ADDR(_machine_restart);
> +	reset = KSEG0ADDR(ocelot_restart);

ah I didn't thought about that when suggesting a sysreset driver.Then
it's maybe not a good idea at all. Or you export a function declaration
like mscc_cpu_reset(void) and implement it for each MSCC SoC. You could
call this still in hal_vcoreiii_ddr_failed() context. The sysreset
driver then simply wraps this function. But then it's not really worth
the overhead. Sorry for the troubles ;)

>  	icache_lock((void *)reset, 128);
>  	asm volatile ("jr %0"::"r" (reset));
>  
> diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c
> deleted file mode 100644
> index e0e610a..0000000
> --- a/arch/mips/mach-mscc/reset.c
> +++ /dev/null
> @@ -1,47 +0,0 @@
> -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> -/*
> - * Copyright (c) 2018 Microsemi Corporation
> - */
> -
> -#include <common.h>
> -
> -#include <asm/sections.h>
> -#include <asm/io.h>
> -
> -#include <asm/reboot.h>
> -
> -void _machine_restart(void)
> -{
> -#if defined(CONFIG_SOC_JR2)
> -	register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
> -	/* Set owner */
> -	reg &= ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M;
> -	reg |= ICPU_GENERAL_CTRL_IF_SI_OWNER(1);
> -	/* Set boot mode */
> -	reg |= ICPU_GENERAL_CTRL_BOOT_MODE_ENA;
> -	writel(reg, BASE_CFG + ICPU_GENERAL_CTRL);
> -	/* Read back in order to make BOOT mode setting active */
> -	reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
> -	/* Reset CPU only - still executing _here_. but from cache */
> -	writel(readl(BASE_CFG + ICPU_RESET) |
> -	       ICPU_RESET_CORE_RST_CPU_ONLY |
> -	       ICPU_RESET_CORE_RST_FORCE,
> -	       BASE_CFG + ICPU_RESET);
> -#else
> -	register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
> -	(void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
> -
> -	/* Make sure VCore is NOT protected from reset */
> -	clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT);
> -
> -	/* Change to SPI bitbang for SPI reset workaround... */
> -	writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) |
> -	       ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE);
> -
> -	/* Do the global reset */
> -	writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST);
> -#endif
> -
> -	while (1)
> -		; /* NOP */
> -}
> 

-- 
- Daniel