[U-Boot] [PATCH v2 04/21] vybrid: clock: Provide enable_i2c_clk() function for Vybrid
Lukasz Majewski
lukma at denx.de
Sun Jan 20 13:34:08 UTC 2019
Provide function to enable I2C2 clock for vf610 (BK4) - in the
generic code.
Signed-off-by: Lukasz Majewski <lukma at denx.de>
---
Changes in v2: None
arch/arm/cpu/armv7/vf610/generic.c | 19 +++++++++++++++++++
arch/arm/include/asm/arch-vf610/clock.h | 3 +++
board/phytec/pcm052/pcm052.c | 2 +-
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index cbd3391918..f1e6c7816e 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -375,3 +375,22 @@ void enable_caches(void)
mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
}
#endif
+
+#ifdef CONFIG_SYS_I2C_MXC
+/* i2c_num can be from 0 - 3 */
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+
+ switch (i2c_num) {
+ case 2:
+ clrsetbits_le32(&ccm->ccgr10, CCM_CCGR10_I2C2_CTRL_MASK,
+ CCM_CCGR10_I2C2_CTRL_MASK);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h
index 3bd73a01f3..72184fd608 100644
--- a/arch/arm/include/asm/arch-vf610/clock.h
+++ b/arch/arm/include/asm/arch-vf610/clock.h
@@ -22,6 +22,9 @@ enum mxc_clock {
void enable_ocotp_clk(unsigned char enable);
unsigned int mxc_get_clock(enum mxc_clock clk);
u32 get_lpuart_clk(void);
+#ifdef CONFIG_SYS_I2C_MXC
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
+#endif
#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index f988af2abc..cfc8009102 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -485,7 +485,7 @@ static void clock_init(void)
clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
- CCM_CCGR10_NFC_CTRL_MASK | CCM_CCGR10_I2C2_CTRL_MASK);
+ CCM_CCGR10_NFC_CTRL_MASK);
clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
--
2.11.0
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