[U-Boot] [PATCH] am335x: chilisom: Initial support for different DDR3 chips
Maciej Zagrabski
maciej.zagrabski at grinn-global.com
Mon Jan 21 11:28:42 UTC 2019
Manufacturing process changes caused that several versions
of chiliSOM with different memory chips are present on market.
Patch introduces method for selecting actual memory chip
on som through Kconfig. Patch creates space for adding more
memory chips in future.
Memory chip configuration is constructed by preprocesor
basing on DDR3 part no from Kconfig. To do this,
Makefile translates string from Kconfig into preprocesor token.
Signed-off-by: Maciej Zagrabski <maciej.zagrabski at grinn-global.com>
---
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 16 ++++++++++
arch/arm/mach-omap2/am33xx/Kconfig | 21 +++++++++++++
arch/arm/mach-omap2/am33xx/Makefile | 1 +
arch/arm/mach-omap2/am33xx/chilisom.c | 48 ++++++++++++++++-------------
4 files changed, 64 insertions(+), 22 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index d8ddecc0bd2..94c1fac9a24 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -154,6 +154,22 @@
#define K4B2G1646EBIH9_PHY_WR_DATA 0x76
#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
+/* Samsung K4B4G1646D-BIK0 */
+#define K4B4G1646DBIK0_EMIF_READ_LATENCY 0x100007
+#define K4B4G1646DBIK0_EMIF_TIM1 0x0AAAE51B
+#define K4B4G1646DBIK0_EMIF_TIM2 0x2A6B7FDA
+#define K4B4G1646DBIK0_EMIF_TIM3 0x501F867F
+#define K4B4G1646DBIK0_EMIF_SDCFG 0x61C05332
+#define K4B4G1646DBIK0_EMIF_SDREF 0xC30
+#define K4B4G1646DBIK0_ZQ_CFG 0x50074BE4
+#define K4B4G1646DBIK0_RATIO 0x80
+#define K4B4G1646DBIK0_INVERT_CLKOUT 0x0
+#define K4B4G1646DBIK0_RD_DQS 0x3C
+#define K4B4G1646DBIK0_WR_DQS 0x38
+#define K4B4G1646DBIK0_PHY_FIFO_WE 0x98
+#define K4B4G1646DBIK0_PHY_WR_DATA 0x73
+#define K4B4G1646DBIK0_IOCTRL_VALUE 0x18B
+
#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294
#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 57284c4ae12..535bcd6c3d0 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -24,6 +24,27 @@ config AM33XX_CHILISOM
bool
select SUPPORT_SPL
+if AM33XX_CHILISOM
+
+choice
+ prompt "DDR3 chip on chiliSOM"
+ default CHILISOM_MT41K256M16HA125E
+
+config CHILISOM_MT41K256M16HA125E
+ bool "Micron MT41K256"
+
+config CHILISOM_K4B4G1646DBIK0
+ bool "Samsung K4B4G1646"
+
+endchoice
+
+config CHILISOM_DDR3_CHIP_NAME
+ string
+ default K4B4G1646DBIK0 if CHILISOM_K4B4G1646DBIK0
+ default MT41K256M16HA125E
+
+endif
+
choice
prompt "AM33xx board select"
diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile
index 61c76d045f3..81c7a82f21e 100644
--- a/arch/arm/mach-omap2/am33xx/Makefile
+++ b/arch/arm/mach-omap2/am33xx/Makefile
@@ -26,3 +26,4 @@ obj-y += fdt.o
obj-$(CONFIG_CLOCK_SYNTHESIZER) += clk_synthesizer.o
obj-$(CONFIG_AM33XX_CHILISOM) += chilisom.o
+CFLAGS_chilisom.o := -DCHILISOM_DDR3_CHIP_NAME=$(CONFIG_CHILISOM_DDR3_CHIP_NAME)
diff --git a/arch/arm/mach-omap2/am33xx/chilisom.c b/arch/arm/mach-omap2/am33xx/chilisom.c
index 39423051088..3cfb611cc89 100644
--- a/arch/arm/mach-omap2/am33xx/chilisom.c
+++ b/arch/arm/mach-omap2/am33xx/chilisom.c
@@ -23,6 +23,10 @@
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define DDR_NAME_TOKEN(CHIP, NAME) CHIP ## _ ## NAME
+#define DDR_NAME_UNWRAP(CHIP, NAME) DDR_NAME_TOKEN(CHIP, NAME)
+#define DDR_NAME(NAME) DDR_NAME_UNWRAP(CHILISOM_DDR3_CHIP_NAME, NAME)
+
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
static struct module_pin_mux i2c0_pin_mux[] = {
@@ -64,32 +68,32 @@ void chilisom_enable_pin_mux(void)
}
static const struct ddr_data ddr3_chilisom_data = {
- .datardsratio0 = MT41K256M16HA125E_RD_DQS,
- .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
- .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
- .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+ .datardsratio0 = DDR_NAME(RD_DQS),
+ .datawdsratio0 = DDR_NAME(WR_DQS),
+ .datafwsratio0 = DDR_NAME(PHY_FIFO_WE),
+ .datawrsratio0 = DDR_NAME(PHY_WR_DATA),
};
static const struct cmd_control ddr3_chilisom_cmd_ctrl_data = {
- .cmd0csratio = MT41K256M16HA125E_RATIO,
- .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+ .cmd0csratio = DDR_NAME(RATIO),
+ .cmd0iclkout = DDR_NAME(INVERT_CLKOUT),
- .cmd1csratio = MT41K256M16HA125E_RATIO,
- .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+ .cmd1csratio = DDR_NAME(RATIO),
+ .cmd1iclkout = DDR_NAME(INVERT_CLKOUT),
- .cmd2csratio = MT41K256M16HA125E_RATIO,
- .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+ .cmd2csratio = DDR_NAME(RATIO),
+ .cmd2iclkout = DDR_NAME(INVERT_CLKOUT),
};
static struct emif_regs ddr3_chilisom_emif_reg_data = {
- .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
- .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
- .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
- .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
- .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .sdram_config = DDR_NAME(EMIF_SDCFG),
+ .ref_ctrl = DDR_NAME(EMIF_SDREF),
+ .sdram_tim1 = DDR_NAME(EMIF_TIM1),
+ .sdram_tim2 = DDR_NAME(EMIF_TIM2),
+ .sdram_tim3 = DDR_NAME(EMIF_TIM3),
.ocp_config = 0x00141414,
- .zq_config = MT41K256M16HA125E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+ .zq_config = DDR_NAME(ZQ_CFG),
+ .emif_ddr_phy_ctlr_1 = DDR_NAME(EMIF_READ_LATENCY),
};
void chilisom_spl_board_init(void)
@@ -166,11 +170,11 @@ const struct dpll_params *get_dpll_ddr_params(void)
}
const struct ctrl_ioregs ioregs_chilisom = {
- .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm0ioctl = DDR_NAME(IOCTRL_VALUE),
+ .cm1ioctl = DDR_NAME(IOCTRL_VALUE),
+ .cm2ioctl = DDR_NAME(IOCTRL_VALUE),
+ .dt0ioctl = DDR_NAME(IOCTRL_VALUE),
+ .dt1ioctl = DDR_NAME(IOCTRL_VALUE),
};
void sdram_init(void)
--
2.11.0
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