[U-Boot] [PATCHv3 11/11] pci: ls_pcie_g4: add Workaround for A-011452

[Z.q. Hou]

From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>

For PCIe controllers with SRIOV, MSIx table entries of all the VFs
are not accessible if BAR size is set to less than 8MB.

This ERRATA is only for LX2160A Rev1.0 and will be fixed in Rev2.0.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
---
V3:
 - New patch.

 drivers/pci/pcie_layerscape_gen4.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c
index b530a9979c..3792dbdf55 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -378,6 +378,11 @@ static void ls_pcie_g4_ep_set_bar_size(struct ls_pcie_g4 *pcie, int pf,
 	u32 mask_l = lower_32_bits(~(size - 1));
 	u32 mask_h = upper_32_bits(~(size - 1));
 
+	/* A-011452 workaround: set the VF BAR1 to 8MB */
+	if (pcie->rev == REV_1_0 && vf_bar && bar == 1) {
+		mask_l = lower_32_bits(~(SZ_8M - 1));
+		mask_h = upper_32_bits(~(SZ_8M - 1));
+	}
 	ccsr_writel(pcie, GPEX_BAR_SELECT, bar_pos);
 	ccsr_writel(pcie, GPEX_BAR_SIZE_LDW, mask_l);
 	ccsr_writel(pcie, GPEX_BAR_SIZE_UDW, mask_h);
-- 
2.17.1